QNX IPC: Vayu - Add DSP1 MMU1 Programming
[ipc/ipcdev.git] / qnx / src / ipc3x_dev / ti / syslink / family / vayu / vayudsp / VAYUDspHalMmu.c
1 /*
2  *  @file   VayuDspHalMmu.c
3  *
4  *  @brief      Hardware abstraction for Memory Management Unit module.
5  *
6  *              This module is responsible for handling slave MMU-related
7  *              hardware- specific operations.
8  *              The implementation is specific to VAYUDSP.
9  *
10  *
11  *  ============================================================================
12  *
13  *  Copyright (c) 2013, Texas Instruments Incorporated
14  *
15  *  Redistribution and use in source and binary forms, with or without
16  *  modification, are permitted provided that the following conditions
17  *  are met:
18  *
19  *  *  Redistributions of source code must retain the above copyright
20  *     notice, this list of conditions and the following disclaimer.
21  *
22  *  *  Redistributions in binary form must reproduce the above copyright
23  *     notice, this list of conditions and the following disclaimer in the
24  *     documentation and/or other materials provided with the distribution.
25  *
26  *  *  Neither the name of Texas Instruments Incorporated nor the names of
27  *     its contributors may be used to endorse or promote products derived
28  *     from this software without specific prior written permission.
29  *
30  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
32  *  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33  *  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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50  */
54 /* Standard headers */
55 #include <ti/syslink/Std.h>
57 /* OSAL and utils headers */
58 #include <ti/syslink/utils/List.h>
59 #include <ti/syslink/utils/Trace.h>
60 #include <ti/syslink/utils/OsalPrint.h>
61 #include <ti/syslink/utils/Memory.h>
62 #include <Bitops.h>
64 /* Module level headers */
65 #include <_ProcDefs.h>
66 #include <Processor.h>
68 /* Hardware Abstraction Layer headers */
69 #include <VAYUDspHal.h>
70 #include <VAYUDspHalMmu.h>
71 #include <VAYUDspPhyShmem.h>
72 #include <VAYUDspEnabler.h>
73 #include <MMUAccInt.h>
76 #if defined (__cplusplus)
77 extern "C" {
78 #endif
81 /* =============================================================================
82  *  Macros and types
83  * =============================================================================
84  */
85 /*!
86  * @brief Defines default mixedSize i.e same types of pages in one segment
87  */
88 #define MMU_RAM_DEFAULT         0
90 #define MPU_INT_OFFSET               32
92 /*!
93  *  @brief  Interrupt Id for DSP MMU faults
94  */
95 #define MMU_FAULT_INTR_DSP1_MMU0     60
96 #define MMU_FAULT_INTR_DSP1_MMU1     143
97 #define MMU_XBAR_INTR_DSP1_MMU1      145
99 /*!
100  *  @brief  CAM register field values
101  */
102 #define MMU_CAM_PRESERVE          (1 << 3)
103 #define MMU_CAM_VALID             (1 << 2)
105 #define IOPTE_SHIFT     12
106 #define IOPTE_SIZE      (1 << IOPTE_SHIFT)
107 #define IOPTE_MASK      (~(IOPTE_SIZE - 1))
108 #define IOPAGE_MASK     IOPTE_MASK
110 #define MMU_SECTION_ADDR_MASK    0xFFF00000
111 #define MMU_SSECTION_ADDR_MASK   0xFF000000
112 #define MMU_PAGE_TABLE_MASK      0xFFFFFC00
113 #define MMU_LARGE_PAGE_MASK      0xFFFF0000
114 #define MMU_SMALL_PAGE_MASK      0xFFFFF000
116 /*!
117  * @brief returns page number based on physical address
118  */
119 #define ti_syslink_phys_to_page(phys)      pfn_to_page((phys) >> PAGE_SHIFT)
121 /*!
122  * @brief helper macros
123  */
124 #define SLAVEVIRTADDR(x)  ((x)->addr [ProcMgr_AddrType_SlaveVirt])
125 #define SLAVEPHYSADDR(x)  ((x)->addr [ProcMgr_AddrType_SlavePhys])
126 #define MASTERPHYSADDR(x) ((x)->addr [ProcMgr_AddrType_MasterPhys])
128 #define MMUPAGE_ALIGN(size, psz)  (((size) + psz - 1) & ~(psz -1))
130 /*!
131  *  @brief  offset in ctrl module to MMR LOCK reg.
132  */
133 #define CTRL_MODULE_MMR_OFFSET           0x544
135 /*!
136  *  @brief  offset in ctrl module to MPU INTs.
137  */
138 #define CTRL_MODULE_MPU_OFFSET           0xA4C
140 /*!
141  *  @brief  interrupt num at offset.
142  */
143 #define CTRL_MODULE_INT_BASE             0x8
145 /*!
146  *  @brief  interrupt num at offset.
147  */
148 #define CTRL_MODULE_INT_m_OFFSET(m)      CTRL_MODULE_MPU_OFFSET + \
149                                          ((((m) - CTRL_MODULE_INT_BASE) / 2) * 4) - \
150                                          (((m) > 131) ? 4 : 0)
152 /*!
153  *  @def    REG32
154  *  @brief  Regsiter access method.
155  */
156 #define REG32(x)        (*(volatile UInt32 *) (x))
158 /* =============================================================================
159  *  Forward declarations of internal functions
160  * =============================================================================
161  */
162 /* Enables the MMU for GEM Module. */
163 Int _VAYUDSP_halMmuEnable (VAYUDSP_HalObject * halObject,
164                             UInt32               numMemEntries,
165                             ProcMgr_AddrInfo *   memTable);
167 /* Disables the MMU for GEM Module. */
168 Int _VAYUDSP_halMmuDisable (VAYUDSP_HalObject * halObject);
170 /* Add entry in TWL. */
171 Int
172 _VAYUDSP_halMmuAddEntry (VAYUDSP_HalObject       * halObject,
173                           VAYUDSP_HalMmuEntryInfo * entry);
174 /* Add static entries in TWL. */
175 Int
176 _VAYUDSP_halMmuAddStaticEntries (VAYUDSP_HalObject * halObject,
177                                   UInt32               numMemEntries,
178                                   ProcMgr_AddrInfo *   memTable);
180 /* Delete entry from TLB. */
181 Int
182 _VAYUDSP_halMmuDeleteEntry (VAYUDSP_HalObject       * halObject,
183                              VAYUDSP_HalMmuEntryInfo * entry);
184 /* Set entry in to TLB. */
185 Int
186 _VAYUDSP_halMmuPteSet (VAYUDSP_HalObject       * halObject,
187                         VAYUDSP_HalMmuEntryInfo * setPteInfo);
190 /* =============================================================================
191  * APIs called by VAYUDSPPROC module
192  * =============================================================================
193  */
194 /*!
195  *  @brief      Function to control MMU operations for this slave device.
196  *
197  *  @param      halObj  Pointer to the HAL object
198  *  @param      cmd     MMU control command
199  *  @param      arg     Arguments specific to the MMU control command
200  *
201  *  @sa
202  */
203 Int
204 VAYUDSP_halMmuCtrl (Ptr halObj, Processor_MmuCtrlCmd cmd, Ptr args)
206         Int                  status     = PROCESSOR_SUCCESS;
207     VAYUDSP_HalObject * halObject  = NULL;
209     GT_3trace (curTrace, GT_ENTER, "VAYUDSP_halMmuCtrl", halObj, cmd, args);
211     GT_assert (curTrace, (halObj != NULL));
213     halObject = (VAYUDSP_HalObject *) halObj ;
215     switch (cmd) {
216         case Processor_MmuCtrlCmd_Enable:
217         {
218             VAYUDSP_HalMmuCtrlArgs_Enable * enableArgs;
219             enableArgs = (VAYUDSP_HalMmuCtrlArgs_Enable *) args;
220             halObject = (VAYUDSP_HalObject *) halObj;
221             status = _VAYUDSP_halMmuEnable (halObject,
222                                              enableArgs->numMemEntries,
223                                              enableArgs->memEntries);
225 #if !defined(SYSLINK_BUILD_OPTIMIZE)
226             if (status < 0) {
227                 /*! @retval PROCESSOR_E_FAIL Failed to configure DSP MMU. */
228                 status = PROCESSOR_E_FAIL;
229                 GT_setFailureReason (curTrace,
230                                      GT_4CLASS,
231                                      "VAYUDSP_halMmuCtrl",
232                                      status,
233                                      "Failed to configure DSP MMU"
234                                      "at _VAYUDSP_halMmuEnable");
235             }
236 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
237         }
238         break;
240         case Processor_MmuCtrlCmd_Disable:
241         {
242             /* args are not used. */
243             halObject = (VAYUDSP_HalObject *) halObj;
244             status = _VAYUDSP_halMmuDisable (halObject);
245 #if !defined(SYSLINK_BUILD_OPTIMIZE)
246             if (status < 0) {
247                 /*! @retval PROCESSOR_E_FAIL Failed to disable DSP MMU. */
248                 status = PROCESSOR_E_FAIL;
249                 GT_setFailureReason (curTrace,
250                                      GT_4CLASS,
251                                      "VAYUDSP_halMmuCtrl",
252                                      status,
253                                      "Failed to disable DSP MMU");
254             }
255 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
256         }
257         break ;
259         case Processor_MmuCtrlCmd_AddEntry:
260         {
261             VAYUDSP_HalMmuCtrlArgs_AddEntry * addEntry;
262             addEntry = (VAYUDSP_HalMmuCtrlArgs_AddEntry *) args;
264             halObject = (VAYUDSP_HalObject *) halObj;
265             /* Add the entry in TLB for new request */
266             //status = _VAYUDSP_halMmuAddEntry (halObject,addEntry) ;
267 #if !defined(SYSLINK_BUILD_OPTIMIZE)
268             if (status < 0) {
269                 /*! @retval PROCESSOR_E_FAIL Failed to dynamically add DSP MMU
270                  *                           entry. */
271                 status = PROCESSOR_E_FAIL;
272                 GT_setFailureReason (curTrace,
273                                      GT_4CLASS,
274                                      "VAYUDSP_halMmuCtrl",
275                                      status,
276                                      "Failed to dynamically add DSP MMU entry");
277             }
278 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
279         }
280         break;
282         case Processor_MmuCtrlCmd_DeleteEntry:
283         {
284             VAYUDSP_HalMmuCtrlArgs_DeleteEntry * deleteEntry;
285             deleteEntry = (VAYUDSP_HalMmuCtrlArgs_DeleteEntry *) args;
287             halObject = (VAYUDSP_HalObject *) halObj;
288             /* Add the entry in TLB for new request */
289             //status = _VAYUDSP_halMmuDeleteEntry (halObject,deleteEntry);
290 #if !defined(SYSLINK_BUILD_OPTIMIZE)
291             if (status < 0) {
292                 /*! @retval PROCESSOR_E_FAIL Failed to dynamically delete DSP
293                  *                           MMU entry  */
294                 status = PROCESSOR_E_FAIL;
295                 GT_setFailureReason (curTrace,
296                                      GT_4CLASS,
297                                      "VAYUDSP_halMmuCtrl",
298                                      status,
299                                      "Failed to dynamically add DSP MMU entry");
300             }
301 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
302         }
303         break;
305         default:
306         {
307             /*! @retval PROCESSOR_E_INVALIDARG Invalid argument */
308             status = PROCESSOR_E_INVALIDARG;
309             GT_setFailureReason (curTrace,
310                                  GT_4CLASS,
311                                  "VAYUDSP_halMmuCtrl",
312                                  status,
313                                  "Unsupported MMU ctrl cmd specified");
314         }
315         break;
316     }
318     GT_1trace (curTrace, GT_LEAVE, "VAYUDSP_halMmuCtrl",status);
320     /*! @retval PROCESSOR_SUCCESS Operation successful */
321     return status;
324 /* =============================================================================
325  * Internal functions
326  * =============================================================================
327  */
328 /*!
329  *  @brief      Enables and configures the DSP MMU as per provided memory map.
330  *
331  *  @param      halObject       Pointer to the HAL object
332  *  @param      numMemEntries   Number of memory entries in memTable
333  *  @param      memTable        Table of memory entries to be configured
334  *
335  *  @sa
336  */
337 Int
338 _VAYUDSP_halMmuAddStaticEntries (VAYUDSP_HalObject * halObject,
339                                   UInt32               numMemEntries,
340                                   ProcMgr_AddrInfo *   memTable)
342     Int                           status    = PROCESSOR_SUCCESS;
343     VAYUDSP_HalMmuEntryInfo      staticEntry;
344     UInt32                        i;
346     GT_3trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuAddStaticEntries",
347                halObject, numMemEntries, memTable);
349     GT_assert (curTrace, (halObject != NULL));
350     /* It is possible that numMemEntries may be 0, if user does not want to
351      * configure any default regions.
352      * memTable may also be NULL.
353      */
355     for (i = 0 ; i < numMemEntries && (status >= 0) ; i++) {
356         /* Configure the TLB */
357         if (memTable [i].size != 0) {
358             staticEntry.slaveVirtAddr =
359                                      SLAVEVIRTADDR (&memTable [i]);
360             staticEntry.size          = memTable[i].size;
361             staticEntry.masterPhyAddr =
362                                      MASTERPHYSADDR (&memTable [i]);
363             /*TBD : elementSize, endianism, mixedSized are hard
364              *      coded now, must be configurable later*/
365             staticEntry.elementSize   = MMU_RAM_ELSZ_16;
366             staticEntry.endianism     = LITTLE_ENDIAN;
367             staticEntry.mixedSize     = MMU_TLBES;
368             status = _VAYUDSP_halMmuAddEntry (halObject,
369                                                &staticEntry);
370             if (status < 0) {
371                 /*! @retval PROCESSOR_E_FAIL Failed to add MMU entry. */
372                 status = PROCESSOR_E_FAIL;
373                 GT_setFailureReason (curTrace,
374                                      GT_4CLASS,
375                                      "_VAYUDSP_halMmuAddStaticEntries",
376                                      status,
377                                      "Failed to add MMU entry!");
378             }
379         }
380     }
381     GT_1trace (curTrace, GT_LEAVE, "_VAYUDSP_halMmuAddStaticEntries", status);
383     /*! @retval PROCESSOR_SUCCESS Operation completed successfully. */
384     return status ;
388 /*!
389  *  @brief      Function to check and clear the remote proc interrupt
390  *
391  *  @param      arg     Optional argument to the function.
392  *
393  *  @sa         _VAYUDSP_halMmuInt_isr
394  */
395 static
396 Bool
397 _VAYUDSP_halMmuCheckAndClearFunc (Ptr arg)
399     VAYUDSP_HalObject * halObject = (VAYUDSP_HalObject *)arg;
400     VAYUDSP_HalMmuObject * mmuObj = &(halObject->mmu0Obj);
401     UInt32 mmuBase;
403     /* Check the interrupt status */
404     mmuObj->mmuIrqStatus = REG32(halObject->mmu0Base + MMU_MMU_IRQSTATUS_OFFSET);
405     mmuObj->mmuIrqStatus &= MMU_IRQ_MASK;
406     if (!(mmuObj->mmuIrqStatus)) {
407         mmuObj = &(halObject->mmu1Obj);
409         /* Check the interrupt status */
410         mmuObj->mmuIrqStatus = REG32(halObject->mmu1Base + MMU_MMU_IRQSTATUS_OFFSET);
411         mmuObj->mmuIrqStatus &= MMU_IRQ_MASK;
412         if (!(mmuObj->mmuIrqStatus)) {
413             return (FALSE);
414         }
415         else {
416             mmuBase = halObject->mmu1Base;
417             GT_0trace (curTrace, GT_4CLASS,
418                        "****************** DSP-MMU1 Fault ******************");
419         }
420     }
421     else {
422         mmuBase = halObject->mmu0Base;
423         GT_0trace (curTrace, GT_4CLASS,
424                    "****************** DSP-MMU0 Fault ******************");
425     }
427     /* Get the fault address. */
428     mmuObj->mmuFaultAddr = REG32(mmuBase + MMU_MMU_FAULT_AD_OFFSET);
430     /* Print the fault information */
431     GT_1trace (curTrace, GT_4CLASS,
432                "****    addr: 0x%x", mmuObj->mmuFaultAddr);
433     if (mmuObj->mmuIrqStatus & MMU_IRQ_TLBMISS)
434         GT_0trace (curTrace, GT_4CLASS, "****    TLBMISS");
435     if (mmuObj->mmuIrqStatus & MMU_IRQ_TRANSLATIONFAULT)
436         GT_0trace (curTrace, GT_4CLASS, "****    TRANSLATIONFAULT");
437     if (mmuObj->mmuIrqStatus & MMU_IRQ_EMUMISS)
438         GT_0trace (curTrace, GT_4CLASS, "****    EMUMISS");
439     if (mmuObj->mmuIrqStatus & MMU_IRQ_TABLEWALKFAULT)
440         GT_0trace (curTrace, GT_4CLASS, "****    TABLEWALKFAULT");
441     if (mmuObj->mmuIrqStatus & MMU_IRQ_MULTIHITFAULT)
442         GT_0trace (curTrace, GT_4CLASS, "****    MULTIHITFAULT");
443     GT_0trace (curTrace, GT_4CLASS,
444                "**************************************************");
446     /* Clear the interrupt and disable further interrupts. */
447     REG32(mmuBase + MMU_MMU_IRQENABLE_OFFSET) = 0x0;
448     REG32(mmuBase + MMU_MMU_IRQSTATUS_OFFSET) = mmuObj->mmuIrqStatus;
450     /* This is not a shared interrupt, so interrupt has always occurred */
451     /*! @retval TRUE Interrupt has occurred. */
452     return (TRUE);
455 /*!
456  *  @brief      Interrupt Service Routine for VAYUDSPHalMmu module
457  *
458  *  @param      arg     Optional argument to the function.
459  *
460  *  @sa         _VAYUDSP_halMmuCheckAndClearFunc
461  */
462 static
463 Bool
464 _VAYUDSP_halMmuInt_isr (Ptr arg)
466     VAYUDSP_HalObject * halObject = (VAYUDSP_HalObject *)arg;
467     VAYUDSPPROC_Object * procObject = NULL;
468     Int32 status;
470     GT_1trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuInt_isr", arg);
471     status = VAYUDSPPROC_open((VAYUDSPPROC_Handle *)&procObject, halObject->procId);
472     if (status >= 0) {
473         Processor_setState(procObject->procHandle, ProcMgr_State_Mmu_Fault);
474         VAYUDSPPROC_close((VAYUDSPPROC_Handle *)&procObject);
475     }
477     GT_1trace (curTrace, GT_LEAVE, "_VAYUDSP_halMmuInt_isr", TRUE);
479     /*! @retval TRUE Interrupt has been handled. */
480     return (TRUE);
483 /*!
484  *  @brief      Enables and configures the DSP MMU as per provided memory map.
485  *
486  *  @param      halObject       Pointer to the HAL object
487  *  @param      numMemEntries   Number of memory entries in memTable
488  *  @param      memTable        Table of memory entries to be configured
489  *
490  *  @sa
491  */
492 Int
493 _VAYUDSP_halMmuEnable (VAYUDSP_HalObject * halObject,
494                        UInt32               numMemEntries,
495                        ProcMgr_AddrInfo *   memTable)
497     Int                           status    = PROCESSOR_SUCCESS;
498     VAYUDSP_HalMmuObject *        mmu0Obj, *mmu1Obj;
499     OsalIsr_Params                isrParams;
500     UInt32 reg = 0;
502     GT_3trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuEnable",
503                halObject, numMemEntries, memTable);
505     GT_assert (curTrace, (halObject != NULL));
506     /* It is possible that numMemEntries may be 0, if user does not want to
507      * configure any default regions.
508      * memTable may also be NULL.
509      */
510     mmu0Obj = &(halObject->mmu0Obj);
511     mmu1Obj = &(halObject->mmu1Obj);
513     /* Program the MMR lock registers to access the SCM
514      * IRQ crossbar register address range */
515     REG32(halObject->ctrlModBase + CTRL_MODULE_MMR_OFFSET) = 0xF757FDC0;
517     /* Program the IntXbar */
518     reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1));
519     if ((MMU_FAULT_INTR_DSP1_MMU1 - CTRL_MODULE_INT_BASE) % 2) {
520         REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
521             (reg & 0x0000FFFF) | (MMU_XBAR_INTR_DSP1_MMU1 << 16);
522     }
523     else {
524         REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
525             (reg & 0xFFFF0000) | (MMU_XBAR_INTR_DSP1_MMU1);
526     }
528     /* Create the ISR to listen for MMU Faults */
529     isrParams.sharedInt        = FALSE;
530     isrParams.checkAndClearFxn = &_VAYUDSP_halMmuCheckAndClearFunc;
531     isrParams.fxnArgs          = halObject;
532     isrParams.intId            = MMU_FAULT_INTR_DSP1_MMU0;
533     mmu0Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
534                                         halObject,
535                                         &isrParams);
536     isrParams.intId            = MMU_FAULT_INTR_DSP1_MMU1;
537     mmu1Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
538                                         halObject,
539                                         &isrParams);
541 #if !defined(SYSLINK_BUILD_OPTIMIZE)
542     if (mmu0Obj->isrHandle == NULL || mmu1Obj->isrHandle == NULL) {
543         /*! @retval PROCESSOR_E_FAIL OsalIsr_create failed */
544         status = PROCESSOR_E_FAIL;
545         GT_setFailureReason (curTrace,
546                              GT_4CLASS,
547                              "_VAYUDSP_halMmuEnable",
548                              status,
549                              "OsalIsr_create failed");
550     }
551     else {
552 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
554         status = OsalIsr_install (mmu0Obj->isrHandle);
556 #if !defined(SYSLINK_BUILD_OPTIMIZE)
557         if (status < 0) {
558             GT_setFailureReason (curTrace,
559                                  GT_4CLASS,
560                                  "_VAYUDSP_halMmuEnable",
561                                  status,
562                                  "OsalIsr_install failed");
563         }
564         else {
565 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
567             status = OsalIsr_install (mmu1Obj->isrHandle);
569 #if !defined(SYSLINK_BUILD_OPTIMIZE)
570             if (status < 0) {
571                 GT_setFailureReason (curTrace,
572                                      GT_4CLASS,
573                                      "_VAYUDSP_halMmuEnable",
574                                      status,
575                                      "OsalIsr_install failed");
576             }
577         }
578 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
580         if ((status >= 0) && (numMemEntries != 0)) {
581             GT_1trace(curTrace, GT_4CLASS, "_VAYUDSP_halMmuEnable: adding %d entries...", numMemEntries);
583             /* Only statically created entries are being added here. */
584             status = _VAYUDSP_halMmuAddStaticEntries(halObject,
585                                                      numMemEntries,
586                                                      memTable);
587 #if !defined(SYSLINK_BUILD_OPTIMIZE)
588             if (status < 0) {
589                 /*! @retval PROCESSOR_E_FAIL Failed at
590                  *                         _VAYUDSP_halMmuAddStaticEntries. */
591                 status = PROCESSOR_E_FAIL;
592                 GT_setFailureReason (curTrace,
593                                      GT_4CLASS,
594                                      "_VAYUDSP_halMmuEnable",
595                                      status,
596                                      "_VAYUDSP_halMmuAddStaticEntries failed !");
597             }
598 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
599         }
600 #if !defined(SYSLINK_BUILD_OPTIMIZE)
601     }
602 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
604     GT_1trace (curTrace, GT_LEAVE, "_VAYUDSP_halMmuEnable", status);
606     /*! @retval PROCESSOR_SUCCESS Operation completed successfully. */
607     return status ;
611 /*!
612  *  @brief      Disables the DSP MMU.
613  *
614  *  @param      halObject       Pointer to the HAL object
615  *
616  *  @sa
617  */
618 Int
619 _VAYUDSP_halMmuDisable (VAYUDSP_HalObject * halObject)
621     Int                        status    = PROCESSOR_SUCCESS;
622     Int                        tmpStatus = PROCESSOR_SUCCESS;
623     VAYUDSP_HalMmuObject *     mmu0Obj, *mmu1Obj;
625     GT_1trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuDisable", halObject);
627     GT_assert (curTrace, (halObject != NULL));
628     mmu0Obj = &(halObject->mmu0Obj);
629     mmu1Obj = &(halObject->mmu1Obj);
631     status = OsalIsr_uninstall (mmu0Obj->isrHandle);
632 #if !defined(SYSLINK_BUILD_OPTIMIZE)
633     if (status < 0) {
634         GT_setFailureReason (curTrace,
635                              GT_4CLASS,
636                              "_VAYUDSP_halMmuDisable",
637                              status,
638                              "OsalIsr_uninstall failed");
639     }
640 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
642     status = OsalIsr_uninstall (mmu1Obj->isrHandle);
643 #if !defined(SYSLINK_BUILD_OPTIMIZE)
644     if (status < 0) {
645         GT_setFailureReason (curTrace,
646                              GT_4CLASS,
647                              "_VAYUDSP_halMmuDisable",
648                              status,
649                              "OsalIsr_uninstall failed");
650     }
651 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
653 #if !defined(SYSLINK_BUILD_OPTIMIZE)
654     tmpStatus =
655 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
656         OsalIsr_delete (&(mmu0Obj->isrHandle));
657 #if !defined(SYSLINK_BUILD_OPTIMIZE)
658     if ((status >= 0) && (tmpStatus < 0)) {
659         status = tmpStatus;
660         GT_setFailureReason (curTrace,
661                              GT_4CLASS,
662                              "_VAYUDSP_halMmuDisable",
663                              status,
664                              "OsalIsr_delete failed");
665     }
666 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
668 #if !defined(SYSLINK_BUILD_OPTIMIZE)
669     tmpStatus =
670 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
671         OsalIsr_delete (&(mmu1Obj->isrHandle));
672 #if !defined(SYSLINK_BUILD_OPTIMIZE)
673     if ((status >= 0) && (tmpStatus < 0)) {
674         status = tmpStatus;
675         GT_setFailureReason (curTrace,
676                              GT_4CLASS,
677                              "_VAYUDSP_halMmuDisable",
678                              status,
679                              "OsalIsr_delete failed");
680     }
681 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
683     GT_1trace (curTrace, GT_LEAVE, "_VAYUDSP_halMmuDisable", status);
685     /*! @retval PROCESSOR_SUCCESS Operation completed successfully. */
686     return status;
690 /*!
691  *  @brief      This function adds an MMU entry for the specfied address and
692  *              size.
693  *
694  *  @param      halObject   Pointer to the HAL object
695  *  @param      entry       entry to be added
696  *
697  *  @sa
698  */
699 Int
700 _VAYUDSP_halMmuAddEntry (VAYUDSP_HalObject       * halObject,
701                          VAYUDSP_HalMmuEntryInfo * entry)
703     Int                         status = PROCESSOR_SUCCESS;
704     UInt32  *                   ppgd = NULL;
705     UInt32  *                   ppte = NULL;
706     VAYUDSP_HalMmuEntryInfo     te;
707     VAYUDSP_HalMmuEntryInfo     currentEntry;
708     Int32                       currentEntrySize;
710     GT_2trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuAddEntry",
711                halObject, entry);
713     GT_assert (curTrace, (halObject != NULL));
714     GT_assert (curTrace, (entry     != NULL));
716     /* Add the entry (or entries) */
717     Memory_copy(&currentEntry,
718                 entry,
719                 sizeof(VAYUDSP_HalMmuEntryInfo));
721     /* Align the addresses to page size */
722     currentEntry.size += (currentEntry.slaveVirtAddr & (PAGE_SIZE_4KB -1));
723     currentEntry.slaveVirtAddr &= ~(PAGE_SIZE_4KB-1);
724     currentEntry.masterPhyAddr &= ~(PAGE_SIZE_4KB-1);
726     /* Align the size as well */
727     currentEntry.size = MMUPAGE_ALIGN(currentEntry.size, PAGE_SIZE_4KB);
728     currentEntrySize = currentEntry.size;
730     /* To find the max. page size with which both PA & VA are
731      * aligned */
732     while ((currentEntrySize != 0) &&
733            (status >= 0)) {
734         if (currentEntrySize >= PAGE_SIZE_16MB
735             && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_16MB - 1))) {
736             currentEntry.size = PAGE_SIZE_16MB;
737         }
738         else if (currentEntrySize >= PAGE_SIZE_1MB
739                  && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_1MB - 1))) {
740             currentEntry.size = PAGE_SIZE_1MB;
741         }
742         else if (currentEntrySize >= PAGE_SIZE_64KB
743                  && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_64KB - 1))){
744             currentEntry.size = PAGE_SIZE_64KB;
745         }
746         else  if (currentEntrySize >= PAGE_SIZE_4KB
747                  && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_4KB - 1))){
748             currentEntry.size = PAGE_SIZE_4KB;
749         }
750         else {
751             Osal_printf ("Configuration error: "
752                          " MMU entries must be aligned to their"
753                          "page size(4KB,"
754                          " 64KB, 1MB, or 16MB).\n");
755             Osal_printf ("Since the addresses are not aligned buffer"
756                          "of size: %x at address: %x cannot be  "
757                          "TLB entries\n",
758                        currentEntrySize, currentEntry.slaveVirtAddr);
759             /*! @retval VAYUDSPPROC_E_MMUCONFIG Memory region is not
760                                                  aligned to page size */
761             status = VAYUDSPPROC_E_MMUCONFIG;
762             GT_setFailureReason (curTrace,
763                               GT_4CLASS,
764                               "_VAYUDSP_halMmuAddEntry",
765                                status,
766                           "Memory region is not aligned to page size!");
767             break ;
768         }
770         /* DO NOT put this check under SYSLINK_BUILD_OPTIMIZE */
771         if (status >= 0) {
772             /* Lookup if the entry exists */
773             if (1) {//(!*ppgd || !*ppte) {
774                 /* Entry doesnot exists, insert this page */
775                 te.size = currentEntry.size;
776                 te.slaveVirtAddr = currentEntry.slaveVirtAddr;
777                 te.masterPhyAddr = currentEntry.masterPhyAddr;
778                 te.elementSize   = currentEntry.elementSize;
779                 te.endianism     = currentEntry.endianism;
780                 te.mixedSize     = currentEntry.mixedSize;
781                 status = _VAYUDSP_halMmuPteSet (halObject, &te);
782             }
783             else if (ppgd && ppte) {
784                 if (currentEntry.masterPhyAddr != (*ppte & IOPAGE_MASK)) {
785                     /* Entry doesnot exists, insert this page */
786                     te.size = currentEntry.size;
787                     te.slaveVirtAddr = currentEntry.slaveVirtAddr;
788                     te.masterPhyAddr = currentEntry.masterPhyAddr;
789                     te.elementSize   = currentEntry.elementSize;
790                     te.endianism     = currentEntry.endianism;
791                     te.mixedSize     = currentEntry.mixedSize;
792                     status = _VAYUDSP_halMmuPteSet (halObject, &te);
793                 }
794             }
796 #if !defined(SYSLINK_BUILD_OPTIMIZE)
797             if (status < 0) {
798                 GT_setFailureReason (
799                                 curTrace,
800                                 GT_4CLASS,
801                                 "_VAYUDSP_halMmuAddEntry",
802                                 status,
803                                 "Failed to in _VAYUDSP_halMmuPteSet!");
804                 break;
805             }
806             else {
807 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
808                 currentEntrySize           -= currentEntry.size;
809                 currentEntry.masterPhyAddr += currentEntry.size;
810                 currentEntry.slaveVirtAddr += currentEntry.size;
811 #if !defined(SYSLINK_BUILD_OPTIMIZE)
812             }
813 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
814         }
815     }
817     GT_1trace (curTrace, GT_LEAVE, "_VAYUDSP_halMmuAddEntry", status);
819     /*! @retval PROCESSOR_SUCCESS Operation completed successfully. */
820     return status;
824 /*!
825  *  @brief      This function deletes an MMU entry for the specfied address and
826  *              size.
827  *
828  *  @param      halObject   Pointer to the HAL object
829  *  @param      slaveVirtAddr DSP virtual address of the memory region
830  *  @param      size        Size of the memory region to be configured
831  *  @param      isDynamic   Is the MMU entry being dynamically added?
832  *
833  *  @sa
834  */
835 Int
836 _VAYUDSP_halMmuDeleteEntry (VAYUDSP_HalObject       * halObject,
837                             VAYUDSP_HalMmuEntryInfo * entry)
839     Int                         status      = PROCESSOR_SUCCESS;
840     UInt32 *                    iopgd       = NULL;
841     UInt32                      currentEntrySize;
842     VAYUDSP_HalMmuEntryInfo     currentEntry;
843     VAYUDSP_HalMmuObject *      mmu0Obj, *mmu1Obj;
844     //UInt32                      clearBytes = 0;
846     GT_2trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuDeleteEntry",
847                halObject, entry);
849     GT_assert (curTrace, (halObject            != NULL));
850     GT_assert (curTrace, (entry                != NULL));
851     GT_assert (curTrace, (entry->size          != 0));
853     mmu0Obj = &(halObject->mmu0Obj);
854     mmu1Obj = &(halObject->mmu1Obj);
856     /* Add the entry (or entries) */
857     Memory_copy(&currentEntry,
858                 entry,
859                 sizeof(VAYUDSP_HalMmuEntryInfo));
861     /* Align the addresses to page size */
862     currentEntry.size += (currentEntry.slaveVirtAddr & (PAGE_SIZE_4KB -1));
863     currentEntry.slaveVirtAddr &= ~(PAGE_SIZE_4KB-1);
865     /* Align the size as well */
866     currentEntry.size = MMUPAGE_ALIGN(currentEntry.size, PAGE_SIZE_4KB);
867     currentEntrySize = currentEntry.size;
869     /* To find the max. page size with which both PA & VA are
870      * aligned */
871     while ((currentEntrySize != 0)
872             && (status >= 0)) {
873         if (currentEntrySize >= PAGE_SIZE_16MB
874             && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_16MB - 1))) {
875             currentEntry.size = PAGE_SIZE_16MB;
876         }
877         else if (currentEntrySize >= PAGE_SIZE_1MB
878                  && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_1MB - 1))) {
879             currentEntry.size = PAGE_SIZE_1MB;
880         }
881         else if (currentEntrySize >= PAGE_SIZE_64KB
882                  && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_64KB - 1))){
883             currentEntry.size = PAGE_SIZE_64KB;
884         }
885         else  if (currentEntrySize >= PAGE_SIZE_4KB
886                  && !(currentEntry.slaveVirtAddr & (PAGE_SIZE_4KB - 1))){
887             currentEntry.size = PAGE_SIZE_4KB;
888         }
889         else {
890             Osal_printf ("Configuration error: "
891                          " MMU entries must be aligned to their"
892                          "page size(4KB,"
893                          " 64KB, 1MB, or 16MB).\n");
894             Osal_printf ("Since the addresses are not aligned buffer"
895                          "of size: %x at address: %x cannot be  "
896                          "TLB entries\n",
897                        currentEntrySize, currentEntry.slaveVirtAddr);
898             /*! @retval VAYUDSPPROC_E_MMUCONFIG Memory region is not
899                                                  aligned to page size */
900             status = VAYUDSPPROC_E_MMUCONFIG;
901             GT_setFailureReason (curTrace,
902                               GT_4CLASS,
903                               "_VAYUDSP_halMmuAddEntry",
904                                status,
905                           "Memory region is not aligned to page size!");
906             break ;
907         }
908         /* DO NOT put this check under SYSLINK_BUILD_OPTIMIZE */
909         if (status >= 0) {
910             /* Check every page if exists */
911             //iopgd = iopgd_offset(mmuObj->dspMmuHandler,
912             //                     currentEntry.slaveVirtAddr);
914             if (*iopgd) {
915                 /* Clear the requested page entry */
916                 //clearBytes = iopgtable_clear_entry(mmuObj->dspMmuHandler,
917                 //                      currentEntry.slaveVirtAddr);
918             }
920             currentEntry.slaveVirtAddr += currentEntry.size;
921             currentEntrySize           -= currentEntry.size;
922         }
923     }
925     GT_1trace (curTrace, GT_LEAVE, "_VAYUDSP_halMmuDeleteEntry", status);
927     /*! @retval PROCESSOR_SUCCESS Operation completed successfully. */
928     return status;
932 static ULONG HAL_MMU_PteAddrL1(const ULONG L1_base, const ULONG va)
934     ULONG TTB_13_to_7, VA_31_to_20, desc_13_to_0;
936     TTB_13_to_7  = L1_base & (0x7FUL << 13);
937     VA_31_to_20  = va >> (20 - 2); /* Left-shift by 2 here itself */
938     desc_13_to_0 = (TTB_13_to_7 + VA_31_to_20) & (0xFFFUL << 2);
940     return ( (L1_base & 0xFFFFC000) | desc_13_to_0 );
943 static ULONG HAL_MMU_PteAddrL2(const ULONG L2_base, const ULONG va)
945     return ( (L2_base & 0xFFFFFC00) | ( (va >> 10) & 0x3FC ) );
948 #define OUTREG32(x, y)      WRITE_REGISTER_ULONG(x, (ULONG)(y))
950 int VAYUDSP_InternalMMU_PteSet (const ULONG        pgTblVa,
951                                       struct iotlb_entry    *mapAttrs)
953     Int status = 0;
954     ULONG pteAddr, pteVal;
955     Int  numEntries = 1;
956     ULONG  physicalAddr = mapAttrs->pa;
957     ULONG  virtualAddr  = mapAttrs->da;
959     switch (mapAttrs->pgsz)
960     {
961     case MMU_CAM_PGSZ_4K:
962         pteAddr = HAL_MMU_PteAddrL2(pgTblVa, virtualAddr & MMU_SMALL_PAGE_MASK);
963         pteVal = ( (physicalAddr & MMU_SMALL_PAGE_MASK) |
964                     (mapAttrs->endian << 9) |
965                     (mapAttrs->elsz << 4) |
966                     (mapAttrs->mixed << 11) | 2
967                   );
968         break;
970     case MMU_CAM_PGSZ_64K:
971         numEntries = 16;
972         pteAddr = HAL_MMU_PteAddrL2(pgTblVa, virtualAddr & MMU_LARGE_PAGE_MASK);
973         pteVal = ( (physicalAddr & MMU_LARGE_PAGE_MASK) |
974                     (mapAttrs->endian << 9) |
975                     (mapAttrs->elsz << 4) |
976                     (mapAttrs->mixed << 11) | 1
977                   );
978         break;
980     case MMU_CAM_PGSZ_1M:
981         pteAddr = HAL_MMU_PteAddrL1(pgTblVa, virtualAddr & MMU_SECTION_ADDR_MASK);
982         pteVal = ( ( ( (physicalAddr & MMU_SECTION_ADDR_MASK) |
983                      (mapAttrs->endian << 15) |
984                      (mapAttrs->elsz << 10) |
985                      (mapAttrs->mixed << 17)) &
986                      ~0x40000) | 0x2
987                  );
988         break;
990     case MMU_CAM_PGSZ_16M:
991         numEntries = 16;
992         pteAddr = HAL_MMU_PteAddrL1(pgTblVa, virtualAddr & MMU_SSECTION_ADDR_MASK);
993         pteVal = ( ( (physicalAddr & MMU_SSECTION_ADDR_MASK) |
994                       (mapAttrs->endian << 15) |
995                       (mapAttrs->elsz << 10) |
996                       (mapAttrs->mixed << 17)
997                     ) | 0x40000 | 0x2
998                   );
999         break;
1001     default:
1002         return -1;
1003     }
1005     while (--numEntries >= 0)
1006     {
1007 #ifdef MMUTEST
1008         ((ULONG*)pteAddr)[numEntries] = pteVal;
1009 #endif
1010     }
1012     return status;
1015 /*!
1016  *  @brief      Updates entries in table.
1017  *
1018  *  @param      refData Argument provided to the ISR registration function
1019  *
1020  *  @sa
1021  */
1022 Int
1023 _VAYUDSP_halMmuPteSet (VAYUDSP_HalObject *      halObject,
1024                        VAYUDSP_HalMmuEntryInfo* setPteInfo)
1026     VAYUDSP_HalMmuObject *     mmu0Obj, *mmu1Obj;
1027     struct iotlb_entry tlb_entry;
1028     Int    status = PROCESSOR_SUCCESS;
1030     GT_assert (curTrace, (halObject  != NULL));
1031     GT_assert (curTrace, (setPteInfo != NULL));
1033     mmu0Obj = &(halObject->mmu0Obj);
1034     GT_assert(curTrace, (mmu0Obj != NULL));
1035     mmu1Obj = &(halObject->mmu1Obj);
1036     GT_assert(curTrace, (mmu1Obj != NULL));
1038     switch (setPteInfo->size) {
1039         case PAGE_SIZE_16MB:
1040              tlb_entry.pgsz = MMU_CAM_PGSZ_16M;
1041              break;
1042         case PAGE_SIZE_1MB:
1043              tlb_entry.pgsz = MMU_CAM_PGSZ_1M;
1044              break;
1045         case PAGE_SIZE_64KB:
1046              tlb_entry.pgsz = MMU_CAM_PGSZ_64K;
1047              break;
1048         case PAGE_SIZE_4KB:
1049              tlb_entry.pgsz = MMU_CAM_PGSZ_4K;
1050              break;
1051         default :
1052             status = PROCESSOR_E_INVALIDARG;
1053             /*! @retval PROCESSOR_E_INVALIDARG Invalid Page size passed!. */
1054             GT_setFailureReason (curTrace,
1055                                  GT_4CLASS,
1056                                  "_VAYUDSP_halMmuPteSet",
1057                                  status,
1058                                  "Invalid Page size passed!");
1059     }
1060 #if !defined(SYSLINK_BUILD_OPTIMIZE)
1061     if (status >= 0) {
1062 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
1063         tlb_entry.prsvd  = MMU_CAM_PRESERVE;
1064         tlb_entry.valid  = MMU_CAM_VALID;
1065         /*TBD : elsz parameter has to be configured*/
1066         switch (setPteInfo->elementSize) {
1067             case ELEM_SIZE_8BIT:
1068                  tlb_entry.elsz = MMU_RAM_ELSZ_8;
1069                  break;
1070             case ELEM_SIZE_16BIT:
1071                  tlb_entry.elsz = MMU_RAM_ELSZ_16;
1072                  break;
1073             case ELEM_SIZE_32BIT:
1074                  tlb_entry.elsz = MMU_RAM_ELSZ_32;
1075                  break;
1076             case ELEM_SIZE_64BIT:
1077                  tlb_entry.elsz = 0x3; /* No translation */
1078                  break;
1079             default :
1080                 status = PROCESSOR_E_INVALIDARG;
1081                 /*! @retval PROCESSOR_E_INVALIDARG Invalid elementSize passed!*/
1082                 GT_setFailureReason (curTrace,
1083                                      GT_4CLASS,
1084                                      "_VAYUDSP_halMmuPteSet",
1085                                      status,
1086                                      "Invalid elementSize passed!");
1087         }
1088 #if !defined(SYSLINK_BUILD_OPTIMIZE)
1089         if (status >= 0) {
1090 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
1091             /*TBD : endian parameter has to configured*/
1092             switch (setPteInfo->endianism) {
1093                 case LITTLE_ENDIAN:
1094                         tlb_entry.endian = MMU_RAM_ENDIAN_LITTLE;
1095                         break;
1096                 case BIG_ENDIAN:
1097                         tlb_entry.endian = MMU_RAM_ENDIAN_BIG;
1098                         break;
1099                 default :
1100                     status = PROCESSOR_E_INVALIDARG;
1101                     /*! @retval PROCESSOR_E_INVALIDARG Invalid endianism
1102                      *                                 passed!. */
1103                     GT_setFailureReason (curTrace,
1104                                          GT_4CLASS,
1105                                          "_VAYUDSP_halMmuPteSet",
1106                                          status,
1107                                          "Invalid endianism passed!");
1108             }
1109 #if !defined(SYSLINK_BUILD_OPTIMIZE)
1110             if (status >= 0) {
1111 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
1112                 /*TBD : mixed parameter has to configured*/
1113                 switch (setPteInfo->mixedSize) {
1114                     case MMU_TLBES:
1115                             tlb_entry.mixed = MMU_RAM_DEFAULT;
1116                             break;
1117                     case MMU_CPUES:
1118                             tlb_entry.mixed = MMU_RAM_MIXED;
1119                             break;
1120                     default :
1121                         status = PROCESSOR_E_INVALIDARG;
1122                         /*! @retval PROCESSOR_E_INVALIDARG Invalid
1123                          *                                 mixed size passed!*/
1124                         GT_setFailureReason (curTrace,
1125                                              GT_4CLASS,
1126                                              "_VAYUDSP_halMmuPteSet",
1127                                              status,
1128                                              "Invalid mixed size passed!");
1129                 }
1131                 tlb_entry.da = setPteInfo->slaveVirtAddr;
1132                 tlb_entry.pa = setPteInfo->masterPhyAddr;
1134                 if (VAYUDSP_InternalMMU_PteSet(halObject->mmu0Base, &tlb_entry)){
1135                     status = PROCESSOR_E_STOREENTERY;
1136                     GT_setFailureReason (curTrace,
1137                             GT_4CLASS,
1138                             "_VAYUDSP_halMmuPteSet",
1139                             status,
1140                             "iopgtable_store_entry failed!");
1141                 }
1142                 if (VAYUDSP_InternalMMU_PteSet(halObject->mmu1Base, &tlb_entry)){
1143                     status = PROCESSOR_E_STOREENTERY;
1144                     GT_setFailureReason (curTrace,
1145                             GT_4CLASS,
1146                             "_VAYUDSP_halMmuPteSet",
1147                             status,
1148                             "iopgtable_store_entry failed!");
1149                 }
1150 #if !defined(SYSLINK_BUILD_OPTIMIZE)
1151             }
1152         }
1153     }
1154 #endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
1156 //    GT_1trace (curTrace, GT_LEAVE, "_VAYUDSP_halMmuPteSet", status);
1158     /*! @retval PROCESSOR_SUCCESS Operation completed successfully. */
1159     return status;
1163 #if defined (__cplusplus)
1165 #endif