1 /**
2 * @file OMAP5430BenelliHalReset.h
3 *
4 * @brief Reset control module header file.
5 *
6 * This module is responsible for handling reset-related hardware-
7 * specific operations.
8 * The implementation is specific to OMAP5430Benelli.
9 *
10 *
11 * @ver 02.00.00.44_pre-alpha3
12 *
13 * ============================================================================
14 *
15 * Copyright (c) 2010-2011, Texas Instruments Incorporated
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 *
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 *
28 * * Neither the name of Texas Instruments Incorporated nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
34 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
35 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
36 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
37 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
38 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
39 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
40 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
41 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
42 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Contact information for paper mail:
44 * Texas Instruments
45 * Post Office Box 655303
46 * Dallas, Texas 75265
47 * Contact information:
48 * http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm?
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50 * ============================================================================
51 *
52 */
54 #ifndef OMAP5430BENELLIHALRESET_H_0xbbef
55 #define OMAP5430BENELLIHALRESET_H_0xbbef
58 /* Module level headers */
59 #include <_ProcDefs.h>
62 #if defined (__cplusplus)
63 extern "C" {
64 #endif
67 /* =============================================================================
68 * Macros and types
69 * See _ProcDefs.h
70 * =============================================================================
71 */
72 #define INREG32(x) in32(x)
73 #define OUTREG32(x, y) out32(x, y)
74 #define SETBITREG32(x, y) OUTREG32(x, (INREG32(x) | (1 << y)))
75 #define CLRBITREG32(x, y) OUTREG32(x, (INREG32(x) & ~(1 << y)))
76 #define TESTBITREG32(x, y) (((INREG32(x) & (1 << y)) >> y) & 0x1)
78 #define CORE_PRM_BASE 0x4ae06700
80 #define RM_IPU_RSTCTRL_OFFSET 0x210
81 #define RM_IPU_RSTCTRL (CORE_PRM_BASE + RM_IPU_RSTCTRL_OFFSET)
82 #define RM_IPU_RST1_BIT 0
83 #define RM_IPU_RST1 (1 << RM_IPU_RST1_BIT)
84 #define RM_IPU_RST2_BIT 1
85 #define RM_IPU_RST2 (1 << RM_IPU_RST2_BIT)
86 #define RM_IPU_RST3_BIT 2
87 #define RM_IPU_RST3 (1 << RM_IPU_RST3_BIT)
89 #define RM_IPU_RSTST_OFFSET 0x214
90 #define RM_IPU_RSTST (CORE_PRM_BASE + RM_IPU_RSTST_OFFSET)
91 #define RM_IPU_RST1ST_BIT 0
92 #define RM_IPU_RST1ST (1 << RM_IPU_RST1ST_BIT)
93 #define RM_IPU_RST2ST_BIT 1
94 #define RM_IPU_RST2ST (1 << RM_IPU_RST2ST_BIT)
95 #define RM_IPU_RST3ST_BIT 2
96 #define RM_IPU_RST3ST (1 << RM_IPU_RST3ST_BIT)
98 #define CORE_CM2_BASE 0x4a008700
100 #define CM_IPU_CLKSTCTRL_OFFSET 0x200
101 #define CM_IPU_CLKSTCTRL (CORE_CM2_BASE + CM_IPU_CLKSTCTRL_OFFSET)
102 #define CM_IPU_CLKSTCTRL_CTRL_BITMASK 0x3
103 #define CM_IPU_CLKSTCTRL_CTRL_NO_SLEEP 0x0
104 #define CM_IPU_CLKSTCTRL_CTRL_SW_SLEEP 0x1
105 #define CM_IPU_CLKSTCTRL_CTRL_SW_WKUP 0x2
106 #define CM_IPU_CLKSTCTRL_CTRL_HW_AUTO 0x3
107 #define CM_IPU_CLKSTCTRL_CLKACTIVITY_BIT 8
108 #define CM_IPU_CLKSTCTRL_CLKACTIVITY_ON 0x1
110 #define CM_IPU_IPU_CLKCTRL_OFFSET 0x220
111 #define CM_IPU_IPU_CLKCTRL (CORE_CM2_BASE + CM_IPU_IPU_CLKCTRL_OFFSET)
112 #define CM_IPU_IPU_CLKCTRL_MODULEMODE_BITMASK 0x3
113 #define CM_IPU_IPU_CLKCTRL_MODULEMODE_DISABLE 0x0
114 #define CM_IPU_IPU_CLKCTRL_MODULEMODE_HWAUTO 0x1
116 /* DSP PRCM Regs*/
117 #define CM_DSP_CLKSTCTRL 0x4A004400
118 #define CM_DSP_STATICDEP 0x4A004404
119 #define CM_DSP_DYNMICDEP 0x4A004408
120 #define CM_DSP_DSP_CLKCTRL 0x4A004420
121 #define PM_DSP_PWRSTCTRL 0x4aE06400
122 #define PM_DSP_PWRSTST 0x4AE06404
123 #define RM_DSP_RSTCTRL 0x4AE06410
124 #define RM_DSP_RSTST 0x4AE06414
126 #define RM_DSP_DSP_CONTEXT 0x4AE06424
128 #define RM_DSP_RSTCTRL_BIT 0x0
129 #define RM_DSP_RSTST_BIT 0x0
130 #define RM_DSP_MMU_RSTCTRL_BIT 0x1
131 #define RM_DSP_RST 0x0
132 #define CM_DSP_CLKSTCTRL_CTRL_BITMASK 0x3
133 #define CM_DSP_CLKSTCTRL_CTRL_HW_AUTO 0x3
137 /* =============================================================================
138 * APIs
139 * =============================================================================
140 */
141 /* Function to control reset operations for this slave device. */
144 Int OMAP5430BENELLI_halResetCtrl (Ptr halObj, Processor_ResetCtrlCmd cmd,
145 UInt32 entryPt);
148 #if defined (__cplusplus)
149 }
150 #endif /* defined (__cplusplus) */
152 #endif /* OMAP5430BenelliHalReset_H_0xbbec */