/* * Copyright (c) 2012-2013, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== DspAmmu.cfg ======== * * An example configuration script used by DSP sample applications. */ /* -------------------------------- Cache ----------------------------------*/ var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache'); Cache.enableCache = true; if (Cache.enableCache) { Cache.ocpL1.wrap = 1; Cache.ocpL1.wrbuffer = 1; Cache.ocpL1.prefetch = 0; Cache.ocpL2.wrap = 1; Cache.ocpL2.wrbuffer = 1; Cache.ocpL2.prefetch = 0; print("DSP Unicache = ON"); } else { print("DSP Unicache = OFF"); } /* -------------------------------- AMMU -----------------------------------*/ var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU'); /*********************** Small Pages *************************/ /* Work-around for bug in BIOS 6.33.06.50 */ AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES; AMMU.smallPages[1].logicalAddress = 0x01c30000; AMMU.smallPages[1].translationEnabled = AMMU.Enable_NO; AMMU.smallPages[1].size = AMMU.Small_4K; AMMU.smallPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.smallPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; /*********************** Medium Pages *************************/ /* config medium page[0] to map 1MB VA 0x01d00000 to 0x01dFFFFF */ /* ABE NC region */ AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[0].logicalAddress = 0x01d00000; AMMU.mediumPages[0].size = AMMU.Medium_1M; AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED; AMMU.mediumPages[0].L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE; AMMU.mediumPages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.mediumPages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.mediumPages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED; AMMU.mediumPages[0].L2_allocate = AMMU.AllocatePolicy_NON_ALLOCATE; AMMU.mediumPages[0].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; /* config medium page[1] to map 1MB VA 0x01e00000 to 0x01eFFFFF */ /* IVA-HD (accelerator memories, NC region) */ AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[1].logicalAddress = 0x01e00000; AMMU.mediumPages[1].size = AMMU.Medium_1M; AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED; AMMU.mediumPages[1].L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE; AMMU.mediumPages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED; AMMU.mediumPages[1].L2_allocate = AMMU.AllocatePolicy_NON_ALLOCATE; AMMU.mediumPages[1].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK; /* config medium page[2] to map 128kB VA 0x10800000 to 0x1081FFFF */ /* SL2->L1 */ AMMU.mediumPages[2].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[2].logicalAddress = 0x10800000; AMMU.mediumPages[2].size = AMMU.Medium_128K; AMMU.mediumPages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[2].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[3].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[2].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.mediumPages[2].L2_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[2].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[2].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[2].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK; /* config medium page[3] to map 128kB VA 0x10820000 to 0x1083FFFF */ /* SL2->L2 */ AMMU.mediumPages[3].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[3].logicalAddress = 0x10820000; AMMU.mediumPages[3].size = AMMU.Medium_128K; AMMU.mediumPages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[3].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[3].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[3].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.mediumPages[3].L2_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[3].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[3].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[3].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK; /* config medium page[4] to map 1MB VA 0x10900000 to 0x109FFFFF */ /* SL2 Locked Region */ AMMU.mediumPages[4].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[4].logicalAddress = 0x10900000; AMMU.mediumPages[4].size = AMMU.Medium_1M; AMMU.mediumPages[4].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[4].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[4].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[4].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.mediumPages[4].L2_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[4].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[4].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[4].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK; /* config medium page[5] to map 1MB VA 0x10d00000 to 0x10dFFFFF */ /* ABE */ AMMU.mediumPages[5].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[5].logicalAddress = 0x10d00000; AMMU.mediumPages[5].size = AMMU.Medium_1M; AMMU.mediumPages[5].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[5].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[5].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[5].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK; AMMU.mediumPages[5].L2_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.mediumPages[5].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.mediumPages[5].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.mediumPages[5].L2_writePolicy = AMMU.WritePolicy_WRITE_BACK; /* config medium page[6] to map 1MB VA 0x10e00000 to 0x10eFFFFF */ /* ABE Locked Region */ AMMU.mediumPages[6].pageEnabled = AMMU.Enable_YES; AMMU.mediumPages[6].logicalAddress = 0x10e00000; AMMU.mediumPages[6].size = AMMU.Medium_1M; AMMU.mediumPages[6].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.mediumPages[6].L1_posted = AMMU.PostedPolicy_NON_POSTED; AMMU.mediumPages[6].L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE; AMMU.mediumPages[6].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.mediumPages[6].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.mediumPages[6].L2_posted = AMMU.PostedPolicy_NON_POSTED; AMMU.mediumPages[6].L2_allocate = AMMU.AllocatePolicy_NON_ALLOCATE; AMMU.mediumPages[6].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; /*********************** Large Pages *************************/ /* Instruction Code: Large page (512M); cacheable, posted */ /* config large page[0] to map 512MB VA 0x20000000 to L3 0x3FFFFFFF */ AMMU.largePages[0].pageEnabled = AMMU.Enable_YES; AMMU.largePages[0].logicalAddress = 0x20000000; AMMU.largePages[0].size = AMMU.Large_512M; AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[0].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[0].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[0].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; /* Peripheral regions: Large Page (512M); non-cacheable, posted */ /* config large page[1] to map 512MB VA 0x40000000 to L3 0x5FFFFFFF */ AMMU.largePages[1].pageEnabled = AMMU.Enable_YES; AMMU.largePages[1].logicalAddress = 0x40000000; AMMU.largePages[1].size = AMMU.Large_512M; AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[1].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[1].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[1].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; /* TILER region: Large Page (512M); cacheable, posted */ /* config large page[2] to map 512MB VA 0x60000000 to L3 0x7FFFFFFF */ AMMU.largePages[2].pageEnabled = AMMU.Enable_YES; AMMU.largePages[2].logicalAddress = 0x60000000; AMMU.largePages[2].size = AMMU.Large_512M; AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[2].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[2].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.largePages[2].L2_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[2].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[2].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[2].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; /* Private and Heap Data regions: Large page (512M); cacheable, posted */ /* config large page[2] to map 512MB VA 0x80000000 to L3 0x9FFFFFFF */ AMMU.largePages[3].pageEnabled = AMMU.Enable_YES; AMMU.largePages[3].logicalAddress = 0x80000000; AMMU.largePages[3].size = AMMU.Large_512M; AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[3].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[3].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.largePages[3].L2_cacheable = AMMU.CachePolicy_CACHEABLE; AMMU.largePages[3].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[3].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[3].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; /* IPC region: Large Page (512M); non-cacheable, posted */ /* config large page[3] to map 512MB VA 0xA0000000 to L3 0xBFFFFFFF */ AMMU.largePages[4].pageEnabled = AMMU.Enable_YES; AMMU.largePages[4].logicalAddress = 0xA0000000; AMMU.largePages[4].size = AMMU.Large_512M; AMMU.largePages[4].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.largePages[4].L1_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[4].L1_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[4].L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH; AMMU.largePages[4].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE; AMMU.largePages[4].L2_posted = AMMU.PostedPolicy_POSTED; AMMU.largePages[4].L2_allocate = AMMU.AllocatePolicy_ALLOCATE; AMMU.largePages[4].L2_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;