diff --git a/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.h b/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.h
index 4dd04cb93640dcc5991efa2345a1ac05a5b65ded..770b4c52d3767c20f0ace108463f61f639707afd 100644 (file)
/*
- * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * Copyright (c) 2012-2019, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*/
/*
- * ======== rsc_table_omap5_dsp.h ========
+ * ======== rsc_table_vayu_dsp.h ========
*
* Define the resource table entries for all DSP cores. This will be
* incorporated into corresponding base images, and used by the remoteproc
*
*/
-#ifndef _RSC_TABLE_DSP_H_
-#define _RSC_TABLE_DSP_H_
+#ifndef _RSC_TABLE_VAYU_DSP_H_
+#define _RSC_TABLE_VAYU_DSP_H_
#include "rsc_types.h"
/* DSP Memory Map */
-#define L4_44XX_BASE 0x4A000000
+#define L4_DRA7XX_BASE 0x4A000000
-#define L4_PERIPHERAL_L4CFG (L4_44XX_BASE)
+#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG 0x4A000000
-#define L4_PERIPHERAL_L4PER 0x48000000
-#define DSP_PERIPHERAL_L4PER 0x48000000
+#define L4_PERIPHERAL_L4PER1 0x48000000
+#define DSP_PERIPHERAL_L4PER1 0x48000000
+
+#define L4_PERIPHERAL_L4PER2 0x48400000
+#define DSP_PERIPHERAL_L4PER2 0x48400000
+
+#define L4_PERIPHERAL_L4PER3 0x48800000
+#define DSP_PERIPHERAL_L4PER3 0x48800000
#define L4_PERIPHERAL_L4EMU 0x54000000
#define DSP_PERIPHERAL_L4EMU 0x54000000
#define L3_PERIPHERAL_DMM 0x4E000000
#define DSP_PERIPHERAL_DMM 0x4E000000
-#define L3_PERIPHERAL_ISS 0x52000000
-#define DSP_PERIPHERAL_ISS 0x52000000
-
#define L3_TILER_MODE_0_1 0x60000000
#define DSP_TILER_MODE_0_1 0x60000000
#define L3_TILER_MODE_3 0x78000000
#define DSP_TILER_MODE_3 0x78000000
-#define DSP_MEM_TEXT 0x20000000
-/* Co-locate alongside TILER region for easier flushing */
-#define DSP_MEM_IOBUFS 0x80000000
-#define DSP_MEM_DATA 0x90000000
-#define DSP_MEM_HEAP 0x90100000
+#define DSP_MEM_TEXT 0x95000000
+#define DSP_MEM_DATA 0x95100000
+#define DSP_MEM_HEAP0 0x95200000
+#define DSP_MEM_HEAP1 0x95300000
#define DSP_MEM_IPC_DATA 0x9F000000
#define DSP_MEM_IPC_VRING 0xA0000000
#define DSP_MEM_VRING_BUFS0 0xA0040000
#define DSP_MEM_VRING_BUFS1 0xA0080000
+/*
+ * NOTE:
+ * To avoid issues with allocation failures with Linux carveout regions, need
+ * to use the RSC_CARVEOUT entries with power of 2 page order sizes and aligned
+ * on the same page order.
+ * The size and the alignment order of entries in the resource table plays a
+ * part in avoiding gaps in allocation
+ */
#define DSP_MEM_IPC_VRING_SIZE SZ_1M
#define DSP_MEM_IPC_DATA_SIZE SZ_1M
#define DSP_MEM_TEXT_SIZE SZ_1M
#define DSP_MEM_DATA_SIZE SZ_1M
-#define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
-#define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
+#define DSP_MEM_HEAP0_SIZE (SZ_1M * 2)
+#define DSP_MEM_HEAP1_SIZE (SZ_1M * 1)
/*
- * Assign fixed RAM addresses to facilitate a fixed MMU table.
+ * The following values need to match Linux side device tree reserved
+ * memory region start address for specific processor core.
+ * The addresses are used to create mmu entry for IPC vrings and buffers
*/
-/* This address is derived from current IPU & ION carveouts */
-#ifdef OMAP5
-#define PHYS_MEM_IPC_VRING 0x95000000
-#else
-#define PHYS_MEM_IPC_VRING 0x98800000
+#if defined (VAYU_DSP_1)
+#define PHYS_MEM_IPC_VRING 0x99000000
+#elif defined (VAYU_DSP_2)
+#define PHYS_MEM_IPC_VRING 0x9F000000
#endif
-/* Need to be identical to that of Ducati */
-#define PHYS_MEM_IOBUFS 0xBA300000
-
/*
* Sizes of the virtqueues (expressed in number of buffers supported,
* and must be power of 2)
/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES 1
-struct resource_table {
- UInt32 version;
- UInt32 num;
- UInt32 reserved[2];
- UInt32 offset[16]; /* Should match 'num' in actual definition */
+#define NUM_RSC_ENTRIES 17
+
+struct my_resource_table {
+ struct resource_table base;
+
+ UInt32 offset[NUM_RSC_ENTRIES]; /* Should match 'num' in actual definition */
/* rpmsg vdev entry */
struct fw_rsc_vdev rpmsg_vdev;
struct fw_rsc_vdev_vring rpmsg_vring0;
struct fw_rsc_vdev_vring rpmsg_vring1;
+ /* ipcdata carveout entry */
+ struct fw_rsc_carveout ipcdata_cout;
+
/* text carveout entry */
struct fw_rsc_carveout text_cout;
struct fw_rsc_carveout data_cout;
/* heap carveout entry */
- struct fw_rsc_carveout heap_cout;
+ struct fw_rsc_carveout heap0_cout;
- /* ipcdata carveout entry */
- struct fw_rsc_carveout ipcdata_cout;
+ /* heap carveout entry */
+ struct fw_rsc_carveout heap1_cout;
/* trace entry */
struct fw_rsc_trace trace;
#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
-struct resource_table ti_ipc_remoteproc_ResourceTable = {
+struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
1, /* we're the first version that implements this */
- 16, /* number of entries in the table */
+ NUM_RSC_ENTRIES, /* number of entries in the table */
0, 0, /* reserved, must be zero */
/* offsets to entries */
{
- offsetof(struct resource_table, rpmsg_vdev),
- offsetof(struct resource_table, text_cout),
- offsetof(struct resource_table, data_cout),
- offsetof(struct resource_table, heap_cout),
- offsetof(struct resource_table, ipcdata_cout),
- offsetof(struct resource_table, trace),
- offsetof(struct resource_table, devmem0),
- offsetof(struct resource_table, devmem1),
- offsetof(struct resource_table, devmem2),
- offsetof(struct resource_table, devmem3),
- offsetof(struct resource_table, devmem4),
- offsetof(struct resource_table, devmem5),
- offsetof(struct resource_table, devmem6),
- offsetof(struct resource_table, devmem7),
- offsetof(struct resource_table, devmem8),
- offsetof(struct resource_table, devmem9),
+ offsetof(struct my_resource_table, rpmsg_vdev),
+ offsetof(struct my_resource_table, ipcdata_cout),
+ offsetof(struct my_resource_table, text_cout),
+ offsetof(struct my_resource_table, data_cout),
+ offsetof(struct my_resource_table, heap0_cout),
+ offsetof(struct my_resource_table, heap1_cout),
+ offsetof(struct my_resource_table, trace),
+ offsetof(struct my_resource_table, devmem0),
+ offsetof(struct my_resource_table, devmem1),
+ offsetof(struct my_resource_table, devmem2),
+ offsetof(struct my_resource_table, devmem3),
+ offsetof(struct my_resource_table, devmem4),
+ offsetof(struct my_resource_table, devmem5),
+ offsetof(struct my_resource_table, devmem6),
+ offsetof(struct my_resource_table, devmem7),
+ offsetof(struct my_resource_table, devmem8),
+ offsetof(struct my_resource_table, devmem9),
},
/* rpmsg vdev entry */
{ DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
{ DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
+ {
+ TYPE_CARVEOUT,
+ DSP_MEM_IPC_DATA, 0,
+ DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
+ },
+
{
TYPE_CARVEOUT,
DSP_MEM_TEXT, 0,
{
TYPE_CARVEOUT,
- DSP_MEM_HEAP, 0,
- DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
+ DSP_MEM_HEAP0, 0,
+ DSP_MEM_HEAP0_SIZE, 0, 0, "DSP_MEM_HEAP0",
},
{
TYPE_CARVEOUT,
- DSP_MEM_IPC_DATA, 0,
- DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
+ DSP_MEM_HEAP1, 0,
+ DSP_MEM_HEAP1_SIZE, 0, 0, "DSP_MEM_HEAP1",
},
{
DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
},
- {
- TYPE_DEVMEM,
- DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
- DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
- },
-
{
TYPE_DEVMEM,
DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
{
TYPE_DEVMEM,
- DSP_PERIPHERAL_L4PER, L4_PERIPHERAL_L4PER,
- SZ_16M, 0, 0, "DSP_PERIPHERAL_L4PER",
+ DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
+ SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
},
{
TYPE_DEVMEM,
- DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
- SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
+ DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
+ SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
},
{
TYPE_DEVMEM,
- DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
- SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
+ DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
+ SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
},
{
TYPE_DEVMEM,
- DSP_PERIPHERAL_ISS, L3_PERIPHERAL_ISS,
- SZ_256K, 0, 0, "DSP_PERIPHERAL_ISS",
+ DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
+ SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
+ SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
},
};
-#endif /* _RSC_TABLE_DSP_H_ */
+#endif /* _RSC_TABLE_VAYU_DSP_H_ */