diff --git a/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.h b/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.h
index 664d4d41d2c46477907213276a82bcecfb77ee5f..34068af82d4c4b8deb7a1eb5757a0d01146fa190 100644 (file)
/*
- * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * Copyright (c) 2012-2019, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*/
/*
- * ======== rsc_table_omap5_ipu.h ========
+ * ======== rsc_table_vayu_ipu.h ========
*
* Define the resource table entries for all IPU cores. This will be
* incorporated into corresponding base images, and used by the remoteproc
*
*/
-#ifndef _RSC_TABLE_IPU_H_
-#define _RSC_TABLE_IPU_H_
+#ifndef _RSC_TABLE_VAYU_IPU_H_
+#define _RSC_TABLE_VAYU_IPU_H_
#include "rsc_types.h"
/* IPU Memory Map */
-#define L4_44XX_BASE 0x4a000000
+#define L4_DRA7XX_BASE 0x4A000000
-#define L4_PERIPHERAL_L4CFG (L4_44XX_BASE)
+/* L4_CFG & L4_WKUP */
+#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
#define IPU_PERIPHERAL_L4CFG 0x6A000000
-#define L4_PERIPHERAL_L4PER 0x48000000
-#define IPU_PERIPHERAL_L4PER 0x68000000
+#define L4_PERIPHERAL_L4PER1 0x48000000
+#define IPU_PERIPHERAL_L4PER1 0x68000000
+
+#define L4_PERIPHERAL_L4PER2 0x48400000
+#define IPU_PERIPHERAL_L4PER2 0x68400000
+
+#define L4_PERIPHERAL_L4PER3 0x48800000
+#define IPU_PERIPHERAL_L4PER3 0x68800000
#define L4_PERIPHERAL_L4EMU 0x54000000
#define IPU_PERIPHERAL_L4EMU 0x74000000
#define L3_TILER_MODE_3 0x78000000
#define IPU_TILER_MODE_3 0xB8000000
-
+#if defined(VAYU_IPU_1)
#define IPU_MEM_TEXT 0x0
-#define IPU_MEM_DATA 0x80000000
+#elif defined(VAYU_IPU_2)
+#define IPU_MEM_TEXT0 0x0
+#define IPU_MEM_TEXT1 0x0200000
+#endif
-#if defined(OMAP5) || defined(VAYU_IPU_1) || defined(VAYU_IPU_2)
-#define IPU_MEM_IOBUFS 0x90000000
-#else
-#define IPU_MEM_IOBUFS 0x88000000
+#if defined(VAYU_IPU_1)
+#define IPU_MEM_DATA0 0x80000000
+#define IPU_MEM_DATA1 0x80100000
+#elif defined(VAYU_IPU_2)
+#define IPU_MEM_DATA0 0x80000000
+#define IPU_MEM_DATA1 0x80800000
+#define IPU_MEM_DATA2 0x81800000
+#define IPU_MEM_DATA3 0x82800000
#endif
#define IPU_MEM_IPC_DATA 0x9F000000
#define IPU_MEM_IPC_VRING_SIZE SZ_1M
#define IPU_MEM_IPC_DATA_SIZE SZ_1M
-#ifdef VAYU_IPU_1
+#if defined(VAYU_IPU_1)
#define IPU_MEM_TEXT_SIZE (SZ_1M)
-#else
-#define IPU_MEM_TEXT_SIZE (SZ_1M * 6)
+#elif defined(VAYU_IPU_2)
+#define IPU_MEM_TEXT0_SIZE (SZ_1M * 2)
+#define IPU_MEM_TEXT1_SIZE (SZ_1M * 4)
#endif
-#if defined(OMAP5) || defined(VAYU_IPU_2)
-#define IPU_MEM_DATA_SIZE (SZ_1M * 156)
-#elif defined(VAYU_IPU_1)
-#define IPU_MEM_DATA_SIZE (SZ_1M * 5)
-#else
-#define IPU_MEM_DATA_SIZE (SZ_1M * 100)
+#if defined(VAYU_IPU_1)
+#define IPU_MEM_DATA0_SIZE (SZ_1M * 1)
+#define IPU_MEM_DATA1_SIZE (SZ_1M * 4)
+#elif defined(VAYU_IPU_2)
+#define IPU_MEM_DATA0_SIZE (SZ_1M * 8)
+#define IPU_MEM_DATA1_SIZE (SZ_1M * 16)
+#define IPU_MEM_DATA2_SIZE (SZ_1M * 16)
+#define IPU_MEM_DATA3_SIZE (SZ_1M * 8)
#endif
-#define IPU_MEM_IOBUFS_SIZE (SZ_1M * 90)
-
/*
- * Assign fixed RAM addresses to facilitate a fixed MMU table.
- * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
+ * NOTE:
+ * To avoid issues with allocation failures with Linux carveout regions, need
+ * to use the RSC_CARVEOUT entries with power of 2 page order sizes and aligned
+ * on the same page order.
+ * The size and the alignment order of entries in the resource table plays a
+ * part in avoiding gaps in allocation
*/
-/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
-#ifdef OMAP5
-#define PHYS_MEM_IPC_VRING 0x95800000
-#elif defined(VAYU_IPU_1)
-#define PHYS_MEM_IPC_VRING 0x94000000
+#if defined(VAYU_IPU_1)
+#define PHYS_MEM_IPC_VRING 0x9D000000
#elif defined (VAYU_IPU_2)
#define PHYS_MEM_IPC_VRING 0x95800000
-#else
-#define PHYS_MEM_IPC_VRING 0x99000000
#endif
-#define PHYS_MEM_IOBUFS 0xBA300000
-
/*
* Sizes of the virtqueues (expressed in number of buffers supported,
* and must be power of 2)
/* flip up bits whose indices represent features we support */
#define RPMSG_IPU_C0_FEATURES 1
+#if defined(VAYU_IPU_1)
+#define NUM_RSC_ENTRIES 18
+#elif defined (VAYU_IPU_2)
+#define NUM_RSC_ENTRIES 21
+#endif
+
struct my_resource_table {
struct resource_table base;
- UInt32 offset[16]; /* Should match 'num' in actual definition */
+ UInt32 offset[NUM_RSC_ENTRIES]; /* Should match 'num' in actual definition */
/* rpmsg vdev entry */
struct fw_rsc_vdev rpmsg_vdev;
struct fw_rsc_vdev_vring rpmsg_vring0;
struct fw_rsc_vdev_vring rpmsg_vring1;
- /* text carveout entry */
- struct fw_rsc_carveout text_cout;
-
- /* data carveout entry */
- struct fw_rsc_carveout data_cout;
-
/* ipcdata carveout entry */
struct fw_rsc_carveout ipcdata_cout;
+ /* text carveout entry */
+#if defined(VAYU_IPU_1)
+ struct fw_rsc_carveout text_cout;
+#elif defined (VAYU_IPU_2)
+ struct fw_rsc_carveout text0_cout;
+ struct fw_rsc_carveout text1_cout;
+#endif
+ /* data carveout entries */
+ struct fw_rsc_carveout data0_cout;
+ struct fw_rsc_carveout data1_cout;
+#if defined(VAYU_IPU_2)
+ struct fw_rsc_carveout data2_cout;
+ struct fw_rsc_carveout data3_cout;
+#endif
+
/* trace entry */
struct fw_rsc_trace trace;
/* devmem entry */
struct fw_rsc_devmem devmem10;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem11;
};
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
1, /* we're the first version that implements this */
- 16, /* number of entries in the table */
+ NUM_RSC_ENTRIES, /* number of entries in the table */
0, 0, /* reserved, must be zero */
/* offsets to entries */
{
offsetof(struct my_resource_table, rpmsg_vdev),
- offsetof(struct my_resource_table, text_cout),
- offsetof(struct my_resource_table, data_cout),
offsetof(struct my_resource_table, ipcdata_cout),
+#if defined(VAYU_IPU_1)
+ offsetof(struct my_resource_table, text_cout),
+#elif defined (VAYU_IPU_2)
+ offsetof(struct my_resource_table, text0_cout),
+ offsetof(struct my_resource_table, text1_cout),
+#endif
+ offsetof(struct my_resource_table, data0_cout),
+ offsetof(struct my_resource_table, data1_cout),
+#if defined(VAYU_IPU_2)
+ offsetof(struct my_resource_table, data2_cout),
+ offsetof(struct my_resource_table, data3_cout),
+#endif
offsetof(struct my_resource_table, trace),
offsetof(struct my_resource_table, devmem0),
offsetof(struct my_resource_table, devmem1),
offsetof(struct my_resource_table, devmem8),
offsetof(struct my_resource_table, devmem9),
offsetof(struct my_resource_table, devmem10),
+ offsetof(struct my_resource_table, devmem11),
},
/* rpmsg vdev entry */
{ IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 },
{ IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },
+ {
+ TYPE_CARVEOUT,
+ IPU_MEM_IPC_DATA, 0,
+ IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA",
+ },
+
+#if defined(VAYU_IPU_1)
{
TYPE_CARVEOUT,
IPU_MEM_TEXT, 0,
IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
},
+#elif defined (VAYU_IPU_2)
+ {
+ TYPE_CARVEOUT,
+ IPU_MEM_TEXT0, 0,
+ IPU_MEM_TEXT0_SIZE, 0, 0, "IPU_MEM_TEXT0",
+ },
{
TYPE_CARVEOUT,
- IPU_MEM_DATA, 0,
- IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA",
+ IPU_MEM_TEXT1, 0,
+ IPU_MEM_TEXT1_SIZE, 0, 0, "IPU_MEM_TEXT1",
},
+#endif
{
TYPE_CARVEOUT,
- IPU_MEM_IPC_DATA, 0,
- IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA",
+ IPU_MEM_DATA0, 0,
+ IPU_MEM_DATA0_SIZE, 0, 0, "IPU_MEM_DATA0",
},
{
- TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3",
+ TYPE_CARVEOUT,
+ IPU_MEM_DATA1, 0,
+ IPU_MEM_DATA1_SIZE, 0, 0, "IPU_MEM_DATA1",
},
+#if defined(VAYU_IPU_2)
{
- TYPE_DEVMEM,
- IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
- IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING",
+ TYPE_CARVEOUT,
+ IPU_MEM_DATA2, 0,
+ IPU_MEM_DATA2_SIZE, 0, 0, "IPU_MEM_DATA2",
+ },
+
+ {
+ TYPE_CARVEOUT,
+ IPU_MEM_DATA3, 0,
+ IPU_MEM_DATA3_SIZE, 0, 0, "IPU_MEM_DATA3",
+ },
+#endif
+
+ {
+ TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3",
},
{
TYPE_DEVMEM,
- IPU_MEM_IOBUFS, PHYS_MEM_IOBUFS,
- IPU_MEM_IOBUFS_SIZE, 0, 0, "IPU_MEM_IOBUFS",
+ IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
+ IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING",
},
{
{
TYPE_DEVMEM,
- IPU_PERIPHERAL_L4PER, L4_PERIPHERAL_L4PER,
- SZ_16M, 0, 0, "IPU_PERIPHERAL_L4PER",
+ IPU_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
+ SZ_2M, 0, 0, "IPU_PERIPHERAL_L4PER1",
+ },
+
+ {
+ TYPE_DEVMEM,
+ IPU_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
+ SZ_4M, 0, 0, "IPU_PERIPHERAL_L4PER2",
+ },
+
+ {
+ TYPE_DEVMEM,
+ IPU_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
+ SZ_8M, 0, 0, "IPU_PERIPHERAL_L4PER3",
},
{
},
};
-#endif /* _RSC_TABLE_IPU_H_ */
+#endif /* _RSC_TABLE_VAYU_IPU_H_ */