diff --git a/packages/ti/ipc/tests/gatempapp_rsc_table_vayu_dsp.h b/packages/ti/ipc/tests/gatempapp_rsc_table_vayu_dsp.h
index b55788c311505eeeb3042c6e51eb6ae6855e7205..a73aeccc23afb4897c4dbcabafe413d4696b89d3 100644 (file)
/*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
*/
-#ifndef _RSC_TABLE_DSP_H_
-#define _RSC_TABLE_DSP_H_
+#ifndef _GATEMPAPP_RSC_TABLE_VAYU_DSP_H_
+#define _GATEMPAPP_RSC_TABLE_VAYU_DSP_H_
#include <ti/ipc/remoteproc/rsc_types.h>
/* DSP Memory Map */
-#define L4_44XX_BASE 0x4A000000
+#define L4_DRA7XX_BASE 0x4A000000
-#define L4_PERIPHERAL_L4CFG (L4_44XX_BASE)
+#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG 0x4A000000
-#define L4_PERIPHERAL_L4PER 0x48000000
-#define DSP_PERIPHERAL_L4PER 0x48000000
+#define L4_PERIPHERAL_L4PER1 0x48000000
+#define DSP_PERIPHERAL_L4PER1 0x48000000
+
+#define L4_PERIPHERAL_L4PER2 0x48400000
+#define DSP_PERIPHERAL_L4PER2 0x48400000
+
+#define L4_PERIPHERAL_L4PER3 0x48800000
+#define DSP_PERIPHERAL_L4PER3 0x48800000
#define L4_PERIPHERAL_L4EMU 0x54000000
#define DSP_PERIPHERAL_L4EMU 0x54000000
#define DSP_MEM_IOBUFS 0x80000000
#define DSP_MEM_DATA 0x95100000
#define DSP_MEM_HEAP 0x95200000
+#define DSP_MEM_CMEM 0x95500000
//0x85900000
-#define DSP_SR0_VIRT 0xBFC00000
-#define DSP_SR0 0xBFC00000
+#define DSP_SR0_VIRT 0xBFB00000
+#define DSP_SR0 0xBFB00000
#define DSP_MEM_IPC_DATA 0x9F000000
#define DSP_MEM_IPC_VRING 0xA0000000
#define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
#define DSP_MEM_IOBUFS_SIZE (SZ_1M * 89)
#define DSP_SR0_SIZE (SZ_1M * 1)
+#define DSP_MEM_CMEM_SIZE (SZ_1M * 4)
/*
* Assign fixed RAM addresses to facilitate a fixed MMU table.
*/
/* This address is derived from current IPU & ION carveouts */
-#ifdef OMAP5
-#define PHYS_MEM_IPC_VRING 0x95000000
-#else
-#define PHYS_MEM_IPC_VRING 0x98800000
-#endif
+#define PHYS_MEM_IPC_VRING 0x99000000
/* Need to be identical to that of IPU */
#define PHYS_MEM_IOBUFS 0xBA300000
+#define PHYS_MEM_CMEM 0x95400000
/*
* Sizes of the virtqueues (expressed in number of buffers supported,
struct my_resource_table {
struct resource_table base;
- UInt32 offset[17]; /* Should match 'num' in actual definition */
+ UInt32 offset[20]; /* Should match 'num' in actual definition */
/* rpmsg vdev entry */
struct fw_rsc_vdev rpmsg_vdev;
/* devmem entry */
struct fw_rsc_devmem devmem10;
+ /* devmem entry */
+ struct fw_rsc_devmem devmem11;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem12;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem13;
};
extern char ti_trace_SysMin_Module_State_0_outbuf__A;
struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
1, /* we're the first version that implements this */
- 17, /* number of entries in the table */
+ 20, /* number of entries in the table */
0, 0, /* reserved, must be zero */
/* offsets to entries */
{
offsetof(struct my_resource_table, devmem8),
offsetof(struct my_resource_table, devmem9),
offsetof(struct my_resource_table, devmem10),
+ offsetof(struct my_resource_table, devmem11),
+ offsetof(struct my_resource_table, devmem12),
+ offsetof(struct my_resource_table, devmem13),
},
/* rpmsg vdev entry */
DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
},
+ {
+ TYPE_DEVMEM,
+ DSP_MEM_CMEM, PHYS_MEM_CMEM,
+ DSP_MEM_CMEM_SIZE, 0, 0, "DSP_MEM_CMEM",
+ },
+
{
TYPE_DEVMEM,
DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
{
TYPE_DEVMEM,
- DSP_PERIPHERAL_L4PER, L4_PERIPHERAL_L4PER,
- SZ_16M, 0, 0, "DSP_PERIPHERAL_L4PER",
+ DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
+ SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
+ SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
+ SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
},
{
};
-#endif /* _RSC_TABLE_DSP_H_ */
+#endif /* _GATEMPAPP_RSC_TABLE_VAYU_DSP_H_ */