index 659757b52bfe28aa1deb279f561480f813e24857..d1a9bb44c3e955a6190799ee9511dd0d3817e1fc 100644 (file)
/* prevent another thread or processor from modifying the ListMP */
key = GateMP_enter((GateMP_Handle)obj->gate);
-#ifdef xdc_target__isaCompatible_v7A
+#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A)
/* ARM speculative execution might have pulled attrs into cache */
if (obj->cacheEnabled) {
Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE);
/* prevent another thread or processor from modifying the ListMP */
key = GateMP_enter((GateMP_Handle)obj->gate);
-#ifdef xdc_target__isaCompatible_v7A
+#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A)
/* ARM speculative execution might have pulled attrs into cache */
if (obj->cacheEnabled) {
Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE);
/* prevent another thread or processor from modifying the ListMP */
key = GateMP_enter((GateMP_Handle)obj->gate);
-#ifdef xdc_target__isaCompatible_v7A
+#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A)
/* ARM speculative execution might have pulled attrs into cache */
if (obj->cacheEnabled) {
Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE);
/* prevent another thread or processor from modifying the ListMP */
key = GateMP_enter((GateMP_Handle)obj->gate);
-#ifdef xdc_target__isaCompatible_v7A
+#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A)
/* ARM speculative execution might have pulled attrs into cache */
if (obj->cacheEnabled) {
Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE);
/* prevent another thread or processor from modifying the ListMP */
key = GateMP_enter((GateMP_Handle)obj->gate);
-#ifdef xdc_target__isaCompatible_v7A
+#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A)
/* ARM speculative execution might have pulled attrs into cache */
if (obj->cacheEnabled) {
Cache_inv(attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL, TRUE);
obj->cacheEnabled = SharedRegion_isCacheEnabled(obj->regionId);
obj->cacheLineSize = SharedRegion_getCacheLineSize(obj->regionId);
-#ifdef xdc_target__isaCompatible_v7A
+#if defined(xdc_target__isaCompatible_v7A) || defined(xdc_target__isaCompatible_v8A)
/* ARM speculative execution might have pulled attrs into cache */
if (obj->cacheEnabled) {
Cache_inv(obj->attrs, sizeof(ti_sdo_ipc_ListMP_Attrs), Cache_Type_ALL,
/* Assert that sharedAddr is cache aligned */
Assert_isTrue((obj->cacheLineSize == 0) ||
- ((UInt32)params->sharedAddr % obj->cacheLineSize == 0),
+ ((uintptr_t)params->sharedAddr % obj->cacheLineSize == 0),
ti_sdo_ipc_Ipc_A_addrNotCacheAligned);
}