diff --git a/packages/ti/sdo/ipc/transports/TransportShm.c b/packages/ti/sdo/ipc/transports/TransportShm.c
index 75d3ad41dc5c4b63d6284ef10cc01eede1871f46..7c83e9d2bb833076b0255b26aa7646b97e422af6 100644 (file)
/*
- * Copyright (c) 2012-2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2012-2019 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
obj->cacheEnabled = SharedRegion_isCacheEnabled(obj->regionId);
localAddr = SharedRegion_getPtr(obj->self->gateMPAddr);
+ if (localAddr == NULL) {
+ Error_raise(eb, ti_sdo_ipc_Ipc_E_internal, 0, 0);
+ return(1);
+ }
+
status = GateMP_openByAddr(localAddr, (GateMP_Handle *)&obj->gate);
if (status < 0) {
Error_raise(eb, ti_sdo_ipc_Ipc_E_internal, 0, 0);
ti_sdo_ipc_Ipc_A_addrNotInSharedRegion);
/* Assert that sharedAddr is cache aligned */
- Assert_isTrue(((UInt32)params->sharedAddr %
+ Assert_isTrue(SharedRegion_getCacheLineSize(obj->regionId) == 0 ||
+ ((UArg)params->sharedAddr %
SharedRegion_getCacheLineSize(obj->regionId) == 0),
ti_sdo_ipc_Ipc_A_addrNotCacheAligned);
* If cache is enabled, these need to be on separate cache lines.
* This is done with minAlign and _Ipc_roundup function.
*/
- obj->other = (TransportShm_Attrs *)((UInt32)(obj->self) +
+ obj->other = (TransportShm_Attrs *)((UArg)(obj->self) +
(_Ipc_roundup(sizeof(TransportShm_Attrs), minAlign)));
ListMP_Params_init(&(listMPParams[0]));
listMPParams[0].gate = (GateMP_Handle)obj->gate;
- listMPParams[0].sharedAddr = (UInt32 *)((UInt32)(obj->other) +
+ listMPParams[0].sharedAddr = (UInt32 *)((UArg)(obj->other) +
(_Ipc_roundup(sizeof(TransportShm_Attrs), minAlign)));
ListMP_Params_init(&listMPParams[1]);
listMPParams[1].gate = (GateMP_Handle)obj->gate;
- listMPParams[1].sharedAddr = (UInt32 *)((UInt32)(listMPParams[0].sharedAddr)
+ listMPParams[1].sharedAddr = (UInt32 *)((UArg)(listMPParams[0].sharedAddr)
+ ListMP_sharedMemReq(&listMPParams[0]));
obj->priority = params->priority;