[ipc/ipcdev.git] / qnx / src / ipc3x_dev / ti / syslink / family / common / vayu / vayuipu / vayucore0 / VAYUIpuCore0Proc.c
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0Proc.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0Proc.c
index a66f497dc40540c55ce2cbb90dd9e9749092d6d5..adab529ed3143c9e36ce050b8612803ab1442459 100644 (file)
#define PROCID_TO_IPU(procId) (procId == VAYUIPUCORE0PROC_state.ipu1ProcId ?\
0 : 1)
-/* Config param for L2MMU. This is not a typo, we are using the
- * same name (IPU1) because both Benelli M4 processors use the
- * same L2MMU. The docs expose IPUx but not the IPUx Core1 processor.
- */
-#define PARAMS_mmuEnable1 "ProcMgr.proc[IPU1].mmuEnable="
-#define PARAMS_mmuEnable2 "ProcMgr.proc[IPU2].mmuEnable="
-
/*!
* @brief VAYUIPUCORE0PROC Module state object
.isSetup = FALSE,
.configSize = sizeof(VAYUIPUCORE0PROC_Config),
.gateHandle = NULL,
- .defInstParams.mmuEnable = TRUE,
.defInstParams.numMemEntries = AddrTable_STATIC_COUNT,
};
/* Added for Netra Benelli core1 is cortex M4 */
params->procArch = Processor_ProcArch_M4;
- /* check for instance params override */
- if (VAYUIPUCORE0PROC_state.ipu1ProcId == procHandle->procId) {
- Cfg_propBool(PARAMS_mmuEnable1, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
- }
- else {
- Cfg_propBool(PARAMS_mmuEnable2, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
- }
-
object->pmHandle = params->pmHandle;
GT_0trace(curTrace, GT_1CLASS,
"VAYUIPUCORE0PROC_attach: Mapping memory regions");
/* search for dsp memory map */
- status = RscTable_process(procHandle->procId, object->params.mmuEnable,
+ status = RscTable_process(procHandle->procId,
TRUE,
&memBlock.numEntries);
if (status < 0 || memBlock.numEntries > SYSLINK_MAX_MEMENTRIES) {
GT_0trace(curTrace, GT_1CLASS,
"VAYUIPUCORE0PROC_attach: slave is now in reset");
- if (object->params.mmuEnable) {
- mmuEnableArgs.numMemEntries = 0;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
+ mmuEnableArgs.numMemEntries = 0;
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_attach", status,
+ "Failed to enable the slave MMU");
+ }
+ else {
+#endif
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUIPUCORE0PROC_attach: Slave MMU "
+ "is configured!");
+ /*
+ * Pull IPU MMU out of reset to make internal
+ * memory "loadable"
+ */
+ status = VAYUIPUCORE0_halResetCtrl(
+ object->halObject,
+ Processor_ResetCtrlCmd_MMU_Release);
if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_attach", status,
- "Failed to enable the slave MMU");
+ /*! @retval status */
+ GT_setFailureReason(curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE0_halResetCtrl",
+ status,
+ "Reset MMU_Release failed");
}
- else {
-#endif
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUIPUCORE0PROC_attach: Slave MMU "
- "is configured!");
- /*
- * Pull IPU MMU out of reset to make internal
- * memory "loadable"
- */
- status = VAYUIPUCORE0_halResetCtrl(
- object->halObject,
- Processor_ResetCtrlCmd_MMU_Release);
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason(curTrace,
- GT_4CLASS,
- "VAYUIPUCORE0_halResetCtrl",
- status,
- "Reset MMU_Release failed");
- }
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- }
-#endif
}
-#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
#endif
}
if ( (procHandle->bootMode == ProcMgr_BootMode_Boot)
|| (procHandle->bootMode == ProcMgr_BootMode_NoLoad_Pwr)) {
- if (object->params.mmuEnable) {
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUIPUCORE0PROC_detach: Disabling Slave MMU ...");
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUIPUCORE0PROC_detach: Disabling Slave MMU ...");
- status = VAYUIPUCORE0_halResetCtrl(object->halObject,
- Processor_ResetCtrlCmd_MMU_Reset);
+ status = VAYUIPUCORE0_halResetCtrl(object->halObject,
+ Processor_ResetCtrlCmd_MMU_Reset);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIPUCORE0_halResetCtrl",
- status,
- "Reset MMU failed");
- }
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE0_halResetCtrl",
+ status,
+ "Reset MMU failed");
+ }
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) */
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Disable, NULL);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Disable, NULL);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_detach", status,
- "Failed to disable the slave MMU");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_detach", status,
+ "Failed to disable the slave MMU");
}
+#endif
/* delete all dynamically added entries */
for (i = AddrTable_STATIC_COUNT; i <
}
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) */
- if (object->params.mmuEnable) {
- status = rproc_ipu_setup(object->halObject,
- object->params.memEntries,
- object->params.numMemEntries);
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIPUCORE0_halResetCtrl",
- status,
- "rproc_ipu_setup failed");
- }
+ status = rproc_ipu_setup(object->halObject,
+ object->params.memEntries,
+ object->params.numMemEntries);
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE0_halResetCtrl",
+ status,
+ "rproc_ipu_setup failed");
}
/* release the slave cpu from reset */
if (status >= 0) {
"Failed to place slave in reset");
}
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) */
- if (object->params.mmuEnable) {
- rproc_ipu_destroy(object->halObject);
- }
+ rproc_ipu_destroy(object->halObject);
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
}
if (*dstAddr == -1u) {
- if (!object->params.mmuEnable) {
- /* default to direct mapping (i.e. v=p) */
- *dstAddr = srcAddr;
- GT_2trace(curTrace, GT_1CLASS, "VAYUIPUCORE0PROC_translate: "
- "(default) srcAddr=0x%x --> dstAddr=0x%x",
- srcAddr, *dstAddr);
- }
- else {
- /* srcAddr not found in slave address space */
- status = PROCESSOR_E_INVALIDARG;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_translate", status,
- "srcAddr not found in slave address space");
- }
+ /* srcAddr not found in slave address space */
+ status = PROCESSOR_E_INVALIDARG;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_translate", status,
+ "srcAddr not found in slave address space");
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
* the assumption is that the ammu will be used.
*/
if (!found) {
- if (object->params.mmuEnable) {
- if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
- AddrTable_SIZE) {
- ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
- [AddrTable_count[PROCID_TO_IPU
- (procHandle->procId)]];
- ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
- ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
- ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
- ai->size = sglist[i].size;
- ai->isCached = sglist[i].isCached;
- ai->refCount++;
+ if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
+ AddrTable_SIZE) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
+ [AddrTable_count[PROCID_TO_IPU
+ (procHandle->procId)]];
+ ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
+ ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
+ ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
+ ai->size = sglist[i].size;
+ ai->isCached = sglist[i].isCached;
+ ai->refCount++;
- AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
- }
- else {
- status = PROCESSOR_E_FAIL;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_map", status,
- "AddrTable_SIZE reached!");
- }
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
}
else {
- /* if mmu disabled, AddrTable not updated */
- ai = NULL;
+ status = PROCESSOR_E_FAIL;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_map", status,
+ "AddrTable_SIZE reached!");
}
}
if ((ai != NULL) && (ai->refCount == 1) && (status >= 0)) {
ai->isMapped = TRUE;
- if (object->params.mmuEnable) {
- /* add entry to L2 MMU */
- addEntryArgs.masterPhyAddr = sglist [i].paddr;
- addEntryArgs.size = sglist [i].size;
- addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- addEntryArgs.elementSize = ELEM_SIZE_16BIT;
- addEntryArgs.endianism = LITTLE_ENDIAN;
- addEntryArgs.mixedSize = MMU_TLBES;
+ /* add entry to L2 MMU */
+ addEntryArgs.masterPhyAddr = sglist [i].paddr;
+ addEntryArgs.size = sglist [i].size;
+ addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ addEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ addEntryArgs.endianism = LITTLE_ENDIAN;
+ addEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_map", status,
- "Processor_MmuCtrlCmd_AddEntry failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_map", status,
+ "Processor_MmuCtrlCmd_AddEntry failed");
}
+#endif
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
ai->mapMask = 0u;
ai->isMapped = FALSE;
- if (object->params.mmuEnable) {
- /* Remove the entry from the IPUCORE0 MMU also */
- deleteEntryArgs.size = size;
- deleteEntryArgs.slaveVirtAddr = addr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
- deleteEntryArgs.endianism = LITTLE_ENDIAN;
- deleteEntryArgs.mixedSize = MMU_TLBES;
+ /* Remove the entry from the IPUCORE0 MMU also */
+ deleteEntryArgs.size = size;
+ deleteEntryArgs.slaveVirtAddr = addr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ deleteEntryArgs.endianism = LITTLE_ENDIAN;
+ deleteEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_unmap", status,
- "IPUCORE0 MMU configuration failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_unmap", status,
+ "IPUCORE0 MMU configuration failed");
}
+#endif
}
}
}