Fix misuse of SET_BIT macro to clear mailbox-interrupt-status-clear registers

Fix misuse of SET_BIT macro to clear mailbox-interrupt-status-clear registers

The mailbox interrupt handling code in QNX IPC uses the SET_BIT macro to
clear status bits from the MAILBOX_IRQSTATUS_CLR_u registers. This is wrong,
because the macro does as follows:

  >#define SET_BIT(num,pos)            ((num) |= (1u << (pos)))

It will read the register and end up clearing *ALL* bits that are pending
during the write-back, as opposed to the specific one it needs to clear. If the
host is in the midst of processing an interrupt from a given core when a second
core writes to its (sub)mailbox, the second payload may be lost.

This commit changes the SET_BIT call to a direct register assignment of the
appropriate bit mask.

Signed-off-by: VW <vwan@ti.com>