author | vwan@ti.com <vwan@ti.com> | |
Thu, 27 Feb 2014 22:49:06 +0000 (14:49 -0800) | ||
committer | Chris Ring <cring@ti.com> | |
Sun, 2 Mar 2014 17:46:21 +0000 (09:46 -0800) | ||
commit | 2d13cedd28aa2a3bb1bf89e064064723be0c76f7 | |
tree | 8f1d867f8a36f29dc64d93d5253a32e78a9268b5 | tree | snapshot (tar.xz tar.gz zip) |
parent | 64cff59ff8df8ccc1746e8f53989f34fd59ad3c3 | commit | diff |
Fix misuse of SET_BIT macro to clear mailbox-interrupt-status-clear registers
The mailbox interrupt handling code in QNX IPC uses the SET_BIT macro to
clear status bits from the MAILBOX_IRQSTATUS_CLR_u registers. This is wrong,
because the macro does as follows:
>#define SET_BIT(num,pos) ((num) |= (1u << (pos)))
It will read the register and end up clearing *ALL* bits that are pending
during the write-back, as opposed to the specific one it needs to clear. If the
host is in the midst of processing an interrupt from a given core when a second
core writes to its (sub)mailbox, the second payload may be lost.
This commit changes the SET_BIT call to a direct register assignment of the
appropriate bit mask.
Signed-off-by: VW <vwan@ti.com>
The mailbox interrupt handling code in QNX IPC uses the SET_BIT macro to
clear status bits from the MAILBOX_IRQSTATUS_CLR_u registers. This is wrong,
because the macro does as follows:
>#define SET_BIT(num,pos) ((num) |= (1u << (pos)))
It will read the register and end up clearing *ALL* bits that are pending
during the write-back, as opposed to the specific one it needs to clear. If the
host is in the midst of processing an interrupt from a given core when a second
core writes to its (sub)mailbox, the second payload may be lost.
This commit changes the SET_BIT call to a direct register assignment of the
appropriate bit mask.
Signed-off-by: VW <vwan@ti.com>
qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/omap5430/Omap5430IpcInt.c | diff | blob | history | |
qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c | diff | blob | history |