Add data memory barrier to transport swi function
authorRamsey Harris <ramsey@ti.com>
Fri, 8 May 2015 00:16:17 +0000 (17:16 -0700)
committerRobert Tivy <rtivy@ti.com>
Fri, 8 May 2015 00:41:42 +0000 (17:41 -0700)
commit6286194ded34439e8668626dbe30954fec9fa28d
tree9c92cefd29ac78013c310dfcfe3a6163b7dace2f
parentd01cc0e86a59f3d7c84e9e0a7b965e26c3731b35
Add data memory barrier to transport swi function

On ARM processor, observed stale data in cache when attempting
to deliver an inbound message. This resulted in undelivered
message. Adding the DMB instruction seems to help, but I'm
unable to explain the exact failure details.
packages/ti/sdo/ipc/transports/TransportShm.c