TMP: listMP: Add Cache operation for v8A
authorSam Nelson <sam.nelson@ti.com>
Tue, 27 Mar 2018 12:43:34 +0000 (08:43 -0400)
committerSam Nelson <sam.nelson@ti.com>
Thu, 9 Aug 2018 20:01:32 +0000 (16:01 -0400)
commite8c3e35a110bca6fd4ba03dd3553953fffc8e540
treeb1d3699f9a1841357f0796578ea36962cbfbe295
parent67e9c143d14dfd50ce18dc07d700bc71a6583500
TMP: listMP: Add Cache operation for v8A

Ideally with the coherence working between A53 and R5F, there is no
cache operations required from A53 side. But the coherence operations
requires the ISC registers configured for R5F transactions to be non-
secure.
Adding this as temporary workaround.

Signed-off-by: Sam Nelson <sam.nelson@ti.com>
packages/ti/sdo/ipc/ListMP.c