SDOCM00116544 Cache management for ARM speculative execution
authorRamsey Harris <ramsey@ti.com>
Wed, 20 May 2015 15:08:24 +0000 (08:08 -0700)
committerRobert Tivy <rtivy@ti.com>
Wed, 20 May 2015 23:40:05 +0000 (16:40 -0700)
commitf2ad3ee2d55ddf594f9e3170618c738967760030
tree4b17f9f4b2e9491794af520f0a6db61009baf5fb
parent1edaf9dbdd0d9eee12ef3141491ff0eac410e2c7
SDOCM00116544 Cache management for ARM speculative execution

The ARM Cortex-A15 processor performs speculative execution on
the instruction stream. This might pull unwanted data into the
cache. The ListMP module expects shared data to be absent from
the cache. However, when running on ARM, we cannot count on the
data to be absent from the cache. A cache invalidate operation
is required.
packages/ti/sdo/ipc/GateMP.c
packages/ti/sdo/ipc/ListMP.c
packages/ti/sdo/ipc/transports/TransportShm.c