| author | Robert Tivy <rtivy@ti.com> | |
| Tue, 8 Apr 2014 23:11:20 +0000 (16:11 -0700) | ||
| committer | Chris Ring <cring@ti.com> | |
| Wed, 9 Apr 2014 19:57:51 +0000 (12:57 -0700) | ||
| commit | f3e274d472966b3a7a89aa7c3732251647461127 | |
| tree | 0a0e52daab82064444af3c6bccf73901c9b07856 | tree | snapshot (tar.xz tar.gz zip) |
| parent | b9f650ae5cb543b741f3961b0184a26a944884a2 | commit | diff |
Create Keystone platform instances with no external DDR defined
On MAR-based cores (i.e., C6x), SYS/BIOS will, by default, set the
"cacheable" bit for any external memory that it "sees", i.e., any
external memory that is defined for the platform. This happens regardless
of whether or not that memory is used for program placement. This
cacheable-ness is somewhat hidden to the programmer.
In order to offer better control of this, Keystone platform instances are
created with no external memory defined. This allows all MAR pages to be
tagged "non-cached" by default, and the programmer is free to set MAR bits
to their liking.
On MAR-based cores (i.e., C6x), SYS/BIOS will, by default, set the
"cacheable" bit for any external memory that it "sees", i.e., any
external memory that is defined for the platform. This happens regardless
of whether or not that memory is used for program placement. This
cacheable-ness is somewhat hidden to the programmer.
In order to offer better control of this, Keystone platform instances are
created with no external memory defined. This allows all MAR pages to be
tagged "non-cached" by default, and the programmer is free to set MAR bits
to their liking.
| ipc-bios.bld | diff | blob | history | |
| packages/ti/ipc/tests/package.bld | diff | blob | history |