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raw | patch | inline | side by side (parent: 6d84b09)
raw | patch | inline | side by side (parent: 6d84b09)
author | Chris Ring <cring@ti.com> | |
Thu, 3 Apr 2014 23:57:00 +0000 (16:57 -0700) | ||
committer | Chris Ring <cring@ti.com> | |
Fri, 4 Apr 2014 00:12:52 +0000 (17:12 -0700) |
Note virtio in this case is the virtualized platform, not the
protocol rpmsg is built on.
We no longer support OMAP5 or DRA7XX-based virtio platforms,
this commit removes related preprocessor defines set in makefiles
and used throughout the code base.
protocol rpmsg is built on.
We no longer support OMAP5 or DRA7XX-based virtio platforms,
this commit removes related preprocessor defines set in makefiles
and used throughout the code base.
diff --git a/ipc-qnx.mak b/ipc-qnx.mak
index b2922eb3f83a2b0007d9dcc4d91fab697c17fcc5..9025702023596a711115a193f831726ef0ed729f 100644 (file)
--- a/ipc-qnx.mak
+++ b/ipc-qnx.mak
@echo "building Qnx user libraries for \"$(PLATFORM)\" platform..."
@make -C qnx \
IPC_REPO=`pwd` \
- PLATFORM=$(PLATFORM) \
- BUILD_FOR_VIRTIO=false
+ PLATFORM=$(PLATFORM)
clean:
@echo "cleaning Qnx user libraries ..."
@make -C qnx \
IPC_REPO=`pwd` \
PLATFORM=$(PLATFORM) \
- BUILD_FOR_VIRTIO=false \
DESTDIR=$(DESTDIR) \
install
diff --git a/qnx/Makefile b/qnx/Makefile
index 20a1b41333462dcbe806ed0b55355284d81ff8f6..5ff806c198f73f25d2f1f9db164e4c81f9c34f13 100644 (file)
--- a/qnx/Makefile
+++ b/qnx/Makefile
ipc3x_dev: utils
@cd src/ipc3x_dev; \
- make SYSLINK_PLATFORM=$(SYSLINK_PLATFORM) SMP=1 VIRTIO=$(BUILD_FOR_VIRTIO)
+ make SYSLINK_PLATFORM=$(SYSLINK_PLATFORM) SMP=1
install:
@cd src/ipc3x_dev; make SYSLINK_PLATFORM=$(SYSLINK_PLATFORM) \
- SMP=1 VIRTIO=$(BUILD_FOR_VIRTIO) USE_INSTALL_ROOT=1 \
+ SMP=1 USE_INSTALL_ROOT=1 \
INSTALL_ROOT_nto=$(DESTDIR) install
@cd src/mm; make USE_INSTALL_ROOT=1 DESTDIR=$(DESTDIR) \
INSTALL_ROOT_nto=$(DESTDIR) install
@cd src/utils; make clean
@cd src/tests; make clean
@cd src/ipc3x_dev; \
- make clean SYSLINK_PLATFORM=$(SYSLINK_PLATFORM) SMP=1 VIRTIO=$(BUILD_FOR_VIRTIO)
+ make clean SYSLINK_PLATFORM=$(SYSLINK_PLATFORM) SMP=1
diff --git a/qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/common.mk b/qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/common.mk
index 0de8f9e8bf109ae6b0cff40d2b320e098621999f..bbc467d145891d829305878eff591eebe59298e8 100644 (file)
#
-# Copyright (c) 2013, Texas Instruments Incorporated
+# Copyright (c) 2013-2014, Texas Instruments Incorporated
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
CCOPTS += -DSYSLINK_BUILDOS_QNX -DSYSLINK_BUILD_DEBUG -DSYSLINK_BUILD_HLOS
-# TODO: Is this macro used anymore? If not, remove it.
-USE_MEMMGR=false
ifeq ("$(SYSLINK_DEBUG)", "1")
#enable debug build
CCOPTS += -g -O0
endif # ifeq ("$(SYSLINK_DEBUG)", "1")
ifeq ("$(SYSLINK_PLATFORM)", "omap5430")
-ifeq ("$(VIRTIO)", "true")
-CCOPTS += -DOMAP5430_VIRTIO
-endif # ifeq ("$(VIRTIO)", "true")
ifeq ("$(SMP)", "1")
CCOPTS += -DSYSLINK_SYSBIOS_SMP
endif # ifeq ("$(SMP)", "1")
endif # ifeq ("$(SYSLINK_PLATFORM)", "omap5430")
ifeq ("$(SYSLINK_PLATFORM)", "vayu")
-ifeq ("$(VIRTIO)", "true")
-CCOPTS += -DVAYU_VIRTIO
-endif # ifeq ("$(VIRTIO)", "true")
ifeq ("$(SMP)", "1")
CCOPTS += -DSYSLINK_SYSBIOS_SMP
endif # ifeq ("$(SMP)", "1")
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c
index 6781bb2e3399a3bd14726dd66446610ccec681a3..d0de52b4c9ba7934ab8486041457102286e7f203 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * Contact information for paper mail:
- * Texas Instruments
- * Post Office Box 655303
- * Dallas, Texas 75265
- * Contact information:
- * http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm?
- * DCMP=TIHomeTracking&HQS=Other+OT+home_d_contact
- * ============================================================================
- *
*/
-
-
#if defined(SYSLINK_BUILD_RTOS)
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
/* Enable the DSP clock */
addr = cmBase + CM_DSP_CLKSTCTRL;
OUTREG32(addr, 0x02);
-#ifndef VAYU_VIRTIO
+
do {
val = INREG32(addr);
if (val & 0x100) {
status = -1;
break;
}
-#endif
+
/* Check that releasing resets would indeed be effective */
addr = prmBase + RM_DSP_RSTCTRL;
val = INREG32(addr);
Osal_printf("DSP Resets in not proper state! [0x%x]\n", val);
OUTREG32(addr, 0x3);
counter = 1000;
-#ifndef VAYU_VIRTIO
+
while ((--counter)&&((INREG32(addr) & 0x3) != 0x3));
if (counter == 0) {
Osal_printf("RESET bits not set in DSP reset Ctrl!\n");
status = -1;
break;
}
-#endif
}
/* De-assert RST2, and clear the Reset status */
OUTREG32(addr, 0x1);
addr = prmBase + RM_DSP_RSTST;
-#ifndef VAYU_VIRTIO
+
while (!((INREG32(addr))& 0x2));
-#endif
+
Osal_printf("DSP:RST2 released!\n");
OUTREG32(addr, 0x2);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0HalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0HalReset.c
index ba3405d9edf39015716228bdad6d06838bf09f92..06dd59f5b268427ac8e4048cdf6b9704d8c6681f 100644 (file)
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * Contact information for paper mail:
- * Texas Instruments
- * Post Office Box 655303
- * Dallas, Texas 75265
- * Contact information:
- * http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm?
- * DCMP=TIHomeTracking&HQS=Other+OT+home_d_contact
- * ============================================================================
- *
*/
-
-
#include <ti/syslink/Std.h>
/* OSAL & Utils headers */
}
} while (--counter);
-#ifndef VAYU_VIRTIO // skip this check
if (counter == 0) {
Osal_printf("FAILED TO ENABLE IPU CLOCK !\n");
return PROCESSOR_E_OSFAILURE;
}
-#endif
/* Check that releasing resets would indeed be effective */
reg = INREG32(prmBase + RM_IPU_RSTCTRL_OFFSET);
Osal_printf("De-assert RST3\n");
CLRBITREG32(prmBase + RM_IPU_RSTCTRL_OFFSET, 2);
-#ifndef VAYU_VIRTIO // skip this check, reset status not modeled properly
while (!(INREG32(prmBase + RM_IPU_RSTST_OFFSET) & 0x4));
Osal_printf("RST3 released!\n");
SETBITREG32(prmBase + RM_IPU_RSTST_OFFSET, 2);
-#endif
}
break;
Osal_printf("De-assert RST2\n");
CLRBITREG32(prmBase + RM_IPU_RSTCTRL_OFFSET, 1);
-#ifndef VAYU_VIRTIO // skip this check for now
while (!(INREG32(prmBase + RM_IPU_RSTST_OFFSET) & 0x3));
Osal_printf("RST1 & RST2 released!");
SETBITREG32(prmBase + RM_IPU_RSTST_OFFSET, 0);
SETBITREG32(prmBase + RM_IPU_RSTST_OFFSET, 1);
-#endif
#else
/*Bring ONLY Benelli M4_0 out of Reset*/
/* De-assert RST1, and clear the Reset status */
Osal_printf("De-assert RST1\n");
CLRBITREG32(prmBase + RM_IPU_RSTCTRL_OFFSET, 0);
-#ifndef VAYU_VIRTIO // skip this check for now
while (!(INREG32(prmBase + RM_IPU_RSTST_OFFSET) & 0x1));
Osal_printf("RST1 released!");
SETBITREG32(prmBase + RM_IPU_RSTST_OFFSET, 0);
-#endif
#endif
/* Setting to HW_AUTO Mode */
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore1/VAYUIpuCore1HalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore1/VAYUIpuCore1HalReset.c
index 3bd4f7b69e98a113792165853c305a420f17aeeb..e9b5b40e053af4f84bdf21269f735742fcf382a9 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * Contact information for paper mail:
- * Texas Instruments
- * Post Office Box 655303
- * Dallas, Texas 75265
- * Contact information:
- * http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm?
- * DCMP=TIHomeTracking&HQS=Other+OT+home_d_contact
- * ============================================================================
- *
*/
-
-
#include <ti/syslink/Std.h>
/* OSAL & Utils headers */
Osal_printf("De-assert RST2\n");
CLRBITREG32(prmBase + RM_IPU_RSTCTRL_OFFSET, 1);
-#ifndef VAYU_VIRTIO // skip this check for now
while (!(INREG32(prmBase + RM_IPU_RSTST_OFFSET) & 0x2));
Osal_printf("RST2 released!");
SETBITREG32(prmBase + RM_IPU_RSTST_OFFSET, 1);
-#endif
/* Setting to HW_AUTO Mode */
reg = INREG32(cmBase + CM_IPU_CLKSTCTRL_OFFSET);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/ipu/ipu_pm.c b/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/ipu/ipu_pm.c
index 277b81a9c0930a890bb32cc953d2a0f32ecc88d8..ae177119b438f52478f86ec4b709351edcdeb900 100644 (file)
/*
- * Copyright (c) 2011-2013, Texas Instruments Incorporated
+ * Copyright (c) 2011-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
/* Ensure that the wake up mode is set to SW_WAKEUP */
out32(cm_base + cm_iva_clkstctrl_offset, 0x00000002);
-#ifndef OMAP5_VIRTIO
/* Check the standby status */
do {
if (((in32(cm_base + cm_iva_iva_clkctrl_offset) & 0x00040000) != 0x0))
if (max_tries == 0) {
GT_0trace(curTrace, GT_4CLASS," ** Error in IVAHD standby status");
}
-#endif
// IVAHD_CM2:CM_IVAHD_IVAHD_CLKCTRL
out32(cm_base + cm_iva_iva_clkctrl_offset, 0x00000000);
-#ifndef OMAP5_VIRTIO
+
max_tries = 100;
do {
if((in32(cm_base + cm_iva_iva_clkctrl_offset) & 0x00030000) == 0x30000)
if (max_tries == 0) {
GT_0trace(curTrace, GT_4CLASS," ** Error in IVAHD standby status");
}
-#endif
// IVAHD_CM2:CM_IVAHD_SL2_CLKCTRL
out32(cm_base + cm_iva_sl2_clkctrl_offset, 0x00000000);
-#ifndef OMAP5_VIRTIO
+
max_tries = 100;
do {
if((in32(cm_base + cm_iva_sl2_clkctrl_offset) & 0x00030000) == 0x30000);
if (max_tries == 0) {
GT_0trace(curTrace, GT_4CLASS," ** Error in SL2 CLKCTRL");
}
-#endif
/* put IVA into HW Auto mode */
out32(cm_base + cm_iva_clkstctrl_offset, 0x00000003);
max_tries = 100;
/* Check CLK ACTIVITY bit */
-#ifndef OMAP5_VIRTIO
+
while(((in32(cm_base + cm_iva_clkstctrl_offset) & 0x00000100) != 0x0) && --max_tries);
if (max_tries == 0)
GT_0trace(curTrace, GT_4CLASS, "SYSLINK: ivahd_disable: WARNING - CLK ACTIVITY bit did not go off");
-#endif
// IVA sub-system resets - Assert reset for IVA logic and SL2
out32(pm_base + rm_iva_rstctrl_offset, 0x00000004);
/* Ensure that the wake up mode is set to SW_WAKEUP */
out32(cm_base + cm_iva_clkstctrl_offset, 0x00000002);
-#ifndef OMAP5_VIRTIO
max_tries = 100;
while(((in32(pm_base + pm_iva_pwrstst_offset) & 0x00100000) != 0) && --max_tries);
if (max_tries == 0)
GT_0trace(curTrace, GT_4CLASS, "SYSLINK: ivahd_enable: WARNING - PwrSt did not transition");
-#endif
// IVAHD_CM2:CM_IVAHD_IVAHD_CLKCTRL
out32(cm_base + cm_iva_iva_clkctrl_offset, 0x00000001);
out32(cm_base + cm_iva_sl2_clkctrl_offset, 0x00000001);
/* Wait until the CLK_ACTIVITY bit is set */
-#ifndef OMAP5_VIRTIO
max_tries = 100;
while (((in32(cm_base + cm_iva_clkstctrl_offset) & 0x00000100) == 0x0) && --max_tries);
if (max_tries == 0)
GT_0trace(curTrace, GT_4CLASS, "SYSLINK: ivahd_enable: WARNING - Clk_ACTIVITY bit is not set");
-#endif
/* Release ICONT1 and SL2/IVAHD first, wait for few usec then release ICONT2 */
reg = in32(pm_base + rm_iva_rstctrl_offset);
reg &= 0xFFFFFFFB;
out32(pm_base + rm_iva_rstctrl_offset, reg);
-#ifndef OMAP5_VIRTIO
+
max_tries = 100;
usleep(100);
do {
GT_0trace(curTrace, GT_4CLASS," ** SL2 is not functional");
return -EIO;
}
-#endif
} else {
GT_0trace(curTrace, GT_3CLASS, "ivahd already acquired");
}
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/ipu/omap5430BenelliHalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/ipu/omap5430BenelliHalReset.c
index c7985f33b36c6fcc15576e244b8eb0fdf22934e9..6d70eda02a131ccda5776a767efa6c4ab81a9056 100644 (file)
/*
- * Copyright (c) 2010-2013, Texas Instruments Incorporated
+ * Copyright (c) 2010-2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
SETBITREG32(IPURstCtrl, RM_IPU_RST1_BIT);
/* Read back the reset control register */
reg = INREG32(IPURstCtrl);
-#ifndef OMAP5430_VIRTIO // skip this for now, not using gptimers
+
/* Disable the GPT3 clock, which is used by CORE0 */
ret = ipu_pm_gpt_stop(GPTIMER_3);
if (ret != EOK) {
status,
"Failed to disable gpt 3");
}
-#endif
break;
#ifndef SYSLINK_SYSBIOS_SMP
case PROCTYPE_IPU1:
/* Put IPU core 1 into reset */
SETBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
-#ifndef OMAP5430_VIRTIO // skip this check, reset status not modeled properly
+
/* Disable the GPT4 clock, which is used by CORE1 */
ret = ipu_pm_gpt_stop(GPTIMER_4);
if (ret != EOK) {
status,
"Failed to disable gpt 4");
}
-#endif
break;
#endif
case PROCTYPE_DSP:
}
} while (--counter);
-#ifndef OMAP5430_VIRTIO // skip this check
if (counter == 0) {
Osal_printf("FAILED TO ENABLE IPU CLOCK !");
return PROCESSOR_E_OSFAILURE;
}
-#endif
/* Check that releasing resets would indeed be
* effective */
Osal_printf("De-assert RST3");
CLRBITREG32(IPURstCtrl, RM_IPU_RST3_BIT);
-#ifndef OMAP5430_VIRTIO // skip this check, reset status not modeled properly
counter = 10;
do {
if (INREG32(IPURstSt) & RM_IPU_RST3ST)
SETBITREG32(IPURstSt, RM_IPU_RST3ST_BIT);
}
}
-#endif
break;
#ifndef SYSLINK_SYSBIOS_SMP
case PROCTYPE_IPU1:
{
switch (halObject->procId) {
case PROCTYPE_IPU0:
-#ifndef OMAP5430_VIRTIO // skip this for now, not using gptimers
/* Enable the GPT3 clock, which is used by CORE0 */
ret = ipu_pm_gpt_enable(GPTIMER_3);
if (ret != EOK) {
"Failed to start gpt 3");
}
else {
-#endif // ifndef OMAP5430_VIRTIO
/* De-assert RST1, and clear the Reset status */
Osal_printf("De-assert RST1");
CLRBITREG32(IPURstCtrl, RM_IPU_RST1_BIT);
-#ifndef OMAP5430_VIRTIO // skip this check for now
counter = 10;
do {
if (INREG32(IPURstSt) & RM_IPU_RST1)
"Failed to release RST1");
}
else {
-#endif // ifndef OMAP5430_VIRTIO
Osal_printf("RST1 released!");
SETBITREG32(IPURstSt, RM_IPU_RST1ST_BIT);
#ifdef SYSLINK_SYSBIOS_SMP
/* De-assert RST2, and clear the Reset status */
CLRBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
-#ifndef OMAP5430_VIRTIO // skip this check for now
+
counter = 10;
do {
if (INREG32(IPURstSt) & RM_IPU_RST2)
"Failed to release RST2");
}
else {
-#endif // ifndef OMAP5430_VIRTIO
Osal_printf("RST2 released!");
SETBITREG32(IPURstSt, RM_IPU_RST2ST_BIT);
-#ifndef OMAP5430_VIRTIO // skip this check for now
}
-#endif // ifndef OMAP5430_VIRTIO
#endif // ifdef SYSLINK_SYSBIOS_SMP
-#ifndef OMAP5430_VIRTIO // skip this check for now
}
}
}
-#endif // ifndef OMAP5430_VIRTIO
break;
#ifndef SYSLINK_SYSBIOS_SMP
case PROCTYPE_IPU1:
-#ifndef OMAP5430_VIRTIO // skip this for now, not using gptimers
/* Enable the GPT4 clock, which is used by CORE1 */
ret = ipu_pm_gpt_enable(GPTIMER_4);
if (ret != EOK) {
else {
restore_gpt_context(GPTIMER_4);
ipu_pm_gpt_start(GPTIMER_4);
-#endif
/* De-assert RST2, and clear the Reset status */
CLRBITREG32(IPURstCtrl, RM_IPU_RST2_BIT);
-#ifndef OMAP5430_VIRTIO // skip this check for now
counter = 10;
do {
if (INREG32(IPURstSt) & RM_IPU_RST2)
else {
Osal_printf("RST2 released!");
SETBITREG32(IPURstSt, RM_IPU_RST2ST_BIT);
-#endif
+
/* Wait until benelli is in idle */
//while(TESTBITREG32(IPUClkStCtrl,
// CM_IPU_CLKSTCTRL_CLKACTIVITY_BIT));
-#ifndef OMAP5430_VIRTIO // skip this check for now
}
-#endif
}
break;
#endif