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raw | patch | inline | side by side (parent: 73882d9)
raw | patch | inline | side by side (parent: 73882d9)
| author | vwan@ti.com <vwan@ti.com> | |
| Wed, 19 Feb 2014 19:51:31 +0000 (11:51 -0800) | ||
| committer | Chris Ring <cring@ti.com> | |
| Fri, 21 Feb 2014 16:39:56 +0000 (08:39 -0800) |
This commit adds support for IPU1 in QNX. It has the current limitation that
the core cannot be put into deep sleep in the idle task, so the function
IpcPower_idle() must be removed from the idle loop. This issue will be fixed
at a later time.
Signed-off-by: VW <vwan@ti.com>
the core cannot be put into deep sleep in the idle task, so the function
IpcPower_idle() must be removed from the idle loop. This issue will be fixed
at a later time.
Signed-off-by: VW <vwan@ti.com>
12 files changed:
diff --git a/qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/syslink_main.c b/qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/syslink_main.c
index aeda4ebedd31f0415cb51aa923e647b79550338d..40950d06cefabbbaf5ab4e79b2fcf15f59120a5c 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2011-2013, Texas Instruments Incorporated
+ * Copyright (c) 2011-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -645,6 +645,12 @@ int init_ipc(syslink_dev_t * dev, syslink_firmware_info * firmware, bool recover
goto ipcattach_fail;
}
+ status = ProcMgr_registerNotify(procH[procId], syslink_error_cb, (Ptr)dev,
+ -1, errStates);
+ if (status < 0) {
+ goto procmgrreg_fail;
+ }
+
status = ProcMgr_start(procH[procId], NULL);
if (status < 0) {
GT_setFailureReason (curTrace,
@@ -655,16 +661,12 @@ int init_ipc(syslink_dev_t * dev, syslink_firmware_info * firmware, bool recover
goto procmgrstart_fail;
}
- status = ProcMgr_registerNotify(procH[procId], syslink_error_cb, (Ptr)dev,
- -1, errStates);
- if (status < 0)
- goto procmgrreg_fail;
-
continue;
-procmgrreg_fail:
- ProcMgr_stop(procH[procId]);
procmgrstart_fail:
+ ProcMgr_unregisterNotify(procH[procId], syslink_error_cb,
+ (Ptr)dev, errStates);
+procmgrreg_fail:
Ipc_detach(procId);
ipcattach_fail:
if (syslink_firmware[i].firmware)
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/VAYUIpuMmu.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/VAYUIpuMmu.c
index 283db9160b5f0541a98a64158e799dbe8c7e929f..d29fe98d339091b75d40d0bd5864f49aa88cde9e 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
#define REG(x) *((volatile UInt32 *) (x))
-
-#define RM_DEFAULT_RSTCTRL 0x00000B10
-#define RM_DEFAULT_RSTST 0x00000B14
-#define CM_DEFAULT_IPU_CLKSTCTRL 0x00000518
-#define CM_DEFAULT_IPU_CLKCTRL 0x00000574
-
-
#if defined (__cplusplus)
extern "C" {
#endif
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/VAYUIpuPhyShmem.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/VAYUIpuPhyShmem.c
index 0d23ed7a416fbbeedd7254d4e9016a5f10816043..ec71fca496633c0b84de5a93511860a644905f1a 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
/* Module headers */
#include <_ProcDefs.h>
#include <Processor.h>
-
+#include <_MultiProc.h>
/* Hardware Abstraction Layer headers */
#include <VAYUIpuHal.h>
Int status = PROCESSOR_SUCCESS;
VAYUIPU_HalObject * halObject = NULL;
Memory_MapInfo mapInfo;
+ UInt16 ipu1ProcId = MultiProc_getId("IPU1");
GT_1trace (curTrace, GT_ENTER, "VAYUIPU_phyShmemInit", halObj);
halObject = (VAYUIPU_HalObject *) halObj;
- mapInfo.src = CM_BASE_ADDR;
+ if (halObject->procId == ipu1ProcId) {
+ mapInfo.src = IPU1_CM_BASE_ADDR;
+ }
+ else {
+ mapInfo.src = IPU2_CM_BASE_ADDR;
+ }
+
mapInfo.size = CM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
halObject->cmBase = mapInfo.dst;
}
- mapInfo.src = PRCM_BASE_ADDR;
+ if (halObject->procId == ipu1ProcId) {
+ mapInfo.src = IPU1_PRCM_BASE_ADDR;
+ }
+ else {
+ mapInfo.src = IPU2_PRCM_BASE_ADDR;
+ }
mapInfo.size = PRCM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
halObject->prmBase = mapInfo.dst;
}
- mapInfo.src = MMU_BASE;
+ if (halObject->procId == ipu1ProcId) {
+ mapInfo.src = IPU1_MMU_BASE;
+ }
+ else {
+ mapInfo.src = IPU2_MMU_BASE;
+ }
+
mapInfo.size = MMU_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/VAYUIpuPwr.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/VAYUIpuPwr.c
index 05b9b5908fe0ec0276c6a6f7a01c4432e7f2f45f..46d6747c3dbff254d2783fb541d5172b833b906e 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
#include <ti/syslink/inc/knl/VAYUIpuPwr.h>
#include <ti/syslink/inc/knl/_VAYUIpuPwr.h>
#include <ti/syslink/inc/knl/Qnx/VAYUIpuMmu.h>
+#include <ti/syslink/inc/knl/VAYUIpuPhyShmem.h>
#if defined (__cplusplus)
extern "C" {
* @brief VAYUIPU module and mmr addresses (physical)
*/
-#define VAYUIPU_PRCM_BASE_ADDR 0x48180000
-#define VAYUIPU_PRCM_SIZE 0x00002FFF
-
-/* Ipu MMU base */
-#define IPU_MMU_CFG 0x55080000
-#define IPU_MMU_CFG_SIZE 0x00000FFF
-
-
-#define IPU_BASE_ADDR 0x55020000
-#define IPU_BASE_ADDR_SIZE 0x00000008
#define MAX_WAIT_COUNT 0x50000
Int status = PWRMGR_SUCCESS;
PwrMgr_Object * pwrMgrHandle = (PwrMgr_Object *) handle;
- VAYUIPUPWR_Object * object = NULL;
+ VAYUIPUPWR_Object * object = NULL;
+ UInt16 ipu1ProcId = MultiProc_getId("IPU1");
Memory_MapInfo mapInfo;
/* Mapping for prcm base is done in VAYUIPUCORE1_phyShmemInit */
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
object = (VAYUIPUPWR_Object *) pwrMgrHandle->object;
GT_assert (curTrace, (object != NULL));
- /* Map and get the virtual address for system control module */
- mapInfo.src = VAYUIPU_PRCM_BASE_ADDR;
- mapInfo.size = VAYUIPU_PRCM_SIZE;
+ /* Map and get the virtual address for PRCM registers */
+ if (handle->procId == ipu1ProcId) {
+ mapInfo.src = IPU1_PRCM_BASE_ADDR;
+ }
+ else {
+ mapInfo.src = IPU2_PRCM_BASE_ADDR;
+ }
+ mapInfo.size = PRCM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
object->prcmVA = mapInfo.dst;
- /* Map and get the virtual address for system control module */
- mapInfo.src = IPU_MMU_CFG;
- mapInfo.size = IPU_MMU_CFG_SIZE;
+ /* Map and get the virtual address for MMU registers */
+ if (handle->procId == ipu1ProcId) {
+ mapInfo.src = IPU1_MMU_BASE;
+ }
+ else {
+ mapInfo.src = IPU2_MMU_BASE;
+ }
+ mapInfo.size = MMU_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
object->ipuMmuVA = mapInfo.dst;
- /* Map and get the virtual address for system control module */
- mapInfo.src = IPU_BASE_ADDR;
- mapInfo.size = IPU_BASE_ADDR_SIZE;
+ /* Map and get the virtual address for the control module */
+ if (handle->procId == ipu1ProcId) {
+ mapInfo.src = IPU1_CM_BASE_ADDR;
+ }
+ else {
+ mapInfo.src = IPU2_CM_BASE_ADDR;
+ }
+ mapInfo.size = CM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
/* Unmap the virtual address for prcm module */
unmapInfo.addr = object->prcmVA;
- unmapInfo.size = VAYUIPU_PRCM_SIZE;
+ unmapInfo.size = PRCM_SIZE;
unmapInfo.isCached = FALSE;
if (unmapInfo.addr != 0) {
status = Memory_unmap (&unmapInfo);
}
/* Unmap the virtual address for mmu base*/
unmapInfo.addr = object->ipuMmuVA;
- unmapInfo.size = IPU_MMU_CFG_SIZE;
+ unmapInfo.size = MMU_SIZE;
unmapInfo.isCached = FALSE;
if (unmapInfo.addr != 0) {
status = Memory_unmap (&unmapInfo);
/* Unmap the virtual address for ipu control base */
unmapInfo.addr = object->ipubaseVA;
- unmapInfo.size = IPU_BASE_ADDR_SIZE;
+ unmapInfo.size = CM_SIZE;
unmapInfo.isCached = FALSE;
if (unmapInfo.addr != 0) {
status = Memory_unmap (&unmapInfo);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0HalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0HalReset.c
index 48d41179e919ccaf449cb6c4b140dc4baa30e117..ba3405d9edf39015716228bdad6d06838bf09f92 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
#define CM_IPU_CLKSTCTRL_OFFSET 0x200
#define CM_IPU_IPU_CLKCTRL_OFFSET 0x220
+/*
+ * empirically determined delay that is necessary between when the IPU
+ * clock is enabled and when the status bit is set
+ */
+#define DELAY 100
+
+/*
+ * IPU1 functional clock selection
+ * 0: DPLL_ABE_X2_CLK
+ * 1: CORE_IPU_ISS_BOOST_CLK
+ */
+#define USE_CORE_IPU_ISS_BOOST_CLK 1
+
+#if USE_CORE_IPU_ISS_BOOST_CLK
+#define IPU1_CLKSEL 0x1000000
+#else
+#define IPU1_CLKSEL 0x0
+#endif
/* =============================================================================
* APIs called by VAYUIPUCORE0PROC module
UInt32 cmBase;
UInt32 prmBase;
UInt32 reg = 0;
- UInt32 counter = 10;
+ UInt32 counter = DELAY;
GT_2trace (curTrace, GT_ENTER, "VAYUIPUCORE0_halResetCtrl", halObj, cmd);
Osal_printf("VAYUIPUCORE0_halResetCtrl: reset state reset!\n");
}
/* Module is managed automatically by HW */
- OUTREG32(cmBase + CM_IPU_IPU_CLKCTRL_OFFSET, 0x1);
+ if (halObject->procId == MultiProc_getId("IPU1")) {
+ /* For IPU1, select CORE_IPU_ISS_BOOST_CLK as functional clk */
+ OUTREG32(cmBase + CM_IPU_IPU_CLKCTRL_OFFSET, 0x1 | IPU1_CLKSEL);
+ }
+ else {
+ OUTREG32(cmBase + CM_IPU_IPU_CLKCTRL_OFFSET, 0x1);
+ }
/* Enable the IPU clock */
OUTREG32(cmBase + CM_IPU_CLKSTCTRL_OFFSET, 0x2);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0Proc.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0Proc.c
index c0d92d0211afe15f00a3d0baf0419747cb8d9507..c11ac58aeee105c51fc0a3285f4e688dde97dfbf 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
*/
#define AddrTable_SIZE 32
+/* Number of IPUs supported */
+#define NUM_IPUS 2
+
+/* Convert procId to IPU # */
+#define PROCID_TO_IPU(procId) (procId == VAYUIPUCORE0PROC_state.ipu1ProcId ?\
+ 0 : 1)
+
#define PARAMS_MAX_NAMELENGTH 64
/* Config param for L2MMU. This is not a typo, we are using the
* same name (IPU1) because both Benelli M4 processors use the
- * same L2MMU. The docs expose IPU2 but not the IPU2 Core1 processor.
+ * same L2MMU. The docs expose IPUx but not the IPUx Core1 processor.
*/
-#define PARAMS_mmuEnable "ProcMgr.proc[IPU2].mmuEnable="
-#define PARAMS_carveoutAddr "ProcMgr.proc[IPU2].carveoutAddr"
-#define PARAMS_carveoutSize "ProcMgr.proc[IPU2].carveoutSize"
+#define PARAMS_mmuEnable1 "ProcMgr.proc[IPU1].mmuEnable="
+#define PARAMS_carveoutAddr1 "ProcMgr.proc[IPU1].carveoutAddr"
+#define PARAMS_carveoutSize1 "ProcMgr.proc[IPU1].carveoutSize"
+#define PARAMS_mmuEnable2 "ProcMgr.proc[IPU2].mmuEnable="
+#define PARAMS_carveoutAddr2 "ProcMgr.proc[IPU2].carveoutAddr"
+#define PARAMS_carveoutSize2 "ProcMgr.proc[IPU2].carveoutSize"
/*!
/*!< Processor handle array. */
IGateProvider_Handle gateHandle;
/*!< Handle of gate to be used for local thread safety */
+ UInt16 ipu1ProcId;
+ /*!< MultiProc id of IPU1 (to avoid multiple lookups) */
} VAYUIPUCORE0PROC_ModuleObject;
-/* Default memory regions */
-static UInt32 AddrTable_count = AddrTable_STATIC_COUNT;
+/* Memory region counters */
+static UInt32 AddrTable_count[NUM_IPUS] = {
+ AddrTable_STATIC_COUNT,
+ AddrTable_STATIC_COUNT,
+};
/* static memory regions
* CAUTION: AddrTable_STATIC_COUNT must match number of entries below.
*/
-static ProcMgr_AddrInfo AddrTable[AddrTable_SIZE] =
+static ProcMgr_AddrInfo AddrTable_IPU1[AddrTable_SIZE] =
+{
+ /* L2 RAM */
+ {
+ .addr[ProcMgr_AddrType_MasterKnlVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterUsrVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterPhys] = 0x55020000u,
+ .addr[ProcMgr_AddrType_SlaveVirt] = 0x20000000u,
+ .addr[ProcMgr_AddrType_SlavePhys] = -1u,
+ .size = 0x10000u,
+ .isCached = FALSE,
+ .mapMask = ProcMgr_SLAVEVIRT,
+ .isMapped = TRUE,
+ .refCount = 0u /* refCount set to 0 for static entry */
+ },
+};
+
+static ProcMgr_AddrInfo AddrTable_IPU2[AddrTable_SIZE] =
+{
+ /* L2 RAM */
{
- /* L2 RAM */
- {
- .addr[ProcMgr_AddrType_MasterKnlVirt] = -1u,
- .addr[ProcMgr_AddrType_MasterUsrVirt] = -1u,
- .addr[ProcMgr_AddrType_MasterPhys] = 0x55020000u,
- .addr[ProcMgr_AddrType_SlaveVirt] = 0x20000000u,
- .addr[ProcMgr_AddrType_SlavePhys] = -1u,
- .size = 0x10000u,
- .isCached = FALSE,
- .mapMask = ProcMgr_SLAVEVIRT,
- .isMapped = TRUE,
- .refCount = 0u /* refCount set to 0 for static entry */
- },
- };
+ .addr[ProcMgr_AddrType_MasterKnlVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterUsrVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterPhys] = 0x55020000u,
+ .addr[ProcMgr_AddrType_SlaveVirt] = 0x20000000u,
+ .addr[ProcMgr_AddrType_SlavePhys] = -1u,
+ .size = 0x10000u,
+ .isCached = FALSE,
+ .mapMask = ProcMgr_SLAVEVIRT,
+ .isMapped = TRUE,
+ .refCount = 0u /* refCount set to 0 for static entry */
+ },
+};
+
+static ProcMgr_AddrInfo * AddrTable[NUM_IPUS] =
+{
+ AddrTable_IPU1,
+ AddrTable_IPU2
+};
/* =============================================================================
* Globals
.configSize = sizeof(VAYUIPUCORE0PROC_Config),
.gateHandle = NULL,
.defInstParams.mmuEnable = FALSE,
- .defInstParams.numMemEntries = AddrTable_STATIC_COUNT
+ .defInstParams.numMemEntries = AddrTable_STATIC_COUNT,
};
/* config override specified in SysLinkCfg.c, defined in ProcMgr.c */
Memory_set (&VAYUIPUCORE0PROC_state.procHandles,
0,
(sizeof (VAYUIPUCORE0PROC_Handle) * MultiProc_MAXPROCESSORS));
+
+ VAYUIPUCORE0PROC_state.ipu1ProcId = MultiProc_getId("IPU1");
VAYUIPUCORE0PROC_state.isSetup = TRUE;
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
VAYUIPUCORE0PROC_Params * params)
{
VAYUIPUCORE0PROC_Object *procObject = (VAYUIPUCORE0PROC_Object *)handle;
- Int i = 0;
- ProcMgr_AddrInfo *ai = NULL;
GT_2trace(curTrace, GT_ENTER, "VAYUIPUCORE0PROC_Params_init",
handle, params);
#endif
if (handle == NULL) {
- /* check for instance params override */
- Cfg_propBool(PARAMS_mmuEnable, ProcMgr_sysLinkCfgParams,
- &(VAYUIPUCORE0PROC_state.defInstParams.mmuEnable));
-
Memory_copy(params, &(VAYUIPUCORE0PROC_state.defInstParams),
sizeof (VAYUIPUCORE0PROC_Params));
-
- /* initialize the translation table */
- for (i = AddrTable_count; i < AddrTable_SIZE; i++) {
- ai = &AddrTable[i];
- ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterPhys] = -1u;
- ai->addr[ProcMgr_AddrType_SlaveVirt] = -1u;
- ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
- ai->size = 0u;
- ai->isCached = FALSE;
- ai->mapMask = 0u;
- ai->isMapped = FALSE;
- }
-
- /* initialize refCount for all entries - both static and dynamic */
- for (i = 0; i < AddrTable_SIZE; i++) {
- AddrTable[i].refCount = 0u;
- }
- Memory_copy((Ptr)params->memEntries, AddrTable, sizeof(AddrTable));
}
else {
/* return updated VAYUIPUCORE0PROC instance specific parameters */
VAYUIPUCORE0PROC_create ( UInt16 procId,
const VAYUIPUCORE0PROC_Params * params)
{
- Int status = PROCESSOR_SUCCESS;
- Processor_Object * handle = NULL;
- VAYUIPUCORE0PROC_Object * object = NULL;
+ Int status = PROCESSOR_SUCCESS;
+ Processor_Object * handle = NULL;
+ VAYUIPUCORE0PROC_Object * object = NULL;
+ Int i = 0;
+ ProcMgr_AddrInfo *ai = NULL;
IArg key;
List_Params listParams;
(Ptr) params,
sizeof (VAYUIPUCORE0PROC_Params));
+ /* initialize the translation table */
+ for (i = AddrTable_count[PROCID_TO_IPU(procId)];
+ i < AddrTable_SIZE; i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procId)][i];
+ ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterPhys] = -1u;
+ ai->addr[ProcMgr_AddrType_SlaveVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
+ ai->size = 0u;
+ ai->isCached = FALSE;
+ ai->mapMask = 0u;
+ ai->isMapped = FALSE;
+ }
+
+ /*
+ * initialize refCount for all entries
+ * both static and dynamic
+ */
+ for (i = 0; i < AddrTable_SIZE; i++) {
+ AddrTable[PROCID_TO_IPU(procId)][i].refCount = 0u;
+ }
+ Memory_copy((Ptr)(object->params.memEntries),
+ AddrTable[PROCID_TO_IPU(procId)],
+ (procId == VAYUIPUCORE0PROC_state.ipu1ProcId ?
+ sizeof(AddrTable_IPU1) : sizeof(AddrTable_IPU2)));
+
/* Set the handle in the state object. */
VAYUIPUCORE0PROC_state.procHandles [procId] =
(VAYUIPUCORE0PROC_Handle) object;
params->procArch = Processor_ProcArch_M4;
/* check for instance params override */
- Cfg_propBool(PARAMS_mmuEnable, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
+ if (VAYUIPUCORE0PROC_state.ipu1ProcId == procHandle->procId) {
+ Cfg_propBool(PARAMS_mmuEnable1, ProcMgr_sysLinkCfgParams,
+ &(object->params.mmuEnable));
+ }
+ else {
+ Cfg_propBool(PARAMS_mmuEnable2, ProcMgr_sysLinkCfgParams,
+ &(object->params.mmuEnable));
+ }
/* check for carveout params override */
for (i = 0; i < ProcMgr_MAX_MEMORY_REGIONS; i++) {
- snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutAddr"%d", i);
+ if (VAYUIPUCORE0PROC_state.ipu1ProcId == procHandle->procId) {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutAddr1"%d", i);
+ }
+ else {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutAddr2"%d", i);
+ }
strcat(prop, "=");
if (!Cfg_prop(prop, ProcMgr_sysLinkCfgParams, configProp))
break;
object->params.carveoutAddr[i] = strtoul(configProp, 0, 16);
- snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutSize"%d", i);
+ if (VAYUIPUCORE0PROC_state.ipu1ProcId == procHandle->procId) {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutSize1"%d", i);
+ }
+ else {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutSize2"%d", i);
+ }
strcat(prop, "=");
if (!Cfg_prop(prop, ProcMgr_sysLinkCfgParams, configProp))
break;
if (entry->map == FALSE) {
/* update table with entries which don't require mapping */
- if (AddrTable_count != AddrTable_SIZE) {
- me = &AddrTable[AddrTable_count];
+ if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
+ AddrTable_SIZE) {
+ me = &AddrTable[PROCID_TO_IPU(procHandle->procId)][
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]];
me->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
me->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
me->isCached = entry->isCached;
me->mapMask = entry->mapMask;
- AddrTable_count++;
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
}
else {
status = PROCESSOR_E_FAIL;
}
/* delete all dynamically added entries */
- for (i = AddrTable_STATIC_COUNT; i < AddrTable_count; i++) {
- ai = &AddrTable[i];
+ for (i = AddrTable_STATIC_COUNT; i <
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]; i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][i];
ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterPhys] = -1u;
ai->refCount = 0u;
}
object->params.numMemEntries = AddrTable_STATIC_COUNT;
- AddrTable_count = AddrTable_STATIC_COUNT;
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)] =
+ AddrTable_STATIC_COUNT;
//No need to reset.. that will be done in STOP
/*tmpStatus = VAYUIPUCORE0_halResetCtrl(object->halObject,
*dstAddr = -1u;
/* search all entries AddrTable */
- for (i = 0; i < AddrTable_count; i++) {
- ai = &AddrTable[i];
+ for (i = 0; i < AddrTable_count[PROCID_TO_IPU(procHandle->procId)];
+ i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][i];
startAddr = ai->addr[ProcMgr_AddrType_SlaveVirt];
endAddr = startAddr + ai->size;
/* check in static entries first */
for (j = 0; j < AddrTable_STATIC_COUNT; j++) {
- ai = &AddrTable[j];
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][j];
startAddr = ai->addr[ProcMgr_AddrType_SlaveVirt];
endAddr = startAddr + ai->size;
/* if not found in static entries, check in dynamic entries */
if (!found) {
- for (j = AddrTable_STATIC_COUNT; j < AddrTable_count; j++) {
- ai = &AddrTable[j];
+ for (j = AddrTable_STATIC_COUNT;
+ j < AddrTable_count[PROCID_TO_IPU(procHandle->procId)]; j++) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][j];
if (ai->isMapped == TRUE) {
startAddr = ai->addr[ProcMgr_AddrType_SlaveVirt];
*/
if (!found) {
if (object->params.mmuEnable) {
- if (AddrTable_count != AddrTable_SIZE) {
- ai = &AddrTable[AddrTable_count];
-
+ if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
+ AddrTable_SIZE) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
+ [AddrTable_count[PROCID_TO_IPU
+ (procHandle->procId)]];
ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
ai->isCached = sglist[i].isCached;
ai->refCount++;
- AddrTable_count++;
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
}
else {
status = PROCESSOR_E_FAIL;
/* Delete dynamically added non-default entries from translation
* table only in last unmap called on that entry
*/
- for (i = AddrTable_STATIC_COUNT; i < AddrTable_count; i++) {
- ai = &AddrTable[i];
+ for (i = AddrTable_STATIC_COUNT;
+ i < AddrTable_count[PROCID_TO_IPU(procHandle->procId)]; i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][i];
if (!ai->isMapped) {
continue;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore1/VAYUIpuCore1Proc.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore1/VAYUIpuCore1Proc.c
index 4c0c2cdc424917bb016904dfc0daf22286a985f7..2433986b9ef1d9a01b91183f1ab6c5cc6950950d 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
*/
#define AddrTable_SIZE 32
+/* Number of IPUs supported */
+#define NUM_IPUS 2
+
+/* Convert procId to IPU # */
+#define PROCID_TO_IPU(procId) (procId == VAYUIPUCORE1PROC_state.ipu1ProcId ?\
+ 0 : 1)
+
#define PARAMS_MAX_NAMELENGTH 64
/* Config param for L2MMU. This is not a typo, we are using the
* same name (IPU1) because both Benelli M4 processors use the
- * same L2MMU. The docs expose IPU2 but not the IPU2 Core1 processor.
+ * same L2MMU. The docs expose IPUx but not the IPUx Core1 processor.
*/
-#define PARAMS_mmuEnable "ProcMgr.proc[IPU2].mmuEnable="
-#define PARAMS_carveoutAddr "ProcMgr.proc[IPU2].carveoutAddr"
-#define PARAMS_carveoutSize "ProcMgr.proc[IPU2].carveoutSize"
+#define PARAMS_mmuEnable1 "ProcMgr.proc[IPU1].mmuEnable="
+#define PARAMS_carveoutAddr1 "ProcMgr.proc[IPU1].carveoutAddr"
+#define PARAMS_carveoutSize1 "ProcMgr.proc[IPU1].carveoutSize"
+#define PARAMS_mmuEnable2 "ProcMgr.proc[IPU2].mmuEnable="
+#define PARAMS_carveoutAddr2 "ProcMgr.proc[IPU2].carveoutAddr"
+#define PARAMS_carveoutSize2 "ProcMgr.proc[IPU2].carveoutSize"
/*!
/*!< Processor handle array. */
IGateProvider_Handle gateHandle;
/*!< Handle of gate to be used for local thread safety */
+ UInt16 ipu1ProcId;
+ /*!< MultiProc id of IPU1 (to avoid multiple lookups) */
} VAYUIPUCORE1PROC_ModuleObject;
-/* Default memory regions */
-static UInt32 AddrTable_count = AddrTable_STATIC_COUNT;
+/* Memory region counters */
+static UInt32 AddrTable_count[NUM_IPUS] = {
+ AddrTable_STATIC_COUNT,
+ AddrTable_STATIC_COUNT,
+};
/* static memory regions
* CAUTION: AddrTable_STATIC_COUNT must match number of entries below.
*/
-static ProcMgr_AddrInfo AddrTable[AddrTable_SIZE] =
+static ProcMgr_AddrInfo AddrTable_IPU1[AddrTable_SIZE] =
+{
+ /* L2 RAM */
{
- /* L2 RAM */
- {
- .addr[ProcMgr_AddrType_MasterKnlVirt] = -1u,
- .addr[ProcMgr_AddrType_MasterUsrVirt] = -1u,
- .addr[ProcMgr_AddrType_MasterPhys] = 0x55020000u,
- .addr[ProcMgr_AddrType_SlaveVirt] = 0x20000000u,
- .addr[ProcMgr_AddrType_SlavePhys] = -1u,
- .size = 0x10000u,
- .isCached = FALSE,
- .mapMask = ProcMgr_SLAVEVIRT,
- .isMapped = TRUE, /* Internal memory is always 'mapped' on the slave */
- .refCount = 0u /* refCount set to 0 for static entry */
- },
- };
+ .addr[ProcMgr_AddrType_MasterKnlVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterUsrVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterPhys] = 0x55020000u,
+ .addr[ProcMgr_AddrType_SlaveVirt] = 0x20000000u,
+ .addr[ProcMgr_AddrType_SlavePhys] = -1u,
+ .size = 0x10000u,
+ .isCached = FALSE,
+ .mapMask = ProcMgr_SLAVEVIRT,
+ .isMapped = TRUE,
+ .refCount = 0u /* refCount set to 0 for static entry */
+ },
+};
+
+static ProcMgr_AddrInfo AddrTable_IPU2[AddrTable_SIZE] =
+{
+ /* L2 RAM */
+ {
+ .addr[ProcMgr_AddrType_MasterKnlVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterUsrVirt] = -1u,
+ .addr[ProcMgr_AddrType_MasterPhys] = 0x55020000u,
+ .addr[ProcMgr_AddrType_SlaveVirt] = 0x20000000u,
+ .addr[ProcMgr_AddrType_SlavePhys] = -1u,
+ .size = 0x10000u,
+ .isCached = FALSE,
+ .mapMask = ProcMgr_SLAVEVIRT,
+ .isMapped = TRUE,
+ .refCount = 0u /* refCount set to 0 for static entry */
+ },
+};
+
+static ProcMgr_AddrInfo * AddrTable[NUM_IPUS] =
+{
+ AddrTable_IPU1,
+ AddrTable_IPU2
+};
/* =============================================================================
* Globals
.configSize = sizeof (VAYUIPUCORE1PROC_Config),
.gateHandle = NULL,
.defInstParams.mmuEnable = FALSE,
- .defInstParams.numMemEntries = AddrTable_STATIC_COUNT
+ .defInstParams.numMemEntries = AddrTable_STATIC_COUNT,
};
/* config override specified in SysLinkCfg.c, defined in ProcMgr.c */
Memory_set (&VAYUIPUCORE1PROC_state.procHandles,
0,
(sizeof (VAYUIPUCORE1PROC_Handle) * MultiProc_MAXPROCESSORS));
+
+ VAYUIPUCORE1PROC_state.ipu1ProcId = MultiProc_getId("IPU1");
VAYUIPUCORE1PROC_state.isSetup = TRUE;
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
}
VAYUIPUCORE1PROC_Params * params)
{
VAYUIPUCORE1PROC_Object * procObject = (VAYUIPUCORE1PROC_Object *) handle;
- Int i = 0;
- ProcMgr_AddrInfo * ai = NULL;
GT_2trace(curTrace, GT_ENTER, "VAYUIPUCORE1PROC_Params_init",
handle, params);
#endif
if (handle == NULL) {
- /* check for instance params override */
- Cfg_propBool(PARAMS_mmuEnable, ProcMgr_sysLinkCfgParams,
- &(VAYUIPUCORE1PROC_state.defInstParams.mmuEnable));
-
Memory_copy(params, &(VAYUIPUCORE1PROC_state.defInstParams),
sizeof(VAYUIPUCORE1PROC_Params));
- /* initialize the translation table */
- for (i = AddrTable_count; i < AddrTable_SIZE; i++) {
- ai = &AddrTable[i];
- ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterPhys] = -1u;
- ai->addr[ProcMgr_AddrType_SlaveVirt] = -1u;
- ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
- ai->size = 0u;
- ai->isCached = FALSE;
- ai->mapMask = 0u;
- ai->isMapped = FALSE;
- }
-
- /* initialize refCount for all entries - both static and dynamic */
- for (i = 0; i < AddrTable_SIZE; i++) {
- AddrTable[i].refCount = 0u;
- }
- Memory_copy((Ptr)params->memEntries, AddrTable, sizeof(AddrTable));
}
else {
/* return updated VAYUIPUCORE1PROC instance specific parameters */
Int status = PROCESSOR_SUCCESS;
Processor_Object * handle = NULL;
VAYUIPUCORE1PROC_Object * object = NULL;
+ Int i = 0;
+ ProcMgr_AddrInfo *ai = NULL;
IArg key;
List_Params listParams;
else {
handle->procId = procId;
object = (VAYUIPUCORE1PROC_Object *) handle->object;
+ object->procHandle = (Processor_Handle)handle;
object->halObject = NULL;
/* Copy params into instance object. */
Memory_copy (&(object->params),
(Ptr) params,
sizeof (VAYUIPUCORE1PROC_Params));
+ /* initialize the translation table */
+ for (i = AddrTable_count[PROCID_TO_IPU(procId)];
+ i < AddrTable_SIZE; i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procId)][i];
+ ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterPhys] = -1u;
+ ai->addr[ProcMgr_AddrType_SlaveVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
+ ai->size = 0u;
+ ai->isCached = FALSE;
+ ai->mapMask = 0u;
+ ai->isMapped = FALSE;
+ }
+
+ /*
+ * initialize refCount for all entries
+ * both static and dynamic
+ */
+ for (i = 0; i < AddrTable_SIZE; i++) {
+ AddrTable[PROCID_TO_IPU(procId)][i].refCount = 0u;
+ }
+ Memory_copy((Ptr)(object->params.memEntries),
+ AddrTable[PROCID_TO_IPU(procId)],
+ (procId == VAYUIPUCORE1PROC_state.ipu1ProcId ?
+ sizeof(AddrTable_IPU1) : sizeof(AddrTable_IPU2)));
+
/* Set the handle in the state object. */
VAYUIPUCORE1PROC_state.procHandles [procId] =
(VAYUIPUCORE1PROC_Handle) handle;
Char configProp[PARAMS_MAX_NAMELENGTH];
UInt32 numCarveouts = 0;
VAYUIPU_HalMmuCtrlArgs_Enable mmuEnableArgs;
+ VAYUIPU_HalParams halParams;
GT_2trace(curTrace, GT_ENTER,
"VAYUIPUCORE1PROC_attach", handle, params);
params->procArch = Processor_ProcArch_M4;
/* check for instance params override */
- Cfg_propBool(PARAMS_mmuEnable, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
+ if (VAYUIPUCORE1PROC_state.ipu1ProcId == procHandle->procId) {
+ Cfg_propBool(PARAMS_mmuEnable1, ProcMgr_sysLinkCfgParams,
+ &(object->params.mmuEnable));
+ }
+ else {
+ Cfg_propBool(PARAMS_mmuEnable2, ProcMgr_sysLinkCfgParams,
+ &(object->params.mmuEnable));
+ }
/* check for carveout params override */
for (i = 0; i < ProcMgr_MAX_MEMORY_REGIONS; i++) {
- snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutAddr"%d", i);
+ if (VAYUIPUCORE1PROC_state.ipu1ProcId == procHandle->procId) {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutAddr1"%d", i);
+ }
+ else {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutAddr2"%d", i);
+ }
strcat(prop, "=");
if (!Cfg_prop(prop, ProcMgr_sysLinkCfgParams, configProp))
break;
object->params.carveoutAddr[i] = strtoul(configProp, 0, 16);
- snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutSize"%d", i);
+ if (VAYUIPUCORE1PROC_state.ipu1ProcId == procHandle->procId) {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutSize1"%d", i);
+ }
+ else {
+ snprintf (prop, PARAMS_MAX_NAMELENGTH, PARAMS_carveoutSize2"%d", i);
+ }
strcat(prop, "=");
if (!Cfg_prop(prop, ProcMgr_sysLinkCfgParams, configProp))
break;
if (entry->map == FALSE) {
/* update table with entries which don't require mapping */
- if (AddrTable_count != AddrTable_SIZE) {
- me = &AddrTable[AddrTable_count];
+ if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
+ AddrTable_SIZE) {
+ me = &AddrTable[PROCID_TO_IPU(procHandle->procId)][
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]];
me->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
me->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
me->isCached = entry->isCached;
me->mapMask = entry->mapMask;
- AddrTable_count++;
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
}
else {
status = PROCESSOR_E_FAIL;
memcpy((Ptr)params->memEntries, (Ptr)object->params.memEntries,
sizeof(ProcMgr_AddrInfo) * params->numMemEntries);
- status = VAYUIPU_halInit (&(object->halObject), NULL);
+ halParams.procId = procHandle->procId;
+ status = VAYUIPU_halInit(&(object->halObject), &halParams);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS)
if (status < 0) {
}
/* delete all dynamically added entries */
- for (i = AddrTable_STATIC_COUNT; i < AddrTable_count; i++) {
- ai = &AddrTable[i];
+ for (i = AddrTable_STATIC_COUNT; i <
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]; i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][i];
ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterPhys] = -1u;
ai->refCount = 0u;
}
object->params.numMemEntries = AddrTable_STATIC_COUNT;
- AddrTable_count = AddrTable_STATIC_COUNT;
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)] =
+ AddrTable_STATIC_COUNT;
//No need to reset.. that will be done in STOP
/*tmpStatus = VAYUIPUCORE1_halResetCtrl(object->halObject,
*dstAddr = -1u;
/* search all entries AddrTable */
- for (i = 0; i < AddrTable_count; i++) {
- ai = &AddrTable[i];
+ for (i = 0; i < AddrTable_count[PROCID_TO_IPU(procHandle->procId)];
+ i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][i];
startAddr = ai->addr[ProcMgr_AddrType_SlaveVirt];
endAddr = startAddr + ai->size;
/* check in static entries first */
for (j = 0; j < AddrTable_STATIC_COUNT; j++) {
- ai = &AddrTable[j];
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][j];
startAddr = ai->addr[ProcMgr_AddrType_SlaveVirt];
endAddr = startAddr + ai->size;
*/
if (!found) {
if (object->params.mmuEnable) {
- if (AddrTable_count != AddrTable_SIZE) {
- ai = &AddrTable[AddrTable_count];
-
+ if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
+ AddrTable_SIZE) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
+ [AddrTable_count[PROCID_TO_IPU
+ (procHandle->procId)]];
ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
ai->isCached = sglist[i].isCached;
ai->refCount++;
- AddrTable_count++;
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
}
else {
status = PROCESSOR_E_FAIL;
/* Delete dynamically added non-default entries from translation
* table only in last unmap called on that entry
*/
- for (i = AddrTable_STATIC_COUNT; i < AddrTable_count; i++) {
- ai = &AddrTable[i];
+ for (i = AddrTable_STATIC_COUNT;
+ i < AddrTable_count[PROCID_TO_IPU(procHandle->procId)]; i++) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)][i];
if (!ai->isMapped) {
continue;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/Platform.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/Platform.c
index 187b4606e81d5282bc74b921bfb379ebfaf9dc09..ed5423325a73b81b571777338b29c436f8f4bec8 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
/*!< Handle to the PwrMgr instance used */
ElfLoader_Handle ldrHandle;
/*!< Handle to the Loader instance used */
- } ipu1;
+ } ipu;
} sHandles;
/*!< Slave specific handles */
} Platform_Object, *Platform_Handle;
String Syslink_Override_Params = "ProcMgr.proc[DSP1].mmuEnable=TRUE;"
"ProcMgr.proc[DSP1].carveoutAddr0=0xBA300000;"
"ProcMgr.proc[DSP1].carveoutSize0=0x5A00000;"
+ "ProcMgr.proc[IPU1].mmuEnable=TRUE;"
+ "ProcMgr.proc[IPU1].carveoutAddr0=0xBA300000;"
+ "ProcMgr.proc[IPU1].carveoutSize0=0x5A00000;"
"ProcMgr.proc[IPU2].mmuEnable=TRUE;"
"ProcMgr.proc[IPU2].carveoutAddr0=0xBA300000;"
"ProcMgr.proc[IPU2].carveoutSize0=0x5A00000;";
/* Override the MESSAGEQCOPY default config */
config->MQCopyConfig.intId[1] = 173; // 141 + 32
+ config->MQCopyConfig.intId[2] = 168; // 136 + 32
config->MQCopyConfig.intId[4] = 168; // 136 + 32
#if !defined(SYSLINK_BUILD_OPTIMIZE)
typedef union _Platform_setup_Local {
ProcMgr_Params params;
VAYUDSPPROC_Config dspProcConfig;
- VAYUIPUCORE1PROC_Config videoProcConfig;
- VAYUIPUCORE0PROC_Config vpssProcConfig;
+ VAYUIPUCORE0PROC_Config ipuProcConfig;
VAYUDSPPWR_Config dspPwrConfig;
- VAYUIPUPWR_Config videoPwrConfig;
- VAYUIPUPWR_Config vpssPwrConfig;
+ VAYUIPUPWR_Config ipuPwrConfig;
VAYUDSPPROC_Params dspProcParams;
- VAYUIPUCORE1PROC_Params videoProcParams;
- VAYUIPUCORE0PROC_Params vpssProcParams;
+ VAYUIPUCORE0PROC_Params ipuProcParams;
VAYUDSPPWR_Params dspPwrParams;
- VAYUIPUPWR_Params videoPwrParams;
- VAYUIPUPWR_Params vpssPwrParams;
+ VAYUIPUPWR_Params ipuPwrParams;
ElfLoader_Params elfLoaderParams;
} _Platform_setup_Local;
}
if (status >= 0) {
/* Get MultiProc ID by name. */
- procId = MultiProc_getId ("IPU2");
+ procId = MultiProc_getId ("IPU1");
handle = &Platform_objects [procId];
- VAYUIPUCORE0PROC_getConfig (&lv->vpssProcConfig);
- status = VAYUIPUCORE0PROC_setup (&lv->vpssProcConfig);
+ VAYUIPUCORE0PROC_getConfig (&lv->ipuProcConfig);
+ status = VAYUIPUCORE0PROC_setup (&lv->ipuProcConfig);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUIPUCORE0PROC_setup failed!");
}
else {
- VAYUIPUPWR_getConfig (&lv->vpssPwrConfig);
- status = VAYUIPUPWR_setup (&lv->vpssPwrConfig);
+ VAYUIPUPWR_getConfig (&lv->ipuPwrConfig);
+ status = VAYUIPUPWR_setup (&lv->ipuPwrConfig);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
if (status >= 0) {
/* Create an instance of the Processor object for
* VAYUIPUCORE0 */
- VAYUIPUCORE0PROC_Params_init (NULL, &lv->vpssProcParams);
- handle->sHandles.ipu1.pHandle = VAYUIPUCORE0PROC_create (procId,
- &lv->vpssProcParams);
+ VAYUIPUCORE0PROC_Params_init (NULL, &lv->ipuProcParams);
+ handle->sHandles.ipu.pHandle = VAYUIPUCORE0PROC_create (procId,
+ &lv->ipuProcParams);
+
+ /* Create an instance of the ELF Loader object */
+ ElfLoader_Params_init (NULL, &lv->elfLoaderParams);
+ handle->sHandles.ipu.ldrHandle = ElfLoader_create (procId,
+ &lv->elfLoaderParams);
+
+ /* Create an instance of the PwrMgr object for VAYUIPUCORE0 */
+ VAYUIPUPWR_Params_init (&lv->ipuPwrParams);
+ handle->sHandles.ipu.pwrHandle = VAYUIPUPWR_create (
+ procId,
+ &lv->ipuPwrParams);
+
+ if (handle->sHandles.ipu.pHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "VAYUIPUCORE0PROC_create failed!");
+ }
+ else if (handle->sHandles.ipu.ldrHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "Failed to create loader instance!");
+ }
+ else if (handle->sHandles.ipu.pwrHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "VAYUIPUPWR_create failed!");
+ }
+ else {
+ /* Initialize parameters */
+ ProcMgr_Params_init (NULL, &lv->params);
+ lv->params.procHandle = handle->sHandles.ipu.pHandle;
+ lv->params.loaderHandle = handle->sHandles.ipu.ldrHandle;
+ lv->params.pwrHandle = handle->sHandles.ipu.pwrHandle;
+ handle->pmHandle = ProcMgr_create (procId, &lv->params);
+ if (handle->pmHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "ProcMgr_create failed!");
+ }
+ }
+ }
+ }
+
+ if (status >= 0) {
+ /* Get MultiProc ID by name. */
+ procId = MultiProc_getId ("IPU2");
+
+ handle = &Platform_objects [procId];
+
+ if (status >= 0) {
+ /* Create an instance of the Processor object for
+ * VAYUIPUCORE0 */
+ VAYUIPUCORE0PROC_Params_init (NULL, &lv->ipuProcParams);
+ handle->sHandles.ipu.pHandle = VAYUIPUCORE0PROC_create (procId,
+ &lv->ipuProcParams);
/* Create an instance of the ELF Loader object */
ElfLoader_Params_init (NULL, &lv->elfLoaderParams);
- handle->sHandles.ipu1.ldrHandle = ElfLoader_create (procId,
+ handle->sHandles.ipu.ldrHandle = ElfLoader_create (procId,
&lv->elfLoaderParams);
/* Create an instance of the PwrMgr object for VAYUIPUCORE0 */
- VAYUIPUPWR_Params_init (&lv->vpssPwrParams);
- handle->sHandles.ipu1.pwrHandle = VAYUIPUPWR_create (
+ VAYUIPUPWR_Params_init (&lv->ipuPwrParams);
+ handle->sHandles.ipu.pwrHandle = VAYUIPUPWR_create (
procId,
- &lv->vpssPwrParams);
+ &lv->ipuPwrParams);
- if (handle->sHandles.ipu1.pHandle == NULL) {
+ if (handle->sHandles.ipu.pHandle == NULL) {
status = Platform_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
status,
"VAYUIPUCORE0PROC_create failed!");
}
- else if (handle->sHandles.ipu1.ldrHandle == NULL) {
+ else if (handle->sHandles.ipu.ldrHandle == NULL) {
status = Platform_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
status,
"Failed to create loader instance!");
}
- else if (handle->sHandles.ipu1.pwrHandle == NULL) {
+ else if (handle->sHandles.ipu.pwrHandle == NULL) {
status = Platform_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
else {
/* Initialize parameters */
ProcMgr_Params_init (NULL, &lv->params);
- lv->params.procHandle = handle->sHandles.ipu1.pHandle;
- lv->params.loaderHandle = handle->sHandles.ipu1.ldrHandle;
- lv->params.pwrHandle = handle->sHandles.ipu1.pwrHandle;
+ lv->params.procHandle = handle->sHandles.ipu.pHandle;
+ lv->params.loaderHandle = handle->sHandles.ipu.ldrHandle;
+ lv->params.pwrHandle = handle->sHandles.ipu.pwrHandle;
handle->pmHandle = ProcMgr_create (procId, &lv->params);
if (handle->pmHandle == NULL) {
status = Platform_E_FAIL;
}
/* ------------------------- IPU1 cleanup ------------------------------- */
+ handle = &Platform_objects [MultiProc_getId ("IPU1")];
+ if (handle->pmHandle != NULL) {
+ tmpStatus = ProcMgr_delete (&handle->pmHandle);
+ GT_assert (curTrace, (tmpStatus >= 0));
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "ProcMgr_delete failed!");
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+ }
+
+ /* Delete the Processor, Loader and PwrMgr instances */
+ if (handle->sHandles.ipu.pwrHandle != NULL) {
+ tmpStatus = VAYUIPUPWR_delete (&handle->sHandles.ipu.pwrHandle);
+ GT_assert (curTrace, (tmpStatus >= 0));
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "VAYUIPUPWR_delete failed!");
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+ }
+
+ if (handle->sHandles.ipu.ldrHandle != NULL) {
+ tmpStatus = ElfLoader_delete (&handle->sHandles.ipu.ldrHandle);
+ GT_assert (curTrace, (tmpStatus >= 0));
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "Failed to delete loader instance!");
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+ }
+
+ if (handle->sHandles.ipu.pHandle != NULL) {
+ tmpStatus = VAYUIPUCORE0PROC_delete (&handle->sHandles.ipu.pHandle);
+ GT_assert (curTrace, (tmpStatus >= 0));
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "VAYUIPUCORE0PROC_delete failed!");
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+ }
+
+ /* ------------------------- IPU2 cleanup ------------------------------- */
handle = &Platform_objects [MultiProc_getId ("IPU2")];
if (handle->pmHandle != NULL) {
tmpStatus = ProcMgr_delete (&handle->pmHandle);
}
/* Delete the Processor, Loader and PwrMgr instances */
- if (handle->sHandles.ipu1.pwrHandle != NULL) {
- tmpStatus = VAYUIPUPWR_delete (&handle->sHandles.ipu1.pwrHandle);
+ if (handle->sHandles.ipu.pwrHandle != NULL) {
+ tmpStatus = VAYUIPUPWR_delete (&handle->sHandles.ipu.pwrHandle);
GT_assert (curTrace, (tmpStatus >= 0));
if ((status >= 0) && (tmpStatus < 0)) {
status = tmpStatus;
}
}
- if (handle->sHandles.ipu1.ldrHandle != NULL) {
- tmpStatus = ElfLoader_delete (&handle->sHandles.ipu1.ldrHandle);
+ if (handle->sHandles.ipu.ldrHandle != NULL) {
+ tmpStatus = ElfLoader_delete (&handle->sHandles.ipu.ldrHandle);
GT_assert (curTrace, (tmpStatus >= 0));
if ((status >= 0) && (tmpStatus < 0)) {
status = tmpStatus;
}
}
- if (handle->sHandles.ipu1.pHandle != NULL) {
- tmpStatus = VAYUIPUCORE0PROC_delete (&handle->sHandles.ipu1.pHandle);
+ if (handle->sHandles.ipu.pHandle != NULL) {
+ tmpStatus = VAYUIPUCORE0PROC_delete (&handle->sHandles.ipu.pHandle);
GT_assert (curTrace, (tmpStatus >= 0));
if ((status >= 0) && (tmpStatus < 0)) {
status = tmpStatus;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayuipu/VAYUIpuHalMmu.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayuipu/VAYUIpuHalMmu.c
index 9f4b9b4534c798631da6ccfd425ee3eb81782ed9..7e6ec701b9fcbf8dd9a5c488f3c6147d9b33ac60 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
#include <ti/syslink/utils/Trace.h>
#include <ti/syslink/utils/OsalPrint.h>
#include <ti/syslink/utils/Memory.h>
+#include <ti/ipc/MultiProc.h>
#include <Bitops.h>
/* Module level headers */
#define MPU_INT_OFFSET 32
+/*!
+ * @brief Interrupt Id for IPU1 MMU faults
+ */
+#define MMU_FAULT_INTERRUPT_IPU1 100
+#define MMU_XBAR_INTERRUPT_IPU1 395
+
/*!
* @brief Interrupt Id for IPU2 MMU faults
*/
ProcMgr_AddrInfo * memTable)
{
Int status = PROCESSOR_SUCCESS;
- VAYUIPU_HalMmuObject * mmuObj;
+ VAYUIPU_HalMmuObject * mmuObj;
OsalIsr_Params isrParams;
- UInt32 reg = 0;
+ UInt32 reg = 0;
+ UInt16 ipu1ProcId = MultiProc_getId("IPU1");
GT_3trace (curTrace, GT_ENTER, "_VAYUIPU_halMmuEnable",
halObject, numMemEntries, memTable);
REG32(halObject->ctrlModBase + CTRL_MODULE_MMR_OFFSET) = 0xF757FDC0;
/* Program the IntXbar */
- reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU2));
- if ((MMU_FAULT_INTERRUPT_IPU2 - CTRL_MODULE_INT_BASE) % 2) {
- REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU2)) =
- (reg & 0x0000FFFF) | (MMU_XBAR_INTERRUPT_IPU2 << 16);
+ if (halObject->procId == ipu1ProcId) {
+ reg = REG32(halObject->ctrlModBase +
+ CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU1));
+ if ((MMU_FAULT_INTERRUPT_IPU1 - CTRL_MODULE_INT_BASE) % 2) {
+ REG32(halObject->ctrlModBase +
+ CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU1)) =
+ (reg & 0x0000FFFF) | (MMU_XBAR_INTERRUPT_IPU1 << 16);
+ }
+ else {
+ REG32(halObject->ctrlModBase +
+ CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU1)) =
+ (reg & 0xFFFF0000) | (MMU_XBAR_INTERRUPT_IPU1);
+ }
}
else {
- REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU2)) =
- (reg & 0xFFFF0000) | (MMU_XBAR_INTERRUPT_IPU2);
+ reg = REG32(halObject->ctrlModBase +
+ CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU2));
+ if ((MMU_FAULT_INTERRUPT_IPU2 - CTRL_MODULE_INT_BASE) % 2) {
+ REG32(halObject->ctrlModBase +
+ CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU2)) =
+ (reg & 0x0000FFFF) | (MMU_XBAR_INTERRUPT_IPU2 << 16);
+ }
+ else {
+ REG32(halObject->ctrlModBase +
+ CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTERRUPT_IPU2)) =
+ (reg & 0xFFFF0000) | (MMU_XBAR_INTERRUPT_IPU2);
+ }
}
/* Create the ISR to listen for MMU Faults */
isrParams.sharedInt = FALSE;
isrParams.checkAndClearFxn = &_VAYUIPU_halMmuCheckAndClearFunc;
isrParams.fxnArgs = halObject;
- isrParams.intId = MMU_FAULT_INTERRUPT_IPU2 + MPU_INT_OFFSET;
+ isrParams.intId = (ipu1ProcId == halObject->procId ?
+ MMU_FAULT_INTERRUPT_IPU1 + MPU_INT_OFFSET : MMU_FAULT_INTERRUPT_IPU2 +
+ MPU_INT_OFFSET);
mmuObj->isrHandle = OsalIsr_create (&_VAYUIPU_halMmuInt_isr,
halObject,
&isrParams);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuPhyShmem.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuPhyShmem.h
index 893ff85086160f9989a3ec0708283d43bcdb1f95..1eb8f2f7310e758b187fdfccc463a513dbf85abb 100644 (file)
/*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* =============================================================================
*/
/*!
- * @brief Base addresses of PRCM module.
- */
-#define PRCM_BASE_ADDR 0x4AE06700
-/*!
- * @brief Base addresses of different peripherals.
+ * @brief Base addresses and size of PRCM module.
*/
+#define IPU1_PRCM_BASE_ADDR 0x4AE06300
+#define IPU2_PRCM_BASE_ADDR 0x4AE06700
#define PRCM_SIZE 0x00002000
/*!
- * @brief Base addresses of PRCM module.
- */
-#define CM_BASE_ADDR 0x4A008700
-/*!
- * @brief Base addresses of different peripherals.
+ * @brief Base addresses and size of control module.
*/
+#define IPU1_CM_BASE_ADDR 0x4A005300
+#define IPU2_CM_BASE_ADDR 0x4A008700
#define CM_SIZE 0x00002000
-#define MMU_BASE 0x55082000
/*!
- * @brief size to be ioremapped.
+ * @brief Base addresses and size of MMU registers.
*/
+#define IPU1_MMU_BASE 0x58882000
+#define IPU2_MMU_BASE 0x55082000
+
#define MMU_SIZE 0x1000
/*!
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuPwr.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuPwr.h
index 3216bb70ceb2215d4a026a1036ab3d6c8db60216..518b9ff35b19943bffa3a28b69accceb78a546c1 100644 (file)
/*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
UInt32 prcmVA;
/*!< Virtual address for prcm module */
UInt32 ipuMmuVA;
- /*!< Virtual address for prcm module */
+ /*!< Virtual address for mmu module */
UInt32 ipubaseVA;
- /*!< Virtual address for prcm module */
+ /*!< Virtual address for control module */
ClockOps_Handle clockHandle;
/*!< Pointer to the Clock object. */
diff --git a/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c b/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c
index 1b5e66e2f12a762e0f27a2440856523f7b5fd7dd..791428d95a3593d1ddcd80f4598018f34ebbac88 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* @def VAYU_VAYU_NUMPROCS
* @brief Number of processors supported on this platform
*/
-#define VAYU_NUMPROCS 9
+#define VAYU_NUMPROCS 5
/*!
- * @def VAYU_VAYU_INDEX_DSP
- * @brief Dsp index.
+ * @def VAYU_INDEX_DSP1
+ * @brief Dsp1 index.
*/
-#define VAYU_INDEX_DSP1 6
+#define VAYU_INDEX_DSP1 4
/*!
- * @def VAYU_INDEX_VIDEOM4
- * @brief M4Video index.
+ * @def VAYU_INDEX_DSP2
+ * @brief Dsp2 index.
*/
-#define VAYU_INDEX_VIDEOM4 1
+#define VAYU_INDEX_DSP2 3
+/*!
+ * @def VAYU_INDEX_IPU1
+ * @brief IPU1 index.
+ */
+#define VAYU_INDEX_IPU1 2
/*!
* @def VAYU_INDEX_IPU2
- * @brief M4Dss index.
+ * @brief IPU2 index.
*/
#define VAYU_INDEX_IPU2 1
/*!
*/
#define VAYU_INDEX_HOST 0
+/*!
+ * @def VAYU_HOST_IPU1_MBOX
+ * @brief Mailbox used for HOST<->IPU1 communication.
+ */
+#define VAYU_HOST_IPU1_MBOX 5
+
/*!
* @def VAYU_HOST_IPU2_MBOX
* @brief Mailbox used for HOST<->IPU2 communication.
*/
#define VAYU_HOST_IPU2_MBOX 6
+/*!
+ * @def IPU1_HOST_SUB_MBOX
+ * @brief Sub-Mailbox used for IPU1->HOST communication.
+ */
+#define IPU1_HOST_SUB_MBOX 4
+
+/*!
+ * @def HOST_IPU1_SUB_MBOX
+ * @brief Sub-Mailbox used for HOST->IPU1 communication.
+ */
+#define HOST_IPU1_SUB_MBOX 6
+
/*!
* @def IPU2_HOST_SUB_MBOX
- * @brief Sub-Mailbox used for HOST->IPU2 communication.
+ * @brief Sub-Mailbox used for IPU2->HOST communication.
*/
#define IPU2_HOST_SUB_MBOX 4
/*!
* @def HOST_IPU2_SUB_MBOX
- * @brief Sub-Mailbox used for IPU2->HOST communication.
+ * @brief Sub-Mailbox used for HOST->IPU2 communication.
*/
#define HOST_IPU2_SUB_MBOX 6
*/
#define VAYU_HOST_USER_ID 2
+/*!
+ * @def VAYU_IPU1_USER_ID
+ * @brief User ID of IPU2.
+ */
+#define VAYU_IPU1_USER_ID 1
+
/*!
* @def VAYU_IPU2_USER_ID
* @brief User ID of IPU2.
*/
#define IRQ_XBAR_DSP1 IRQ_XBAR_MBOX_5_USR_2
+/*!
+ * @def IRQ_XBAR_IPU1
+ * @brief irq xbar num for ipu1.
+ */
+#define IRQ_XBAR_IPU1 IRQ_XBAR_MBOX_5_USR_2
+
/*!
* @def IRQ_XBAR_IPU2
* @brief irq xbar num for ipu2.
VAYUIpcInt_clearInterrupt,
};
-int mailbox_5_context[MAILBOX_SIZE];
+int mailbox_5_context_ipu1[MAILBOX_SIZE];
+int mailbox_5_context_ipu2[MAILBOX_SIZE];
int mailbox_6_context[MAILBOX_SIZE];
/* =============================================================================
*/
VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1] =
MultiProc_getId ("DSP1");
+ VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1] =
+ MultiProc_getId ("IPU1");
VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2] =
MultiProc_getId ("IPU2");
VAYUIpcInt_state.maxProcessors = MultiProc_getNumProcessors();
unmapInfo.size = CTRL_MODULE_SIZE;
unmapInfo.isCached = FALSE;
Memory_unmap (&unmapInfo);
- VAYUIpcInt_state.archCoreCmBase = (UInt32) NULL;
+ VAYUIpcInt_state.controlModuleBase = (UInt32) NULL;
}
GT_0trace (curTrace, GT_ENTER, "VAYUIpcInt_destroy");
if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1]) {
mboxId = IRQ_XBAR_DSP1;
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]){
+ mboxId = IRQ_XBAR_IPU1;
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]){
mboxId = IRQ_XBAR_IPU2;
}
return status;
}
-/*!
- * @brief Function to Save context.
- *
- * @param procId The procId associated with the mailbox context being
- * saved.
- *
- * @sa VAYUIpcInt_mbxRestoreCtxt
- */
-
-Int32
-VAYUIpcInt_mboxSaveCtxt (UInt16 procId)
-{
- Int32 status = VAYUIPCINT_SUCCESS;
- UInt32 i = 0;
-
- if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2] &&
- VAYUIpcInt_state.mailbox5Base == NULL) {
- status = VAYUIPCINT_E_MEMORY;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIpcInt_mboxSaveCtxt",
- status,
- "Unable to map the Mailbox memory in SaveCtxt");
- }
- else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1] &&
- VAYUIpcInt_state.mailbox6Base == NULL) {
- status = VAYUIPCINT_E_MEMORY;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIpcInt_mboxSaveCtxt",
- status,
- "Unable to map the Mailbox memory in SaveCtxt");
- }
- else {
- if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
- for (i = 0; i < 4; i++) {
- mailbox_5_context[i] = REG32(VAYUIpcInt_state.mailbox5Base + \
- VAYU_MAILBOX_IRQENABLE(i));
- }
- }
- else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1]) {
- for (i = 0; i < 4; i++) {
- mailbox_6_context[i] = REG32(VAYUIpcInt_state.mailbox6Base + \
- VAYU_MAILBOX_IRQENABLE(i));
- }
- }
- VAYUIpcInt_interruptDisable(procId, VAYUIpcInt_state.intId);
- }
- return status;
-}
-
-/*!
- * @brief Function to Restore context.
- *
- * @param procId The procId associated with the mailbox context being
- * restored.
- *
- * @sa VAYUIpcInt_mbxSaveCtxt
- */
-
-Int32
-VAYUIpcInt_mboxRestoreCtxt (UInt16 procId)
-{
- Int32 status = VAYUIPCINT_SUCCESS;
- UInt32 i = 0;
-
- if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2] &&
- VAYUIpcInt_state.mailbox5Base == NULL) {
- status = VAYUIPCINT_E_MEMORY;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIpcInt_mboxRestoreCtxt",
- status,
- "Unable to map the Mailbox memory in RestoreCtxt");
- }
- else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1] &&
- VAYUIpcInt_state.mailbox6Base == NULL) {
- status = VAYUIPCINT_E_MEMORY;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIpcInt_mboxRestoreCtxt",
- status,
- "Unable to map the Mailbox memory in RestoreCtxt");
- }
- else {
- if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
- /* Set to Smart Idle mode*/
- REG(VAYUIpcInt_state.mailbox5Base + MAILBOX_SYSCONFIG_OFFSET) = 0x8;
-
- for (i = 0; i < 4; i++) {
- REG32(VAYUIpcInt_state.mailbox5Base + \
- VAYU_MAILBOX_IRQENABLE(i)) = mailbox_5_context[i];
- }
- }
- else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1]) {
- /* Set to Smart Idle mode*/
- REG(VAYUIpcInt_state.mailbox6Base + MAILBOX_SYSCONFIG_OFFSET) = 0x8;
-
- for (i = 0; i < 4; i++) {
- REG32(VAYUIpcInt_state.mailbox6Base + \
- VAYU_MAILBOX_IRQENABLE(i)) = mailbox_6_context[i];
- }
- }
-
- VAYUIpcInt_interruptEnable(procId, VAYUIpcInt_state.intId);
- }
-
- return status;
-}
/*!
VAYU_MAILBOX_IRQENABLE(VAYU_HOST_USER_ID)),
( (DSP1_HOST_SUB_MBOX) << 1));
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
+ /*
+ * Mailbox 5 is used for HOST<->IPU1 communication
+ */
+ SET_BIT(REG(VAYUIpcInt_state.mailbox5Base + \
+ VAYU_MAILBOX_IRQENABLE(VAYU_HOST_USER_ID)),
+ ( (IPU1_HOST_SUB_MBOX) << 1));
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
/*
* Mailbox 6 is used for HOST<->IPU2 communication
MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)),
( (DSP1_HOST_SUB_MBOX) << 1));
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
+ /*
+ * Mailbox 5 is used for HOST<->IPU1 communication
+ */
+ SET_BIT(REG(VAYUIpcInt_state.mailbox5Base + \
+ MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)),
+ ( (IPU1_HOST_SUB_MBOX) << 1));
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
/*
* Mailbox 6 is used for HOST<->IPU2 communication
+ MAILBOX_MSGSTATUS_m_OFFSET(HOST_DSP1_SUB_MBOX)))
& 0x3F ));
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
+ /* Wait for M4 to clear the previous interrupt */
+ while( ( REG32((VAYUIpcInt_state.mailbox5Base
+ + MAILBOX_MSGSTATUS_m_OFFSET(HOST_IPU1_SUB_MBOX)))
+ & 0x3F ));
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
- /* Wait for VIDEOM4 to clear the previous interrupt */
+ /* Wait for M4 to clear the previous interrupt */
while( ( REG32((VAYUIpcInt_state.mailbox6Base
+ MAILBOX_MSGSTATUS_m_OFFSET(HOST_IPU2_SUB_MBOX)))
& 0x3F ));
*/
REG32(VAYUIpcInt_state.mailbox5Base + \
MAILBOX_MESSAGE_m_OFFSET(HOST_DSP1_SUB_MBOX)) = value;
- } else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
+ }
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
/*
- * Mailbox 6 is used for HOST<->DSP1 communication
+ * Mailbox 5 is used for HOST<->IPU1 communication
+ */
+ REG32(VAYUIpcInt_state.mailbox5Base + \
+ MAILBOX_MESSAGE_m_OFFSET(HOST_IPU1_SUB_MBOX)) = value;
+ }
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
+ /*
+ * Mailbox 6 is used for HOST<->IPU2 communication
*/
REG32(VAYUIpcInt_state.mailbox6Base + \
MAILBOX_MESSAGE_m_OFFSET(HOST_IPU2_SUB_MBOX)) = value;
GT_1trace (curTrace, GT_ENTER, "_VAYUIpcInt_checkAndClearFunc", arg);
- if( REG32( VAYUIpcInt_state.mailbox6Base
+ if (REG32(VAYUIpcInt_state.mailbox6Base
+ MAILBOX_MSGSTATUS_m_OFFSET(IPU2_HOST_SUB_MBOX)) != 0 ){
procId = VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2];
msg = VAYUIpcInt_clearInterrupt (procId, IPU2_HOST_SUB_MBOX);
List_put(VAYUIpcInt_state.isrLists[procId], (List_Elem *)elem);
}
}
- if( REG32( VAYUIpcInt_state.mailbox5Base
+ if (REG32(VAYUIpcInt_state.mailbox5Base
+ + MAILBOX_MSGSTATUS_m_OFFSET(IPU1_HOST_SUB_MBOX)) != 0 ){
+ procId = VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1];
+ msg = VAYUIpcInt_clearInterrupt (procId, IPU1_HOST_SUB_MBOX);
+
+ GT_1trace (curTrace, GT_1CLASS, "Got msg [0x%08x] from IPU1", msg);
+
+ /* This is a message from IPU1, put the message in IPU1's list */
+ elem = get_msg();
+ if (elem) {
+ elem->msg = msg;
+ List_put(VAYUIpcInt_state.isrLists[procId], (List_Elem *)elem);
+ }
+ }
+ if (REG32(VAYUIpcInt_state.mailbox5Base
+ MAILBOX_MSGSTATUS_m_OFFSET(DSP1_HOST_SUB_MBOX)) != 0 ){
procId = VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1];
msg = VAYUIpcInt_clearInterrupt (procId, DSP1_HOST_SUB_MBOX);