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raw | patch | inline | side by side (parent: d746e3c)
raw | patch | inline | side by side (parent: d746e3c)
| author | G Anthony <a0783926@ti.com> | |
| Mon, 22 Jul 2013 21:18:23 +0000 (14:18 -0700) | ||
| committer | Chris Ring <cring@ti.com> | |
| Fri, 26 Jul 2013 03:48:25 +0000 (20:48 -0700) |
- Resource Table: Vring physical addresses are made unique depending on VAYU
core, and need to match CMA base addresses; given both DSP and IPU
have IOMMU's, the device addresses otherwise remain the same.
- Adjust test image memory maps to fit in 6MB footprint for initial testing.
- Add support to build tests for IPU1 and DSP2 platform instances.
Signed-off-by: G Anthony <a0783926@ti.com>
[s-anna@ti.com: add dsp2 and ipu1 build targets]
Signed-off-by: Suman Anna <s-anna@ti.com>
Vayu: Tests: Adjust memory maps for IPU1 and DSP2
Retain the memory map for IPU2 while creating a newer
memory map for IPU1. Also fix some of the other sizes.
Signed-off-by: Suman Anna <s-anna@ti.com>
core, and need to match CMA base addresses; given both DSP and IPU
have IOMMU's, the device addresses otherwise remain the same.
- Adjust test image memory maps to fit in 6MB footprint for initial testing.
- Add support to build tests for IPU1 and DSP2 platform instances.
Signed-off-by: G Anthony <a0783926@ti.com>
[s-anna@ti.com: add dsp2 and ipu1 build targets]
Signed-off-by: Suman Anna <s-anna@ti.com>
Vayu: Tests: Adjust memory maps for IPU1 and DSP2
Retain the memory map for IPU2 while creating a newer
memory map for IPU1. Also fix some of the other sizes.
Signed-off-by: Suman Anna <s-anna@ti.com>
diff --git a/ipc-bios.bld b/ipc-bios.bld
index 5e3501528283f9f38a09efbed5979f42d1a93773..1a7026b5791ab33b4588dfcbc4e302a7bc8914be 100644 (file)
--- a/ipc-bios.bld
+++ b/ipc-bios.bld
case 'dra7xx':
target.platforms.$add("ti.platforms.evmDRA7XX:dsp1");
+ target.platforms.$add("ti.platforms.evmDRA7XX:dsp2");
break;
default:
case 'dra7xx':
target.platforms.$add("ti.platforms.evmDRA7XX:ipu2");
+ target.platforms.$add("ti.platforms.evmDRA7XX:ipu1");
break;
default:
diff --git a/packages/ti/configs/vayu/Dsp2.cfg b/packages/ti/configs/vayu/Dsp2.cfg
--- /dev/null
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * The SysMin is used here instead of StdMin, as trace buffer address is
+ * required for Linux trace debug driver, plus provides better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('ti.trace.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize = 0x8000;
+
+/* Define default memory heap properties */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+Memory.defaultHeapSize = 0x20000;
+
+/* Modules used in the virtqueue/MessageQCopy/ServiceMgr libraries: */
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+
+var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
+Cache.setMarMeta(0xa0000000, 0x02000000, Cache.Mar_DISABLE);
+var L1cache = new Cache.Size();
+L1cache.l1dSize = Cache.L1Size_0K;
+
+/* Reduces code size, by only pulling in modules explicitly referenced: */
+//BIOS.libType = BIOS.LibType_Custom;
+
+/* Use LibType_Debug option for now to avoid linking error due to bug in BIOS */
+BIOS.libType = BIOS.LibType_Debug;
+
+xdc.loadPackage('ti.sdo.ipc.family.vayu');
+xdc.useModule('ti.sdo.ipc.family.vayu.InterruptDsp');
+xdc.loadPackage('ti.ipc.rpmsg');
+xdc.loadPackage('ti.ipc.family.vayu');
+
+/* TBD: Not yet taken in from omapzoom:
+xdc.loadPackage('ti.srvmgr');
+xdc.useModule('ti.srvmgr.omx.OmxSrvMgr');
+xdc.loadPackage('ti.resmgr');
+*/
+
+/* Enable Memory Translation module that operates on the BIOS Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = "EXT_CODE"
+
+/* Modules used in Power Management */
+xdc.loadPackage('ti.pm');
+/*
+var Power = xdc.useModule('ti.sysbios.family.c64p.tesla.Power');
+Power.loadSegment = "PM_DATA";
+*/
+
+/* Idle function that periodically flushes the unicache */
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+Idle.addFunc('&VirtQueue_cacheWb');
+
+//TBD: Idle.addFunc('&ti_deh_Deh_idleBegin'); /* Must be placed before pwr mgmt */
+//TBD: Idle.addFunc('&IpcPower_idle'); /* IpcPower_idle must be at the end */
+
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var List = xdc.useModule('ti.sdo.utils.List');
+
+/* ti.grcm Configuration */
+/* TBD:
+var rcmSettings = xdc.useModule('ti.grcm.Settings');
+rcmSettings.ipc = rcmSettings.IpcSupport_ti_sdo_ipc;
+xdc.useModule('ti.grcm.RcmServer');
+*/
+xdc.useModule('ti.sysbios.xdcruntime.GateThreadSupport');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.common$.namedInstance = true;
+
+var Assert = xdc.useModule('xdc.runtime.Assert');
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+
+/* Enable Logger: */
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+/* Enable runtime Diags_setMask() for non-XDC spec'd modules: */
+var Text = xdc.useModule('xdc.runtime.Text');
+Text.isLoaded = true;
+var Registry = xdc.useModule('xdc.runtime.Registry');
+Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;
+Registry.common$.diags_EXIT = Diags.RUNTIME_OFF;
+Registry.common$.diags_USER1 = Diags.ALWAYS_ON;
+Registry.common$.diags_INFO = Diags.ALWAYS_ON;
+Registry.common$.diags_LIFECYCLE = Diags.ALWAYS_ON;
+Registry.common$.diags_STATUS = Diags.ALWAYS_ON;
+Diags.setMaskEnabled = true;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
+
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+//TBD: var Deh = xdc.useModule('ti.deh.Deh');
+Hwi.enableException = true;
+
+/* -------------------------------- DSP ----------------------------------*/
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+MultiProc.setConfig("DSP2", ["HOST", "IPU2", "IPU1", "DSP2", "DSP1"]);
+
+/* --------------------------- TICK --------------------------------------*/
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.tickSource = Clock.TickSource_NULL;
+//Clock.tickSource = Clock.TickSource_USER;
+/* Configure BIOS clock source as GPTimer5 */
+//Clock.timerId = 0;
+
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+
+/* Skip the Timer frequency verification check. Need to remove this later */
+Timer.checkFrequency = false;
+
+/* Match this to the SYS_CLK frequency sourcing the dmTimers.
+ * Not needed once the SYS/BIOS family settings is updated. */
+Timer.intFreq.hi = 0;
+Timer.intFreq.lo = 19200000;
+
+//var timerParams = new Timer.Params();
+//timerParams.period = Clock.tickPeriod;
+//timerParams.periodType = Timer.PeriodType_MICROSECS;
+/* Switch off Software Reset to make the below settings effective */
+//timerParams.tiocpCfg.softreset = 0x0;
+/* Smart-idle wake-up-capable mode */
+//timerParams.tiocpCfg.idlemode = 0x3;
+/* Wake-up generation for Overflow */
+//timerParams.twer.ovf_wup_ena = 0x1;
+//Timer.create(Clock.timerId, Clock.doTick, timerParams);
+
+Program.sectMap[".tracebuf"] = "TRACE_BUF";
+Program.sectMap[".errorbuf"] = "EXC_DATA";
+
+/* Version module */
+/* ???
+xdc.useModule('ti.utils.Version');
+*/
diff --git a/packages/ti/configs/vayu/Ipu1Smp.cfg b/packages/ti/configs/vayu/Ipu1Smp.cfg
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Configure BIOS for SMP-mode */
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.smpEnabled = true;
+
+/* -------------------------------- CORE0 ----------------------------------*/
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+MultiProc.setConfig("IPU1", ["HOST", "IPU2", "IPU1", "DSP2", "DSP1"]);
+
+/* We are IPU1 */
+var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.ipuId = 1;
+
+/* ----------------------------- TICK ---------------------------------------*/
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.tickSource = Clock.TickSource_USER;
+/* Configure GPTimer3 as BIOS clock source */
+Clock.timerId = 2;
+
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+var timerParams = new Timer.Params();
+timerParams.period = Clock.tickPeriod;
+timerParams.periodType = Timer.PeriodType_MICROSECS;
+/* Smart-idle wake-up-capable mode */
+timerParams.tiocpCfg.idlemode = 0x3;
+/* Wake-up generation for Overflow */
+timerParams.twer.ovf_wup_ena = 0x1;
+Timer.create(Clock.timerId, Clock.doTick, timerParams);
+
+/* Modules used in Power Management */
+xdc.loadPackage('ti.pm');
+var Power = xdc.useModule('ti.sysbios.family.arm.ducati.smp.Power');
+Power.loadSegment = "PM_DATA";
+
+/* Idle functions - PM functions should be last */
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+/* Function to flush unicache in each core */
+Idle.addCoreFunc('&VirtQueue_cacheWb', 0);
+Idle.addCoreFunc('&VirtQueue_cacheWb', 1);
+
+/* Watchdog detection functions in each core */
+/* TBD: DEH not taken from omapzoom yet:
+Idle.addCoreFunc('&ti_deh_Deh_idleBegin', 0);
+Idle.addCoreFunc('&ti_deh_Deh_idleBegin', 1);
+*/
+
+/* Idle Power Management functions for each core */
+Idle.addCoreFunc('&IpcPower_idle', 0);
+Idle.addCoreFunc('&IpcPower_idle', 1);
+
+Program.sectMap[".tracebuf"] = "TRACE_BUF";
+Program.sectMap[".errorbuf"] = "EXC_DATA";
index 8c4f805d4f40c6b3edb1535d701ae700b50bafe2..0f87a88c04bf9d9e8f39ad145cbcb3d847b40f61 100644 (file)
% }
% else if (prog.cpu.deviceName.match(/Vayu/) ||
% prog.cpu.deviceName.match(/DRA7XX/)) {
-% if (prog.cpu.attrs.cpuCore.match(/CM4/) &&
-% (xdc.om["ti.sysbios.family.arm.ducati.Core"].ipuId == 2)) {
-#define OMAP5
+% if (prog.cpu.attrs.cpuCore.match(/CM4/)) {
+% if (xdc.om["ti.sysbios.family.arm.ducati.Core"].ipuId == 1) {
+#define VAYU_IPU_1
+% //print("ti.ipc.remoteproc.Resource.xdt : VAYU_IPU_1");
+% }
+% if (xdc.om["ti.sysbios.family.arm.ducati.Core"].ipuId == 2) {
+#define VAYU_IPU_2
+% //print("ti.ipc.remoteproc.Resource.xdt : VAYU_IPU_2");
+% }
#include <ti/ipc/remoteproc/rsc_table_vayu_ipu.h>
% }
% else if (prog.cpu.attrs.cpuCore.match(/6600/)) {
-#define OMAP5
+% if (prog.platformName.match(/DRA7XX:dsp1$/)) {
+#define VAYU_DSP_1
+% //print("ti.ipc.remoteproc.Resource.xdt : VAYU_DSP_1");
+% }
+% if (prog.platformName.match(/DRA7XX:dsp2$/)) {
+#define VAYU_DSP_2
+% //print("ti.ipc.remoteproc.Resource.xdt : VAYU_DSP_2");
+% }
#include <ti/ipc/remoteproc/rsc_table_vayu_dsp.h>
% }
% else {
diff --git a/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.h b/packages/ti/ipc/remoteproc/rsc_table_vayu_dsp.h
index 84608b6040051c110b177a961e6e553ce6e6a1fc..961a9a66df16a932dabe879e1336891715422ea5 100644 (file)
/*
* Assign fixed RAM addresses to facilitate a fixed MMU table.
*/
-/* This address is derived from current IPU & ION carveouts */
+/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#ifdef OMAP5
#define PHYS_MEM_IPC_VRING 0x95000000
+#elif defined (VAYU_DSP_1)
+#define PHYS_MEM_IPC_VRING 0x95000000
+#elif defined (VAYU_DSP_2)
+#define PHYS_MEM_IPC_VRING 0x94800000
#else
#define PHYS_MEM_IPC_VRING 0x98800000
#endif
diff --git a/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.h b/packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.h
index 5054351c06376c6c8e1a42ecda27063e6ecc23d6..664d4d41d2c46477907213276a82bcecfb77ee5f 100644 (file)
#define IPU_MEM_TEXT 0x0
#define IPU_MEM_DATA 0x80000000
-#ifdef OMAP5
+#if defined(OMAP5) || defined(VAYU_IPU_1) || defined(VAYU_IPU_2)
#define IPU_MEM_IOBUFS 0x90000000
#else
#define IPU_MEM_IOBUFS 0x88000000
#define IPU_MEM_IPC_VRING_SIZE SZ_1M
#define IPU_MEM_IPC_DATA_SIZE SZ_1M
+
+#ifdef VAYU_IPU_1
+#define IPU_MEM_TEXT_SIZE (SZ_1M)
+#else
#define IPU_MEM_TEXT_SIZE (SZ_1M * 6)
-#ifdef OMAP5
+#endif
+
+#if defined(OMAP5) || defined(VAYU_IPU_2)
#define IPU_MEM_DATA_SIZE (SZ_1M * 156)
+#elif defined(VAYU_IPU_1)
+#define IPU_MEM_DATA_SIZE (SZ_1M * 5)
#else
#define IPU_MEM_DATA_SIZE (SZ_1M * 100)
#endif
+
#define IPU_MEM_IOBUFS_SIZE (SZ_1M * 90)
/*
* Assign fixed RAM addresses to facilitate a fixed MMU table.
* PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
*/
+/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#ifdef OMAP5
#define PHYS_MEM_IPC_VRING 0x95800000
+#elif defined(VAYU_IPU_1)
+#define PHYS_MEM_IPC_VRING 0x94000000
+#elif defined (VAYU_IPU_2)
+#define PHYS_MEM_IPC_VRING 0x95800000
#else
#define PHYS_MEM_IPC_VRING 0x99000000
#endif
index 707c3b0feedb66a0ae71529f664a2913b6acac65..685e3dbf174d44dfcba11358dbde68cc8f5ba311 100644 (file)
stackMemory: "EXT_DATA",
};
-/* Memory Map for ti.platforms.evmDRA7XX:dsp1
+/* Memory Map for ti.platforms.evmDRA7XX:dsp1 and ti.platforms.evmDRA7XX:dsp2
*
* --- External Memory ---
* Virtual Physical Size Comment
* ------------------------------------------------------------------------
- * 0000_4000 ????_???? 5F_C000 ( ~6 MB) EXT_CODE
- * 8000_0000 ????_???? 60_0000 ( 6 MB) EXT_DATA
- * 8060_0000 ????_???? 960_0000 ( 86 MB) EXT_HEAP
+ * 9500_4000 ????_???? 10_0000 ( ~1 MB) EXT_CODE
+ * 9510_0000 ????_???? 10_0000 ( 1 MB) EXT_DATA
+ * 9520_0000 ????_???? 30_0000 ( 3 MB) EXT_HEAP
* 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
* 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
* 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
*/
-var evmDRA7XX_ExtMemMapDsp1 = {
+var evmDRA7XX_ExtMemMapDsp = {
EXT_CODE: {
name: "EXT_CODE",
base: 0x95000000,
Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
externalMemoryMap: [
- [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp1.EXT_CODE ],
- [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp1.EXT_DATA ],
- [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp1.EXT_HEAP ],
- [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp1.TRACE_BUF ],
- [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp1.EXC_DATA ],
- [ "PM_DATA", evmDRA7XX_ExtMemMapDsp1.PM_DATA ]
+ [ "EXT_CODE", evmDRA7XX_ExtMemMapDsp.EXT_CODE ],
+ [ "EXT_DATA", evmDRA7XX_ExtMemMapDsp.EXT_DATA ],
+ [ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp.EXT_HEAP ],
+ [ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp.TRACE_BUF ],
+ [ "EXC_DATA", evmDRA7XX_ExtMemMapDsp.EXC_DATA ],
+ [ "PM_DATA", evmDRA7XX_ExtMemMapDsp.PM_DATA ]
],
codeMemory: "EXT_CODE",
dataMemory: "EXT_DATA",
stackMemory: "EXT_DATA",
};
+Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] =
+ Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];
+
/* Memory Map for ti.platforms.evmDRA7XX:ipu2
stackMemory: "EXT_DATA",
};
+/* Memory Map for ti.platforms.evmDRA7XX:ipu1
+ *
+ * --- External Memory ---
+ * Virtual Physical Size Comment
+ * ------------------------------------------------------------------------
+ * 0000_4000 ????_???? F_C000 ( ~1 MB) EXT_CODE
+ * 8000_0000 ????_???? 20_0000 ( 2 MB) EXT_DATA
+ * 8020_0000 ????_???? 30_0000 ( 3 MB) EXT_HEAP
+ * 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
+ * 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
+ * 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
+ */
+var evmDRA7XX_ExtMemMapIpu1 = {
+ EXT_CODE: {
+ name: "EXT_CODE",
+ base: 0x00004000,
+ len: 0x000FC000,
+ space: "code",
+ access: "RWX"
+ },
+ EXT_DATA: {
+ name: "EXT_DATA",
+ base: 0x80000000,
+ len: 0x00200000,
+ space: "data",
+ access: "RW"
+ },
+ EXT_HEAP: {
+ name: "EXT_HEAP",
+ base: 0x80200000,
+ len: 0x00300000,
+ space: "data",
+ access: "RW"
+ },
+ TRACE_BUF: {
+ name: "TRACE_BUF",
+ base: 0x9F000000,
+ len: 0x00060000,
+ space: "data",
+ access: "RW"
+ },
+ EXC_DATA: {
+ name: "EXC_DATA",
+ base: 0x9F060000,
+ len: 0x00010000,
+ space: "data",
+ access: "RW"
+ },
+ PM_DATA: {
+ name: "PM_DATA",
+ base: 0x9F070000,
+ len: 0x00020000,
+ space: "data",
+ access: "RWX" /* should this have execute perm? */
+ }
+};
+
+Build.platformTable["ti.platforms.evmDRA7XX:ipu1"] = {
+ externalMemoryMap: [
+ [ "EXT_CODE", evmDRA7XX_ExtMemMapIpu1.EXT_CODE ],
+ [ "EXT_DATA", evmDRA7XX_ExtMemMapIpu1.EXT_DATA ],
+ [ "EXT_HEAP", evmDRA7XX_ExtMemMapIpu1.EXT_HEAP ],
+ [ "TRACE_BUF", evmDRA7XX_ExtMemMapIpu1.TRACE_BUF ],
+ [ "EXC_DATA", evmDRA7XX_ExtMemMapIpu1.EXC_DATA ],
+ [ "PM_DATA", evmDRA7XX_ExtMemMapIpu1.PM_DATA ]
+ ],
+ codeMemory: "EXT_CODE",
+ dataMemory: "EXT_DATA",
+ stackMemory: "EXT_DATA",
+};
+
for (var i = 0; i < Build.targets.length; i++) {
var targ = Build.targets[i];
}).addObjects(test_omx_SRCS);
}
+ if (platform.match(/^ti\.platform\.vayu\.ipu1/) ||
+ platform.match(/^ti\.platforms\.evmDRA7XX:ipu1$/)) {
+ Pkg.addExecutable(name + "/test_omx_ipu1_vayu", targ, platform, {
+ cfgScript: "test_omx_ipu_vayu",
+ defs: "-D IPU -D VAYU -DRPMSG_NS_2_0"
+ }).addObjects(test_omx_SRCS);
+ }
if (platform.match(/^ti\.platform\.vayu\.ipu2/) ||
platform.match(/^ti\.platforms\.evmDRA7XX:ipu2$/)) {
Pkg.addExecutable(name + "/test_omx_ipu2_vayu", targ, platform, {
}).addObjects(test_omx_SRCS);
}
- if (platform.match(/^ti\.platform\.vayu\.dsp1/) ||
+ if (platform.match(/^ti\.platform\.vayu/) ||
platform.match(/^ti\.platforms\.evmDRA7XX:dsp1$/)) {
Pkg.addExecutable(name + "/test_omx_dsp1_vayu", targ, platform, {
cfgScript: "test_omx_dsp_vayu",
defs: "-D DSP -D VAYU -DRPMSG_NS_2_0"
}).addObjects(test_omx_SRCS);
}
+ if (platform.match(/^ti\.platform\.vayu/) ||
+ platform.match(/^ti\.platforms\.evmDRA7XX:dsp2$/)) {
+ Pkg.addExecutable(name + "/test_omx_dsp2_vayu", targ, platform, {
+ cfgScript: "test_omx_dsp_vayu",
+ defs: "-D DSP -D VAYU -DRPMSG_NS_2_0"
+ }).addObjects(test_omx_SRCS);
+ }
}
}
index cc0ccbc0df65bb3b5b45817da9e566e23f4a6ac2..473675056365a67ec5069e992d28d2650155382d 100644 (file)
xdc.includeFile("ti/configs/omap54xx/Dsp.cfg");
xdc.includeFile("ti/configs/omap54xx/DspAmmu.cfg");
}
-else if (Program.platformName.match(/^ti\.platform\.vayu\.ipu2/) ||
- (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
- Program.cpu.attrs.cpuCore.match(/^CM4$/))) {
+else if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
+ Program.cpu.attrs.cpuCore.match(/^CM4$/)) {
var Task = xdc.useModule('ti.sysbios.knl.Task');
var params = new Task.Params;
params.instance.name = "ping";
BIOS.addUserStartupFunction('&IpcMgr_rpmsgStartup');
xdc.loadCapsule("ti/configs/vayu/IpcCommon.cfg.xs");
- xdc.includeFile("ti/configs/vayu/Ipu2Smp.cfg");
+ if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX\:ipu1/)) {
+ xdc.includeFile("ti/configs/vayu/Ipu1Smp.cfg");
+ }
+ else {
+ xdc.includeFile("ti/configs/vayu/Ipu2Smp.cfg");
+ }
xdc.includeFile("ti/configs/vayu/IpuAmmu.cfg");
}
-else if (Program.platformName.match(/^ti\.platform\.vayu\.dsp1/) ||
- (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
- Program.cpu.attrs.cpuCore.match(/^6600$/))) {
+else if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
+ Program.cpu.attrs.cpuCore.match(/^6600$/)) {
var Task = xdc.useModule('ti.sysbios.knl.Task');
var params = new Task.Params;
params.instance.name = "ping";
var BIOS = xdc.useModule('ti.sysbios.BIOS');
BIOS.addUserStartupFunction('&IpcMgr_rpmsgStartup');
- xdc.includeFile("ti/configs/vayu/Dsp1.cfg");
+ if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX\:dsp1/)) {
+ xdc.includeFile("ti/configs/vayu/Dsp1.cfg");
+ }
+ else {
+ xdc.includeFile("ti/configs/vayu/Dsp2.cfg");
+ }
}
else {
xdc.loadCapsule("ping_rpmsg_common.cfg.xs");
index 6809b3282b78a51c6f75d91a973855663eba38f0..bbe2fc7f13b6c79e1c58fbfffb15d48497f1a4e7 100644 (file)
xdc.includeFile("ti/configs/omap54xx/Dsp.cfg");
xdc.includeFile("ti/configs/omap54xx/DspAmmu.cfg");
}
-else if ((Program.platformName.match(/^ti\.platform\.vayu\.ipu2/)) ||
- (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
- Program.cpu.attrs.cpuCore.match(/^CM4$/))) {
+else if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
+ Program.cpu.attrs.cpuCore.match(/^CM4$/)) {
/* This initializes the MessageQ Transport RPMSG stack: */
xdc.loadPackage('ti.ipc.ipcmgr');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
VirtioSetup.common$.diags_INFO = Diags.ALWAYS_ON;
xdc.loadCapsule("ti/configs/vayu/IpcCommon.cfg.xs");
- xdc.includeFile("ti/configs/vayu/Ipu2Smp.cfg");
+ if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX\:ipu1/)) {
+ xdc.includeFile("ti/configs/vayu/Ipu1Smp.cfg");
+ }
+ else {
+ xdc.includeFile("ti/configs/vayu/Ipu2Smp.cfg");
+ }
xdc.includeFile("ti/configs/vayu/IpuAmmu.cfg");
}
-else if (Program.platformName.match(/^ti\.platform\.vayu\.dsp1/) ||
- (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
- Program.cpu.attrs.cpuCore.match(/^6600$/))) {
+else if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX/) &&
+ Program.cpu.attrs.cpuCore.match(/^6600$/)) {
/* This initializes the MessageQ Transport RPMSG stack: */
xdc.loadPackage('ti.ipc.ipcmgr');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
VirtioSetup.common$.diags_INFO = Diags.ALWAYS_ON;
- xdc.includeFile("ti/configs/vayu/Dsp1.cfg");
+ if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX\:dsp1/)) {
+ xdc.includeFile("ti/configs/vayu/Dsp1.cfg");
+ }
+ else {
+ xdc.includeFile("ti/configs/vayu/Dsp2.cfg");
+ }
}
else {
xdc.loadCapsule("messageq_common.cfg.xs");
diff --git a/packages/ti/ipc/tests/test_omx_dsp_vayu.cfg b/packages/ti/ipc/tests/test_omx_dsp_vayu.cfg
index 491f96c0110e1061e832c84262b3679f840a4146..4795b6ef36609984d8cb16392ff45b2add82438b 100644 (file)
rcmSettings.ipc = rcmSettings.IpcSupport_ti_sdo_ipc;
xdc.useModule('ti.grcm.RcmServer');
-xdc.includeFile("ti/configs/vayu/Dsp1.cfg");
+if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX\:dsp1/)) {
+ xdc.includeFile("ti/configs/vayu/Dsp1.cfg");
+}
+else {
+ xdc.includeFile("ti/configs/vayu/Dsp2.cfg");
+}
var Task = xdc.useModule('ti.sysbios.knl.Task');
Task.defaultStackSize = 12 * 0x400;
diff --git a/packages/ti/ipc/tests/test_omx_ipu_vayu.cfg b/packages/ti/ipc/tests/test_omx_ipu_vayu.cfg
index 844e2605d3a68cbbb424f22eb0026838adf86ba2..fd50568cb75f20ae8824a928459cae567bd112d7 100644 (file)
xdc.useModule('ti.grcm.RcmServer');
xdc.loadCapsule("ti/configs/vayu/IpcCommon.cfg.xs");
-xdc.loadCapsule("ti/configs/vayu/Ipu2Smp.cfg");
+if (Program.platformName.match(/^ti\.platforms\.evmDRA7XX\:ipu1/)) {
+ xdc.includeFile("ti/configs/vayu/Ipu1Smp.cfg");
+}
+else {
+ xdc.includeFile("ti/configs/vayu/Ipu2Smp.cfg");
+}
xdc.loadCapsule("ti/configs/vayu/IpuAmmu.cfg");
var Task = xdc.useModule('ti.sysbios.knl.Task');