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raw | patch | inline | side by side (from parent 1: 364bea9)
raw | patch | inline | side by side (from parent 1: 364bea9)
| author | vwan@ti.com <vwan@ti.com> | |
| Fri, 13 Mar 2015 20:55:38 +0000 (13:55 -0700) | ||
| committer | Robert Tivy <rtivy@ti.com> | |
| Wed, 25 Mar 2015 23:41:23 +0000 (16:41 -0700) |
Cleaned-up version of original commit from Praveen Rao.
Signed-off-by: VW <vwan@ti.com>
Signed-off-by: VW <vwan@ti.com>
diff --git a/qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/syslink_main.c b/qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/syslink_main.c
index 5979e6fc76e6a88ca06572f5acd4185bedddcc19..8edddf7cd6b060d2b9411c618185c2a6c00dc181 100644 (file)
#else
printf("\n%s: [-gdca] <core_id1> <executable1> [<core_id2> <executable2> ...]\n",
app);
- printf(" <core_id#> should be set to a core name (e.g. DSP1, IPU2)\n");
+ printf(" <core_id#> should be set to a core name (e.g. DSP1, DSP2, IPU1, IPU2)\n");
printf(" followed by the path to the executable to load on that core.\n");
printf("Options:\n");
printf(" -g enable GateMP support on host\n");
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c
index f976a7277f68b735976216b4b2641b386c10ca53..bbd91318d66c9343659da75bc4bbe0451dac0ea0 100644 (file)
* =============================================================================
*/
/* DSP PRCM Regs*/
-#define CM_DSP_CLKSTCTRL 0x400
-#define CM_DSP_STATICDEP 0x404
-#define CM_DSP_DYNMICDEP 0x408
-#define CM_DSP_DSP_CLKCTRL 0x420
-
-#define PM_DSP_PWRSTCTRL 0x400
-#define PM_DSP_PWRSTST 0x404
-#define RM_DSP_RSTCTRL 0x410
-#define RM_DSP_RSTST 0x414
+#define CM_DSP_CLKSTCTRL 0x00
+#define CM_DSP_STATICDEP 0x04
+#define CM_DSP_DYNMICDEP 0x08
+#define CM_DSP_DSP_CLKCTRL 0x20
+
+#define PM_DSP_PWRSTCTRL 0x00
+#define PM_DSP_PWRSTST 0x04
+#define RM_DSP_RSTCTRL 0x10
+#define RM_DSP_RSTST 0x14
#define DSP_SYS_MMU_CONFIG_OFFSET 0x18
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c
index f531a92db07f4318afce59bb11634bfb711af6f7..b9fc5feaa9898cbed4471db25766b5411e78e4fa 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2015, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
Int status = PROCESSOR_SUCCESS;
VAYUDSP_HalObject * halObject = NULL;
Memory_MapInfo mapInfo;
+ UInt16 dsp1ProcId = MultiProc_getId("DSP1");
GT_1trace (curTrace, GT_ENTER, "VAYUDSP_phyShmemInit", halObj);
halObject = (VAYUDSP_HalObject *) halObj;
- mapInfo.src = DSP_BOOT_ADDR;
+ if (halObject->procId == dsp1ProcId) {
+ mapInfo.src = DSP1_BOOT_ADDR;
+ }
+ else {
+ mapInfo.src = DSP2_BOOT_ADDR;
+ }
mapInfo.size = DSP_BOOT_ADDR_SIZE;
mapInfo.isCached = FALSE;
halObject->generalCtrlBase = mapInfo.dst;
}
- mapInfo.src = DSP_BOOT_STAT;
- mapInfo.size = DSP_BOOT_STAT_SIZE;
- mapInfo.isCached = FALSE;
- status = Memory_map (&mapInfo);
- if (status < 0) {
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUDSP_phyShmemInit",
- status,
- "Failure in Memory_map for MMU base registers");
- halObject->bootStatBase = 0;
- }
- else {
- halObject->bootStatBase = mapInfo.dst;
- }
+ /* Not used */
+ halObject->bootStatBase = 0;
+ halObject->l2ClkBase = 0;
- mapInfo.src = L2_RAM_CLK_ENABLE;
- mapInfo.size = L2_RAM_CLK_ENABLE_SIZE;
- mapInfo.isCached = FALSE;
- status = Memory_map (&mapInfo);
- if (status < 0) {
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUDSP_phyShmemInit",
- status,
- "Failure in Memory_map for MMU base registers");
- halObject->l2ClkBase = 0;
+ if (halObject->procId == dsp1ProcId) {
+ mapInfo.src = CM_DSP1_BASE_ADDR;
}
else {
- halObject->l2ClkBase = mapInfo.dst;
+ mapInfo.src = CM_DSP2_BASE_ADDR;
}
-
- mapInfo.src = CM_BASE_ADDR;
mapInfo.size = CM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
halObject->cmBase = mapInfo.dst;
}
- mapInfo.src = PRM_BASE_ADDR;
+ if (halObject->procId == dsp1ProcId) {
+ mapInfo.src = PRM_DSP1_BASE_ADDR;
+ }
+ else {
+ mapInfo.src = PRM_DSP2_BASE_ADDR;
+ }
mapInfo.size = PRM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
halObject->prmBase = mapInfo.dst;
}
- mapInfo.src = MMU0_BASE;
+ if (halObject->procId == dsp1ProcId) {
+ mapInfo.src = MMU0_DSP1_BASE;
+ }
+ else {
+ mapInfo.src = MMU0_DSP2_BASE;
+ }
mapInfo.size = MMU0_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
halObject->mmu0Base = mapInfo.dst;
}
- mapInfo.src = MMU1_BASE;
+ if (halObject->procId == dsp1ProcId) {
+ mapInfo.src = MMU1_DSP1_BASE;
+ }
+ else {
+ mapInfo.src = MMU1_DSP2_BASE;
+ }
mapInfo.size = MMU1_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
halObject->mmu1Base = mapInfo.dst;
}
- mapInfo.src = DSP_SYS_MMU_CONFIG_BASE;
+ if (halObject->procId == dsp1ProcId) {
+ mapInfo.src = DSP1_SYS_MMU_CONFIG_BASE;
+ }
+ else {
+ mapInfo.src = DSP2_SYS_MMU_CONFIG_BASE;
+ }
mapInfo.size = DSP_SYS_MMU_CONFIG_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
halObject->prmBase = 0 ;
}
- unmapInfo.addr = halObject->l2ClkBase;
- unmapInfo.size = L2_RAM_CLK_ENABLE_SIZE;
- unmapInfo.isCached = FALSE;
- if (unmapInfo.addr != 0) {
- status = Memory_unmap (&unmapInfo);
- if (status < 0) {
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUDSP_phyShmemExit",
- status,
- "Failure in Memory_Unmap for MMU base registers");
- }
- halObject->l2ClkBase = 0 ;
- }
-
- unmapInfo.addr = halObject->bootStatBase;
- unmapInfo.size = DSP_BOOT_STAT_SIZE;
- unmapInfo.isCached = FALSE;
- if (unmapInfo.addr != 0) {
- status = Memory_unmap (&unmapInfo);
- if (status < 0) {
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUDSP_phyShmemExit",
- status,
- "Failure in Memory_Unmap for MMU base registers");
- }
- halObject->bootStatBase = 0 ;
- }
+ /* Not used */
+ halObject->l2ClkBase = 0 ;
+ halObject->bootStatBase = 0 ;
unmapInfo.addr = halObject->generalCtrlBase;
unmapInfo.size = DSP_BOOT_ADDR_SIZE;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPwr.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPwr.c
index aeb71597fac9a1dce9338776674931d8181c5fcf..0d3e5fb07ad01bdf520d220d4960cb7803b7f0a4 100644 (file)
#define RM_ACTIVE_RSTCTRL 0x00000A10
#define RM_ACTIVE_RSTST 0x00000A14
-#define GEM_L2RAM_BASE_ADDR 0x40800000
+#define GEM_L2RAM_DSP1_BASE_ADDR 0x40800000
+#define GEM_L2RAM_DSP2_BASE_ADDR 0x41000000
#define GEM_L2RAM_SIZE 0x00040000
#define CTRL_MODULE_BASE_ADDR 0x48140000
Int status = PWRMGR_SUCCESS;
PwrMgr_Object * pwrMgrHandle = (PwrMgr_Object *) handle;
VAYUDSPPWR_Object * object = NULL;
+ UInt16 dsp1ProcId = MultiProc_getId("DSP1");
Memory_MapInfo mapInfo;
/* Mapping for prcm base is done in VAYUVIDEOM3_phyShmemInit */
object->controlVA = mapInfo.dst;
/* Map and get the virtual address for system l2 ram */
- mapInfo.src = GEM_L2RAM_BASE_ADDR;
+ if (handle->procId == dsp1ProcId) {
+ mapInfo.src = GEM_L2RAM_DSP1_BASE_ADDR;
+ }
+ else {
+ mapInfo.src = GEM_L2RAM_DSP2_BASE_ADDR;
+ }
mapInfo.size = GEM_L2RAM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/Platform.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/Platform.c
index 6c81521e4a239dba787eb1b47d38b9ef183fb3b4..b62422314219d8c771db27c5dd4de1e37fa19149 100644 (file)
/*!< Handle to the PwrMgr instance used */
ElfLoader_Handle ldrHandle;
/*!< Handle to the Loader instance used */
- } dsp0;
+ } dsp;
struct {
VAYUIPUCORE0PROC_Handle pHandle;
/*!< Handle to the Processor instance used */
/* Override the MESSAGEQCOPY default config */
config->MQCopyConfig.intId[1] = 173; // 141 + 32
config->MQCopyConfig.intId[2] = 168; // 136 + 32
+ config->MQCopyConfig.intId[3] = 173; // 141 + 32
config->MQCopyConfig.intId[4] = 168; // 136 + 32
#if !defined(IPC_BUILD_OPTIMIZE)
/* Create an instance of the Processor object for
* VAYUDSP */
VAYUDSPPROC_Params_init (NULL, &lv->dspProcParams);
- handle->sHandles.dsp0.pHandle = VAYUDSPPROC_create (procId,
+ handle->sHandles.dsp.pHandle = VAYUDSPPROC_create (procId,
&lv->dspProcParams);
/* Create an instance of the ELF Loader object */
ElfLoader_Params_init (NULL, &lv->elfLoaderParams);
- handle->sHandles.dsp0.ldrHandle =
+ handle->sHandles.dsp.ldrHandle =
ElfLoader_create (procId,
&lv->elfLoaderParams);
/* Create an instance of the PwrMgr object for VAYUDSP */
VAYUDSPPWR_Params_init (&lv->dspPwrParams);
- handle->sHandles.dsp0.pwrHandle = VAYUDSPPWR_create (procId,
+ handle->sHandles.dsp.pwrHandle = VAYUDSPPWR_create (procId,
&lv->dspPwrParams);
- if (handle->sHandles.dsp0.pHandle == NULL) {
+ if (handle->sHandles.dsp.pHandle == NULL) {
status = Platform_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
status,
"VAYUDSPPROC_create failed!");
}
- else if (handle->sHandles.dsp0.ldrHandle == NULL) {
+ else if (handle->sHandles.dsp.ldrHandle == NULL) {
status = Platform_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
status,
"Failed to create loader instance!");
}
- else if (handle->sHandles.dsp0.pwrHandle == NULL) {
+ else if (handle->sHandles.dsp.pwrHandle == NULL) {
status = Platform_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
else {
/* Initialize parameters */
ProcMgr_Params_init (NULL, &lv->params);
- lv->params.procHandle = handle->sHandles.dsp0.pHandle;
- lv->params.loaderHandle = handle->sHandles.dsp0.ldrHandle;
- lv->params.pwrHandle = handle->sHandles.dsp0.pwrHandle;
+ lv->params.procHandle = handle->sHandles.dsp.pHandle;
+ lv->params.loaderHandle = handle->sHandles.dsp.ldrHandle;
+ lv->params.pwrHandle = handle->sHandles.dsp.pwrHandle;
+ handle->pmHandle = ProcMgr_create (procId, &lv->params);
+ if (handle->pmHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "ProcMgr_create failed!");
+ }
+ }
+ }
+ }
+
+ if (status >= 0) {
+ /* Get MultiProc ID by name. */
+ procId = MultiProc_getId ("DSP2");
+
+ handle = &Platform_objects [procId];
+ VAYUDSPPROC_getConfig (&lv->dspProcConfig);
+ status = VAYUDSPPROC_setup (&lv->dspProcConfig);
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "VAYUDSPPROC_setup failed!");
+ }
+ else {
+ VAYUDSPPWR_getConfig (&lv->dspPwrConfig);
+ status = VAYUDSPPWR_setup (&lv->dspPwrConfig);
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "VAYUDSPPWR_setup failed!");
+ }
+ }
+
+ if (status >= 0) {
+ /* Create an instance of the Processor object for
+ * VAYUDSP */
+ VAYUDSPPROC_Params_init (NULL, &lv->dspProcParams);
+ handle->sHandles.dsp.pHandle = VAYUDSPPROC_create (procId,
+ &lv->dspProcParams);
+
+ /* Create an instance of the ELF Loader object */
+ ElfLoader_Params_init (NULL, &lv->elfLoaderParams);
+ handle->sHandles.dsp.ldrHandle =
+ ElfLoader_create (procId,
+ &lv->elfLoaderParams);
+ /* Create an instance of the PwrMgr object for VAYUDSP */
+ VAYUDSPPWR_Params_init (&lv->dspPwrParams);
+ handle->sHandles.dsp.pwrHandle = VAYUDSPPWR_create (procId,
+ &lv->dspPwrParams);
+
+ if (handle->sHandles.dsp.pHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "VAYUDSPPROC_create failed!");
+ }
+ else if (handle->sHandles.dsp.ldrHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "Failed to create loader instance!");
+ }
+ else if (handle->sHandles.dsp.pwrHandle == NULL) {
+ status = Platform_E_FAIL;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_setup",
+ status,
+ "VAYUDSPPWR_create failed!");
+ }
+ else {
+ /* Initialize parameters */
+ ProcMgr_Params_init (NULL, &lv->params);
+ lv->params.procHandle = handle->sHandles.dsp.pHandle;
+ lv->params.loaderHandle = handle->sHandles.dsp.ldrHandle;
+ lv->params.pwrHandle = handle->sHandles.dsp.pwrHandle;
handle->pmHandle = ProcMgr_create (procId, &lv->params);
if (handle->pmHandle == NULL) {
status = Platform_E_FAIL;
GT_0trace (curTrace, GT_ENTER, "_Platform_destroy");
- /* ------------------------- DSP cleanup -------------------------------- */
+ /* ------------------------- DSP1 cleanup -------------------------------- */
handle = &Platform_objects [MultiProc_getId ("DSP1")];
if (handle->pmHandle != NULL) {
status = ProcMgr_delete (&handle->pmHandle);
}
/* Delete the Processor, Loader and PwrMgr instances */
- if (handle->sHandles.dsp0.pwrHandle != NULL) {
- tmpStatus = VAYUDSPPWR_delete (&handle->sHandles.dsp0.pwrHandle);
+ if (handle->sHandles.dsp.pwrHandle != NULL) {
+ tmpStatus = VAYUDSPPWR_delete (&handle->sHandles.dsp.pwrHandle);
+ GT_assert (curTrace, (tmpStatus >= 0));
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "VAYUDSPPWR_delete failed!");
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+ }
+
+ if (handle->sHandles.dsp.ldrHandle != NULL) {
+ tmpStatus = ElfLoader_delete (&handle->sHandles.dsp.ldrHandle);
+ GT_assert (curTrace, (tmpStatus >= 0));
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "Failed to delete loader instance!");
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+ }
+
+ if (handle->sHandles.dsp.pHandle != NULL) {
+ tmpStatus = VAYUDSPPROC_delete (&handle->sHandles.dsp.pHandle);
+ GT_assert (curTrace, (tmpStatus >= 0));
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "VAYUDSPPROC_delete failed!");
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+ }
+
+ /* ------------------------- DSP2 cleanup -------------------------------- */
+ handle = &Platform_objects [MultiProc_getId ("DSP2")];
+ if (handle->pmHandle != NULL) {
+ status = ProcMgr_delete (&handle->pmHandle);
+ GT_assert (curTrace, (status >= 0));
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_Platform_destroy",
+ status,
+ "ProcMgr_delete failed!");
+ }
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ }
+
+ /* Delete the Processor, Loader and PwrMgr instances */
+ if (handle->sHandles.dsp.pwrHandle != NULL) {
+ tmpStatus = VAYUDSPPWR_delete (&handle->sHandles.dsp.pwrHandle);
GT_assert (curTrace, (tmpStatus >= 0));
if ((status >= 0) && (tmpStatus < 0)) {
status = tmpStatus;
}
}
- if (handle->sHandles.dsp0.ldrHandle != NULL) {
- tmpStatus = ElfLoader_delete (&handle->sHandles.dsp0.ldrHandle);
+ if (handle->sHandles.dsp.ldrHandle != NULL) {
+ tmpStatus = ElfLoader_delete (&handle->sHandles.dsp.ldrHandle);
GT_assert (curTrace, (tmpStatus >= 0));
if ((status >= 0) && (tmpStatus < 0)) {
status = tmpStatus;
}
}
- if (handle->sHandles.dsp0.pHandle != NULL) {
- tmpStatus = VAYUDSPPROC_delete (&handle->sHandles.dsp0.pHandle);
+ if (handle->sHandles.dsp.pHandle != NULL) {
+ tmpStatus = VAYUDSPPROC_delete (&handle->sHandles.dsp.pHandle);
GT_assert (curTrace, (tmpStatus >= 0));
if ((status >= 0) && (tmpStatus < 0)) {
status = tmpStatus;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c
index 560e4886acbc28d18a1f1ab15ddcce80e71b4ae6..9a25958bd8c9f829b639db58055eb9b9fc50d0db 100644 (file)
#define MPU_INT_OFFSET 32
/*!
- * @brief Interrupt Id for DSP MMU faults
+ * @brief Interrupt Id for DSP1 MMU faults
*/
-#define MMU_FAULT_INTR_DSP1_MMU0 60
+#define MMU_FAULT_INTR_DSP1_MMU0 28
+
#define MMU_FAULT_INTR_DSP1_MMU1 143
#define MMU_XBAR_INTR_DSP1_MMU1 145
+/*!
+ * @brief Interrupt Id for DSP2 MMU faults
+ */
+#define MMU_FAULT_INTR_DSP2_MMU0 144
+#define MMU_XBAR_INTR_DSP2_MMU0 146
+
+#define MMU_FAULT_INTR_DSP2_MMU1 145
+#define MMU_XBAR_INTR_DSP2_MMU1 147
+
+
/*!
* @brief CAM register field values
*/
Int status = PROCESSOR_SUCCESS;
VAYUDSP_HalMmuObject * mmu0Obj, *mmu1Obj;
OsalIsr_Params isrParams;
- UInt32 reg = 0;
+ UInt32 reg = 0;
+ UInt16 dsp1ProcId = MultiProc_getId("DSP1");
GT_3trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuEnable",
halObject, numMemEntries, memTable);
REG32(halObject->ctrlModBase + CTRL_MODULE_MMR_OFFSET) = 0xF757FDC0;
/* Program the IntXbar */
- reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1));
- if ((MMU_FAULT_INTR_DSP1_MMU1 - CTRL_MODULE_INT_BASE) % 2) {
- REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
- (reg & 0x0000FFFF) | (MMU_XBAR_INTR_DSP1_MMU1 << 16);
+ if (halObject->procId == dsp1ProcId) {
+ reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1));
+ if ((MMU_FAULT_INTR_DSP1_MMU1 - CTRL_MODULE_INT_BASE) % 2) {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
+ (reg & 0x0000FFFF) | (MMU_XBAR_INTR_DSP1_MMU1 << 16);
+ }
+ else {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
+ (reg & 0xFFFF0000) | (MMU_XBAR_INTR_DSP1_MMU1);
+ }
}
else {
- REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
- (reg & 0xFFFF0000) | (MMU_XBAR_INTR_DSP1_MMU1);
+ reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP2_MMU0));
+ if ((MMU_FAULT_INTR_DSP2_MMU0 - CTRL_MODULE_INT_BASE) % 2) {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP2_MMU0)) =
+ (reg & 0x0000FFFF) | (MMU_XBAR_INTR_DSP2_MMU0 << 16);
+ }
+ else {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP2_MMU0)) =
+ (reg & 0xFFFF0000) | (MMU_XBAR_INTR_DSP2_MMU0);
+ }
+
+ reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP2_MMU1));
+ if ((MMU_FAULT_INTR_DSP2_MMU1 - CTRL_MODULE_INT_BASE) % 2) {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP2_MMU1)) =
+ (reg & 0x0000FFFF) | (MMU_XBAR_INTR_DSP2_MMU1 << 16);
+ }
+ else {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP2_MMU1)) =
+ (reg & 0xFFFF0000) | (MMU_XBAR_INTR_DSP2_MMU1);
+ }
}
/* Create the ISR to listen for MMU Faults */
isrParams.sharedInt = FALSE;
isrParams.checkAndClearFxn = &_VAYUDSP_halMmuCheckAndClearFunc;
isrParams.fxnArgs = halObject;
- isrParams.intId = MMU_FAULT_INTR_DSP1_MMU0;
+ isrParams.intId = (dsp1ProcId == halObject->procId ?
+ MMU_FAULT_INTR_DSP1_MMU0 + MPU_INT_OFFSET: MMU_FAULT_INTR_DSP2_MMU0 + MPU_INT_OFFSET);
mmu0Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
halObject,
&isrParams);
- isrParams.intId = MMU_FAULT_INTR_DSP1_MMU1;
+ isrParams.intId = (dsp1ProcId == halObject->procId ?
+ MMU_FAULT_INTR_DSP1_MMU1 + MPU_INT_OFFSET: MMU_FAULT_INTR_DSP2_MMU1+ MPU_INT_OFFSET);
mmu1Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
halObject,
&isrParams);
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspEnabler.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspEnabler.h
index 1808c6c1cffdaa2425b688ca83f8932331364f4f..322d79404ff4255e5d3e00da517865248a777149 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2015, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
Taken from iommu2.h of Linux
*/
-#define MMU_DSP_ENABLER_BASE 0x55082000
+#define MMU_DSP_ENABLER_BASE 0x55082000 // Praveen...wrong for DSP.. looks like copied from IPU
#define MMU_REVISION MMU_DSP_ENABLER_BASE + 0x00
#define MMU_SYSCONFIG MMU_DSP_ENABLER_BASE + 0x10
#define MMU_SYSSTATUS MMU_DSP_ENABLER_BASE + 0x14
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h
index 5ce2cd7bc6a72cb6f33f0c7de699a8833ed5cb43..efc6191af5a8c0fcf802b84db41a68cfd33af6d1 100644 (file)
/*
* ============================================================================
*
- * Copyright (c) 2013, Texas Instruments Incorporated
+ * Copyright (c) 2013-2015, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* See _ProcDefs.h
* =============================================================================
*/
-/*!
- * @brief Base addresses of dsp boot stat reg to indicate the boot complete.
- */
-#define DSP_BOOT_STAT 0x48140044
-#define DSP_BOOT_STAT_SIZE 0x4
/*!
- * @brief Base addresses of L2_RAM for Ducati.
+ * @brief Base addresses of Reset Vector for DSP
*/
-#define DSP_BOOT_ADDR 0x4a00255c
+#define DSP1_BOOT_ADDR 0x4a00255c
+#define DSP2_BOOT_ADDR 0x4a002560
-/*!
- * @brief Base addresses of L2_RAM for Ducati.
- */
#define DSP_BOOT_ADDR_SIZE 0x4
-/*!
- * @brief Base addresses of L2_RAM for clock enable.
- */
-#define L2_RAM_CLK_ENABLE 0x48140650
-
-#define L2_RAM_CLK_ENABLE_SIZE 0x4
/*!
* @brief Base addresses of PRCM module.
*/
-#define PRM_BASE_ADDR 0x4Ae06000
-/*!
- * @brief Base addresses of different peripherals.
- */
+#define PRM_DSP1_BASE_ADDR 0x4Ae06400
+#define PRM_DSP2_BASE_ADDR 0x4Ae07b00
-#define PRM_SIZE 0x00002000
+#define PRM_SIZE 0x00000200
/*!
- * @brief Base addresses of PRCM module.
- */
-#define CM_BASE_ADDR 0x4A005000
-/*!
- * @brief Base addresses of different peripherals.
+ * @brief Base addresses of CM module.
*/
+#define CM_DSP1_BASE_ADDR 0x4A005400
+#define CM_DSP2_BASE_ADDR 0x4A005600
-#define CM_SIZE 0x00002000
+#define CM_SIZE 0x00000200
-#define DSP_SYS_MMU_CONFIG_BASE 0x40D00000
/*!
- * @brief size to be ioremapped.
+ * @brief Base addresses to be DSP MMU
*/
+#define DSP1_SYS_MMU_CONFIG_BASE 0x40D00000
+#define DSP2_SYS_MMU_CONFIG_BASE 0x41500000
+
+
#define DSP_SYS_MMU_CONFIG_SIZE 0x1000
-#define MMU0_BASE 0x40D01000
-/*!
- * @brief size to be ioremapped.
- */
-#define MMU0_SIZE 0x1000
+#define MMU0_DSP1_BASE 0x40D01000
+#define MMU0_DSP2_BASE 0x41501000
+
+#define MMU0_SIZE 0x1000
+
+#define MMU1_DSP1_BASE 0x40D02000
+#define MMU1_DSP2_BASE 0x41502000
-#define MMU1_BASE 0x40D02000
-/*!
- * @brief size to be ioremapped.
- */
#define MMU1_SIZE 0x1000
/*!
diff --git a/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c b/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c
index b2464b56ab44b5e4d0ca280d83cb58860ccef4bf..f485bcb15af75cb3d67b003c271690eaafe076b5 100644 (file)
#define HOST_IPU2_SUB_MBOX 6
/*!
- * @def VAYU_HOST_DSP1_2_MBOX
+ * @def VAYU_HOST_DSP1_MBOX
* @brief Mailbox used for HOST<->DSP1 communication.
*/
#define VAYU_HOST_DSP1_MBOX 5
*/
#define HOST_DSP1_SUB_MBOX 5
+/*!
+ * @def VAYU_HOST_DSP2_MBOX
+ * @brief Mailbox used for HOST<->DSP2 communication.
+ */
+#define VAYU_HOST_DSP2_MBOX 6
+
+/*!
+ * @def DSP2_HOST_SUB_MBOX
+ * @brief Mailbox used for DSP2->HOST communication.
+ */
+#define DSP2_HOST_SUB_MBOX 1
+
+/*!
+ * @def HOST_DSP2_SUB_MBOX
+ * @brief Mailbox used for HOST->DSP2 communication.
+ */
+#define HOST_DSP2_SUB_MBOX 5
+
/*!
* @def VAYU_HOST_USER_ID
* @brief User ID of HOST.
*/
#define VAYU_DSP1_USER_ID 0
+/*!
+ * @def VAYU_DSP2_USER_ID
+ * @brief User ID of DSP2.
+ */
+#define VAYU_DSP2_USER_ID 0
+
/* Macro to make a correct module magic number with refCount */
#define VAYUIPCINT_MAKE_MAGICSTAMP(x) \
((VAYUIPCINT_MODULEID << 12u) | (x))
*/
#define IRQ_XBAR_DSP1 IRQ_XBAR_MBOX_5_USR_2
+/*!
+ * @def IRQ_XBAR_DSP2
+ * @brief irq xbar num for dsp2.
+ */
+#define IRQ_XBAR_DSP2 IRQ_XBAR_MBOX_6_USR_2
+
/*!
* @def IRQ_XBAR_IPU1
* @brief irq xbar num for ipu1.
*/
VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1] =
MultiProc_getId ("DSP1");
+ VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2] =
+ MultiProc_getId ("DSP2");
VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1] =
MultiProc_getId ("IPU1");
VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2] =
if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1]) {
mboxId = IRQ_XBAR_DSP1;
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2]) {
+ mboxId = IRQ_XBAR_DSP2;
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]){
mboxId = IRQ_XBAR_IPU1;
}
VAYU_MAILBOX_IRQENABLE(VAYU_HOST_USER_ID)),
( (DSP1_HOST_SUB_MBOX) << 1));
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2]) {
+ /*
+ * Mailbox 6 is used for HOST<->DSP2 communication
+ */
+ SET_BIT(REG(VAYUIpcInt_state.mailbox6Base + \
+ VAYU_MAILBOX_IRQENABLE(VAYU_HOST_USER_ID)),
+ ( (DSP2_HOST_SUB_MBOX) << 1));
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
/*
* Mailbox 5 is used for HOST<->IPU1 communication
MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)) =
1 << ((DSP1_HOST_SUB_MBOX) << 1);
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2]) {
+ /*
+ * Mailbox 6 is used for HOST<->DSP2 communication
+ */
+ REG(VAYUIpcInt_state.mailbox6Base + \
+ MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)) =
+ 1 << ((DSP2_HOST_SUB_MBOX) << 1);
+
+/* SET_BIT(REG(VAYUIpcInt_state.mailbox6Base + \
+ MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)),
+ ( (DSP2_HOST_SUB_MBOX) << 1));*/
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
/*
* Mailbox 5 is used for HOST<->IPU1 communication
+ MAILBOX_MSGSTATUS_m_OFFSET(HOST_DSP1_SUB_MBOX)))
& 0x3F ));
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2]) {
+ /* Wait for DSP to clear the previous interrupt */
+ while( ( REG32(( VAYUIpcInt_state.mailbox6Base
+ + MAILBOX_MSGSTATUS_m_OFFSET(HOST_DSP2_SUB_MBOX)))
+ & 0x3F ));
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
/* Wait for M4 to clear the previous interrupt */
while( ( REG32((VAYUIpcInt_state.mailbox5Base
REG32(VAYUIpcInt_state.mailbox5Base + \
MAILBOX_MESSAGE_m_OFFSET(HOST_DSP1_SUB_MBOX)) = value;
}
+ else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2]) {
+ /*
+ * Mailbox 6 is used for HOST<->DSP2 communication
+ */
+ REG32(VAYUIpcInt_state.mailbox6Base + \
+ MAILBOX_MESSAGE_m_OFFSET(HOST_DSP2_SUB_MBOX)) = value;
+ }
else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
/*
* Mailbox 5 is used for HOST<->IPU1 communication
GT_1trace (curTrace,GT_ENTER,"VAYUIpcInt_clearInterrupt", mboxNum);
GT_assert (curTrace,(ArchIpcInt_object.isSetup == TRUE));
-
- if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2])
+ if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2] ||
+ procId == VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2])
mailboxBase = VAYUIpcInt_state.mailbox6Base;
else
mailboxBase = VAYUIpcInt_state.mailbox5Base;
List_put(VAYUIpcInt_state.isrLists[procId], (List_Elem *)elem);
}
}
+ if (REG32(VAYUIpcInt_state.mailbox6Base
+ + MAILBOX_MSGSTATUS_m_OFFSET(DSP2_HOST_SUB_MBOX)) != 0 ){
+ procId = VAYUIpcInt_state.procIds [VAYU_INDEX_DSP2];
+ msg = VAYUIpcInt_clearInterrupt (procId, DSP2_HOST_SUB_MBOX);
+
+ GT_1trace (curTrace, GT_1CLASS, "Got msg [0x%08x] from DSP2", msg);
+
+ /* This is a message from DSP2, put the message in DSP2's list */
+ elem = get_msg();
+ if (elem) {
+ elem->msg = msg;
+ List_put(VAYUIpcInt_state.isrLists[procId], (List_Elem *)elem);
+ }
+ }
if (REG32(VAYUIpcInt_state.mailbox5Base
+ MAILBOX_MSGSTATUS_m_OFFSET(DSP1_HOST_SUB_MBOX)) != 0 ){
procId = VAYUIpcInt_state.procIds [VAYU_INDEX_DSP1];
GT_1trace (curTrace, GT_1CLASS, "Got msg [0x%08x] from DSP1", msg);
- /* This is a message from DSP, put the message in DSP's list */
+ /* This is a message from DSP1, put the message in DSP1's list */
elem = get_msg();
if (elem) {
elem->msg = msg;