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raw | patch | inline | side by side (parent: 64cff59)
raw | patch | inline | side by side (parent: 64cff59)
author | vwan@ti.com <vwan@ti.com> | |
Thu, 27 Feb 2014 22:49:06 +0000 (14:49 -0800) | ||
committer | Chris Ring <cring@ti.com> | |
Sun, 2 Mar 2014 17:46:21 +0000 (09:46 -0800) |
The mailbox interrupt handling code in QNX IPC uses the SET_BIT macro to
clear status bits from the MAILBOX_IRQSTATUS_CLR_u registers. This is wrong,
because the macro does as follows:
>#define SET_BIT(num,pos) ((num) |= (1u << (pos)))
It will read the register and end up clearing *ALL* bits that are pending
during the write-back, as opposed to the specific one it needs to clear. If the
host is in the midst of processing an interrupt from a given core when a second
core writes to its (sub)mailbox, the second payload may be lost.
This commit changes the SET_BIT call to a direct register assignment of the
appropriate bit mask.
Signed-off-by: VW <vwan@ti.com>
clear status bits from the MAILBOX_IRQSTATUS_CLR_u registers. This is wrong,
because the macro does as follows:
>#define SET_BIT(num,pos) ((num) |= (1u << (pos)))
It will read the register and end up clearing *ALL* bits that are pending
during the write-back, as opposed to the specific one it needs to clear. If the
host is in the midst of processing an interrupt from a given core when a second
core writes to its (sub)mailbox, the second payload may be lost.
This commit changes the SET_BIT call to a direct register assignment of the
appropriate bit mask.
Signed-off-by: VW <vwan@ti.com>
qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/omap5430/Omap5430IpcInt.c | patch | blob | history | |
qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c | patch | blob | history |
diff --git a/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/omap5430/Omap5430IpcInt.c b/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/omap5430/Omap5430IpcInt.c
index 1e74b1fa8d5ef6b628cd5031b414d2640d8b47af..295d01b0a7535de9a722955d8f1f6ddfd4cbe1d2 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2011-2013, Texas Instruments Incorporated
+ * Copyright (c) 2011-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
/* Clear the IRQ status.
* If there are more in the mailbox FIFO, it will re-assert.
*/
- SET_BIT(REG((Omap5430IpcInt_state.mailboxBase
- + MAILBOX_IRQSTATUS_CLEAR_OFFSET)),
- (mboxNum<<1));
+ REG32(Omap5430IpcInt_state.mailboxBase
+ + MAILBOX_IRQSTATUS_CLEAR_OFFSET) = 0x1 << (mboxNum << 1);
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
else {
diff --git a/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c b/qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c
index 791428d95a3593d1ddcd80f4598018f34ebbac88..2040e806df09a771854531f3b3f84879652afdee 100644 (file)
/* Clear the IRQ status.
* If there are more in the mailbox FIFO, it will re-assert.
*/
- SET_BIT(REG(mailboxBase + MAILBOX_IRQSTATUS_CLEAR_OFFSET + \
- (0x10 * VAYU_HOST_USER_ID)),
- (mboxNum<<1));
+ REG32(mailboxBase + MAILBOX_IRQSTATUS_CLEAR_OFFSET + \
+ (0x10 * VAYU_HOST_USER_ID)) = 0x1 << (mboxNum << 1);
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
else {