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raw | patch | inline | side by side (parent: 081f8e2)
author | vwan@ti.com <vwan@ti.com> | |
Thu, 3 Apr 2014 23:21:00 +0000 (16:21 -0700) | ||
committer | Chris Ring <cring@ti.com> | |
Sun, 6 Apr 2014 17:08:57 +0000 (10:08 -0700) |
This commit removes the SysLink_Override_Params mechanism that is used
to turn on support for slaves with MMU disabled. This mode was never
tested, nor do we anticipate supporting this in the future, given
the benefits of an MMU.
Signed-off-by: VW <vwan@ti.com>
to turn on support for slaves with MMU disabled. This mode was never
tested, nor do we anticipate supporting this in the future, given
the benefits of an MMU.
Signed-off-by: VW <vwan@ti.com>
13 files changed:
index 27aecf03d16dbf8ffc59be56d3bc0d2c9610ac1f..f87ee4c3d246817dd764694f44811bf2d584bae1 100644 (file)
/*
* ============================================================================
*
- * Copyright (c) 2008-2012, Texas Instruments Incorporated
+ * Copyright (c) 2008-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
/** @endcond */
-/**
- * @brief Config params override strings.
- *
- * This string is a list of semi-colon-delimited "assignments" that can be set
- * by users prior to the initial call to SysLink_setup() to affect system
- * behavior.
- *
- * Example assignments include:
- * - "ProcMgr.proc[DSP].mmuEnable=FALSE;"
- * - "ProcMgr.proc[VPSS-M3].mmuEnable=TRUE;"
- * - "SharedRegion.entry[1].cacheEnable=FALSE;"
- * - "SharedRegion.entry[3].cacheEnable=FALSE;"
- *
- * @remarks Note that many users don't explicitly set this string and
- * rebuild their app, but rather leverage the @c SL_PARAMS
- * environment variable to set this string's value.
- *
- * @remarks In many systems, slaveloader (or similar) is used to load
- * and start the slaves, and is therefore the initial app
- * in the system. In those systems, it's important to set
- * this variable (or @c SL_PARAMS) prior to running slaveloader.
- *
- * @remarks A common mistake is to forget to terminate the string with
- * a trailing semi-colon.
- */
-extern String SysLink_params;
-
-
/* =============================================================================
* APIs
* =============================================================================
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspProc.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspProc.c
index 33c90656d4eda05417f32cb40b4a29f02e422b14..e3e264553a3624f3146b2013a6f99a54c01a7993 100644 (file)
*/
#define AddrTable_SIZE 32
-/* config param for dsp mmu */
-#define PARAMS_mmuEnable "ProcMgr.proc[DSP1].mmuEnable="
-
/*!
* @brief VAYUDSPPROC Module state object
.isSetup = FALSE,
.configSize = sizeof(VAYUDSPPROC_Config),
.gateHandle = NULL,
- .defInstParams.mmuEnable = TRUE,
.defInstParams.numMemEntries = AddrTable_STATIC_COUNT
};
#endif
if (handle == NULL) {
- /* check for instance params override */
- Cfg_propBool(PARAMS_mmuEnable, ProcMgr_sysLinkCfgParams,
- &(VAYUDSPPROC_state.defInstParams.mmuEnable));
-
Memory_copy(params, &(VAYUDSPPROC_state.defInstParams),
sizeof(VAYUDSPPROC_Params));
params->procArch = Processor_ProcArch_C66x;
- /* check for instance params override */
- Cfg_propBool(PARAMS_mmuEnable, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
-
object->pmHandle = params->pmHandle;
GT_0trace(curTrace, GT_1CLASS,
"VAYUDSPPROC_attach: Mapping memory regions");
/* search for dsp memory map */
- status = RscTable_process(procHandle->procId, object->params.mmuEnable,
+ status = RscTable_process(procHandle->procId,
TRUE,
&memBlock.numEntries);
if (status < 0 || memBlock.numEntries > SYSLINK_MAX_MEMENTRIES) {
GT_0trace(curTrace, GT_3CLASS,
"VAYUDSPPROC_attach: slave is now in reset");
- if (object->params.mmuEnable) {
- mmuEnableArgs.numMemEntries = 0;
- status = VAYUDSP_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
+ mmuEnableArgs.numMemEntries = 0;
+ status = VAYUDSP_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUDSPPROC_attach", status,
- "Failed to enable the slave MMU");
- }
- else {
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUDSPPROC_attach", status,
+ "Failed to enable the slave MMU");
+ }
+ else {
#endif
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUDSPPROC_attach: Slave MMU "
- "is configured!");
-
- /*
- * Pull DSP MMU out of reset to make internal
- * memory "loadable"
- */
- status = VAYUDSP_halResetCtrl(object->halObject,
- Processor_ResetCtrlCmd_MMU_Release);
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason(curTrace,
- GT_4CLASS,
- "VAYUDSP_halResetCtrl",
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUDSPPROC_attach: Slave MMU "
+ "is configured!");
+
+ /*
+ * Pull DSP MMU out of reset to make internal
+ * memory "loadable"
+ */
+ status = VAYUDSP_halResetCtrl(object->halObject,
+ Processor_ResetCtrlCmd_MMU_Release);
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason(curTrace,
+ GT_4CLASS,
+ "VAYUDSP_halResetCtrl",
status,
- "Reset MMU_Release failed");
- }
-#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ "Reset MMU_Release failed");
}
-#endif
- }
#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ }
}
#endif
}
if ( (procHandle->bootMode == ProcMgr_BootMode_Boot)
|| (procHandle->bootMode == ProcMgr_BootMode_NoLoad_Pwr)) {
- if (object->params.mmuEnable) {
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUDSPPROC_detach: Disabling Slave MMU ...");
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUDSPPROC_detach: Disabling Slave MMU ...");
- status = VAYUDSP_halResetCtrl(object->halObject,
- Processor_ResetCtrlCmd_MMU_Reset);
+ status = VAYUDSP_halResetCtrl(object->halObject,
+ Processor_ResetCtrlCmd_MMU_Reset);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUDSP_halResetCtrl",
- status,
- "Reset MMU failed");
- }
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUDSP_halResetCtrl",
+ status,
+ "Reset MMU failed");
+ }
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS) */
- status = VAYUDSP_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Disable, NULL);
+ status = VAYUDSP_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Disable, NULL);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUDSPPROC_detach", status,
- "Failed to disable the slave MMU");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUDSPPROC_detach", status,
+ "Failed to disable the slave MMU");
}
+#endif
/* delete all dynamically added entries */
for (i = AddrTable_STATIC_COUNT; i < AddrTable_count; i++) {
}
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS) */
- if (object->params.mmuEnable) {
- status = rproc_dsp_setup(object->halObject,
- object->params.memEntries,
- object->params.numMemEntries);
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUDSP_halResetCtrl",
- status,
- "rproc_dsp_setup failed");
- }
+ status = rproc_dsp_setup(object->halObject,
+ object->params.memEntries,
+ object->params.numMemEntries);
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUDSP_halResetCtrl",
+ status,
+ "rproc_dsp_setup failed");
}
/* release the slave cpu from reset */
if (status >= 0) {
"Failed to place slave in reset");
}
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS) */
- if (object->params.mmuEnable) {
- rproc_dsp_destroy(object->halObject);
- }
+ rproc_dsp_destroy(object->halObject);
}
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
}
}
if (*dstAddr == -1u) {
- if (!object->params.mmuEnable) {
- /* default to direct mapping (i.e. v=p) */
- *dstAddr = srcAddr;
- }
- else {
- /* srcAddr not found in slave address space */
- status = PROCESSOR_E_INVALIDARG;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUDSPPROC_translate", status,
- "srcAddr not found in slave address space");
- }
+ /* srcAddr not found in slave address space */
+ status = PROCESSOR_E_INVALIDARG;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUDSPPROC_translate", status,
+ "srcAddr not found in slave address space");
}
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
}
/* if not found and mmu is enabled, add new entry to table */
if (!found) {
- if (object->params.mmuEnable) {
- if (AddrTable_count != AddrTable_SIZE) {
- ai = &AddrTable[AddrTable_count];
-
- ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
- ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
- ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
- ai->size = sglist[i].size;
- ai->isCached = sglist[i].isCached;
- ai->refCount++;
-
- AddrTable_count++;
- }
- else {
- status = PROCESSOR_E_FAIL;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUDSPPROC_map", status,
- "AddrTable_SIZE reached!");
- }
+ if (AddrTable_count != AddrTable_SIZE) {
+ ai = &AddrTable[AddrTable_count];
+
+ ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
+ ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
+ ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
+ ai->size = sglist[i].size;
+ ai->isCached = sglist[i].isCached;
+ ai->refCount++;
+
+ AddrTable_count++;
}
else {
- /* if mmu disabled, AddrTable not updated */
- ai = NULL;
+ status = PROCESSOR_E_FAIL;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUDSPPROC_map", status,
+ "AddrTable_SIZE reached!");
}
}
if ((ai != NULL) && (ai->refCount == 1) && (status >= 0)) {
ai->isMapped = TRUE;
- if (object->params.mmuEnable) {
- /* Add entry to Dsp mmu */
- addEntryArgs.masterPhyAddr = sglist [i].paddr;
- addEntryArgs.size = sglist [i].size;
- addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- addEntryArgs.elementSize = ELEM_SIZE_16BIT;
- addEntryArgs.endianism = LITTLE_ENDIAN;
- addEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUDSP_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
+ /* Add entry to Dsp mmu */
+ addEntryArgs.masterPhyAddr = sglist [i].paddr;
+ addEntryArgs.size = sglist [i].size;
+ addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ addEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ addEntryArgs.endianism = LITTLE_ENDIAN;
+ addEntryArgs.mixedSize = MMU_TLBES;
+ status = VAYUDSP_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUDSPPROC_map", status,
- "Processor_MmuCtrlCmd_AddEntry failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUDSPPROC_map", status,
+ "Processor_MmuCtrlCmd_AddEntry failed");
}
+#endif
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
ai->mapMask = 0u;
ai->isMapped = FALSE;
- if (object->params.mmuEnable) {
- /* Remove the entry from the DSP MMU also */
- deleteEntryArgs.size = size;
- deleteEntryArgs.slaveVirtAddr = addr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
- deleteEntryArgs.endianism = LITTLE_ENDIAN;
- deleteEntryArgs.mixedSize = MMU_TLBES;
+ /* Remove the entry from the DSP MMU also */
+ deleteEntryArgs.size = size;
+ deleteEntryArgs.slaveVirtAddr = addr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ deleteEntryArgs.endianism = LITTLE_ENDIAN;
+ deleteEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUDSP_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
+ status = VAYUDSP_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUDSPPROC_unmap", status,
- "DSP MMU configuration failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUDSPPROC_unmap", status,
+ "DSP MMU configuration failed");
}
+#endif
}
}
}
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0Proc.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore0/VAYUIpuCore0Proc.c
index a66f497dc40540c55ce2cbb90dd9e9749092d6d5..adab529ed3143c9e36ce050b8612803ab1442459 100644 (file)
#define PROCID_TO_IPU(procId) (procId == VAYUIPUCORE0PROC_state.ipu1ProcId ?\
0 : 1)
-/* Config param for L2MMU. This is not a typo, we are using the
- * same name (IPU1) because both Benelli M4 processors use the
- * same L2MMU. The docs expose IPUx but not the IPUx Core1 processor.
- */
-#define PARAMS_mmuEnable1 "ProcMgr.proc[IPU1].mmuEnable="
-#define PARAMS_mmuEnable2 "ProcMgr.proc[IPU2].mmuEnable="
-
/*!
* @brief VAYUIPUCORE0PROC Module state object
.isSetup = FALSE,
.configSize = sizeof(VAYUIPUCORE0PROC_Config),
.gateHandle = NULL,
- .defInstParams.mmuEnable = TRUE,
.defInstParams.numMemEntries = AddrTable_STATIC_COUNT,
};
/* Added for Netra Benelli core1 is cortex M4 */
params->procArch = Processor_ProcArch_M4;
- /* check for instance params override */
- if (VAYUIPUCORE0PROC_state.ipu1ProcId == procHandle->procId) {
- Cfg_propBool(PARAMS_mmuEnable1, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
- }
- else {
- Cfg_propBool(PARAMS_mmuEnable2, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
- }
-
object->pmHandle = params->pmHandle;
GT_0trace(curTrace, GT_1CLASS,
"VAYUIPUCORE0PROC_attach: Mapping memory regions");
/* search for dsp memory map */
- status = RscTable_process(procHandle->procId, object->params.mmuEnable,
+ status = RscTable_process(procHandle->procId,
TRUE,
&memBlock.numEntries);
if (status < 0 || memBlock.numEntries > SYSLINK_MAX_MEMENTRIES) {
GT_0trace(curTrace, GT_1CLASS,
"VAYUIPUCORE0PROC_attach: slave is now in reset");
- if (object->params.mmuEnable) {
- mmuEnableArgs.numMemEntries = 0;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
+ mmuEnableArgs.numMemEntries = 0;
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_attach", status,
+ "Failed to enable the slave MMU");
+ }
+ else {
+#endif
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUIPUCORE0PROC_attach: Slave MMU "
+ "is configured!");
+ /*
+ * Pull IPU MMU out of reset to make internal
+ * memory "loadable"
+ */
+ status = VAYUIPUCORE0_halResetCtrl(
+ object->halObject,
+ Processor_ResetCtrlCmd_MMU_Release);
if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_attach", status,
- "Failed to enable the slave MMU");
+ /*! @retval status */
+ GT_setFailureReason(curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE0_halResetCtrl",
+ status,
+ "Reset MMU_Release failed");
}
- else {
-#endif
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUIPUCORE0PROC_attach: Slave MMU "
- "is configured!");
- /*
- * Pull IPU MMU out of reset to make internal
- * memory "loadable"
- */
- status = VAYUIPUCORE0_halResetCtrl(
- object->halObject,
- Processor_ResetCtrlCmd_MMU_Release);
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason(curTrace,
- GT_4CLASS,
- "VAYUIPUCORE0_halResetCtrl",
- status,
- "Reset MMU_Release failed");
- }
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- }
-#endif
}
-#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
#endif
}
if ( (procHandle->bootMode == ProcMgr_BootMode_Boot)
|| (procHandle->bootMode == ProcMgr_BootMode_NoLoad_Pwr)) {
- if (object->params.mmuEnable) {
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUIPUCORE0PROC_detach: Disabling Slave MMU ...");
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUIPUCORE0PROC_detach: Disabling Slave MMU ...");
- status = VAYUIPUCORE0_halResetCtrl(object->halObject,
- Processor_ResetCtrlCmd_MMU_Reset);
+ status = VAYUIPUCORE0_halResetCtrl(object->halObject,
+ Processor_ResetCtrlCmd_MMU_Reset);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIPUCORE0_halResetCtrl",
- status,
- "Reset MMU failed");
- }
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE0_halResetCtrl",
+ status,
+ "Reset MMU failed");
+ }
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) */
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Disable, NULL);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Disable, NULL);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_detach", status,
- "Failed to disable the slave MMU");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_detach", status,
+ "Failed to disable the slave MMU");
}
+#endif
/* delete all dynamically added entries */
for (i = AddrTable_STATIC_COUNT; i <
}
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) */
- if (object->params.mmuEnable) {
- status = rproc_ipu_setup(object->halObject,
- object->params.memEntries,
- object->params.numMemEntries);
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIPUCORE0_halResetCtrl",
- status,
- "rproc_ipu_setup failed");
- }
+ status = rproc_ipu_setup(object->halObject,
+ object->params.memEntries,
+ object->params.numMemEntries);
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE0_halResetCtrl",
+ status,
+ "rproc_ipu_setup failed");
}
/* release the slave cpu from reset */
if (status >= 0) {
"Failed to place slave in reset");
}
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) */
- if (object->params.mmuEnable) {
- rproc_ipu_destroy(object->halObject);
- }
+ rproc_ipu_destroy(object->halObject);
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
}
if (*dstAddr == -1u) {
- if (!object->params.mmuEnable) {
- /* default to direct mapping (i.e. v=p) */
- *dstAddr = srcAddr;
- GT_2trace(curTrace, GT_1CLASS, "VAYUIPUCORE0PROC_translate: "
- "(default) srcAddr=0x%x --> dstAddr=0x%x",
- srcAddr, *dstAddr);
- }
- else {
- /* srcAddr not found in slave address space */
- status = PROCESSOR_E_INVALIDARG;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_translate", status,
- "srcAddr not found in slave address space");
- }
+ /* srcAddr not found in slave address space */
+ status = PROCESSOR_E_INVALIDARG;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_translate", status,
+ "srcAddr not found in slave address space");
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
* the assumption is that the ammu will be used.
*/
if (!found) {
- if (object->params.mmuEnable) {
- if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
- AddrTable_SIZE) {
- ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
- [AddrTable_count[PROCID_TO_IPU
- (procHandle->procId)]];
- ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
- ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
- ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
- ai->size = sglist[i].size;
- ai->isCached = sglist[i].isCached;
- ai->refCount++;
+ if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
+ AddrTable_SIZE) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
+ [AddrTable_count[PROCID_TO_IPU
+ (procHandle->procId)]];
+ ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
+ ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
+ ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
+ ai->size = sglist[i].size;
+ ai->isCached = sglist[i].isCached;
+ ai->refCount++;
- AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
- }
- else {
- status = PROCESSOR_E_FAIL;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_map", status,
- "AddrTable_SIZE reached!");
- }
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
}
else {
- /* if mmu disabled, AddrTable not updated */
- ai = NULL;
+ status = PROCESSOR_E_FAIL;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_map", status,
+ "AddrTable_SIZE reached!");
}
}
if ((ai != NULL) && (ai->refCount == 1) && (status >= 0)) {
ai->isMapped = TRUE;
- if (object->params.mmuEnable) {
- /* add entry to L2 MMU */
- addEntryArgs.masterPhyAddr = sglist [i].paddr;
- addEntryArgs.size = sglist [i].size;
- addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- addEntryArgs.elementSize = ELEM_SIZE_16BIT;
- addEntryArgs.endianism = LITTLE_ENDIAN;
- addEntryArgs.mixedSize = MMU_TLBES;
+ /* add entry to L2 MMU */
+ addEntryArgs.masterPhyAddr = sglist [i].paddr;
+ addEntryArgs.size = sglist [i].size;
+ addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ addEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ addEntryArgs.endianism = LITTLE_ENDIAN;
+ addEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_map", status,
- "Processor_MmuCtrlCmd_AddEntry failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_map", status,
+ "Processor_MmuCtrlCmd_AddEntry failed");
}
+#endif
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
ai->mapMask = 0u;
ai->isMapped = FALSE;
- if (object->params.mmuEnable) {
- /* Remove the entry from the IPUCORE0 MMU also */
- deleteEntryArgs.size = size;
- deleteEntryArgs.slaveVirtAddr = addr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
- deleteEntryArgs.endianism = LITTLE_ENDIAN;
- deleteEntryArgs.mixedSize = MMU_TLBES;
+ /* Remove the entry from the IPUCORE0 MMU also */
+ deleteEntryArgs.size = size;
+ deleteEntryArgs.slaveVirtAddr = addr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ deleteEntryArgs.endianism = LITTLE_ENDIAN;
+ deleteEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE0PROC_unmap", status,
- "IPUCORE0 MMU configuration failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE0PROC_unmap", status,
+ "IPUCORE0 MMU configuration failed");
}
+#endif
}
}
}
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore1/VAYUIpuCore1Proc.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayuipu/vayucore1/VAYUIpuCore1Proc.c
index 56fbf4d8a04abc19d9e9f0686fa27fd4d8c03c3f..9cc0046a724813253903787b197893ba3157c5d3 100644 (file)
#define PROCID_TO_IPU(procId) (procId == VAYUIPUCORE1PROC_state.ipu1ProcId ?\
0 : 1)
-/* Config param for L2MMU. This is not a typo, we are using the
- * same name (IPU1) because both Benelli M4 processors use the
- * same L2MMU. The docs expose IPUx but not the IPUx Core1 processor.
- */
-#define PARAMS_mmuEnable1 "ProcMgr.proc[IPU1].mmuEnable="
-#define PARAMS_mmuEnable2 "ProcMgr.proc[IPU2].mmuEnable="
/*!
.isSetup = FALSE,
.configSize = sizeof (VAYUIPUCORE1PROC_Config),
.gateHandle = NULL,
- .defInstParams.mmuEnable = TRUE,
.defInstParams.numMemEntries = AddrTable_STATIC_COUNT,
};
/* Added for Netra Benelli core0 is cortex M4 */
params->procArch = Processor_ProcArch_M4;
- /* check for instance params override */
- if (VAYUIPUCORE1PROC_state.ipu1ProcId == procHandle->procId) {
- Cfg_propBool(PARAMS_mmuEnable1, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
- }
- else {
- Cfg_propBool(PARAMS_mmuEnable2, ProcMgr_sysLinkCfgParams,
- &(object->params.mmuEnable));
- }
-
object->pmHandle = params->pmHandle;
GT_0trace(curTrace, GT_1CLASS,
"VAYUIPUCORE1PROC_attach: Mapping memory regions");
/* search for dsp memory map */
- status = RscTable_process(procHandle->procId, object->params.mmuEnable,
+ status = RscTable_process(procHandle->procId,
TRUE,
&memBlock.numEntries);
if (status < 0 || memBlock.numEntries > SYSLINK_MAX_MEMENTRIES) {
GT_0trace(curTrace, GT_1CLASS,
"VAYUIPUCORE1PROC_attach: slave is now in reset");
- if (object->params.mmuEnable) {
- mmuEnableArgs.numMemEntries = 0;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
+ mmuEnableArgs.numMemEntries = 0;
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Enable, &mmuEnableArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE1PROC_attach", status,
+ "Failed to enable the slave MMU");
+ }
+ else {
+#endif
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUIPUCORE1PROC_attach: Slave MMU "
+ "is configured!");
+ /*
+ * Pull IPU MMU out of reset to make internal
+ * memory "loadable"
+ */
+ status = VAYUIPUCORE1_halResetCtrl(
+ object->halObject,
+ Processor_ResetCtrlCmd_MMU_Release);
if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE1PROC_attach", status,
- "Failed to enable the slave MMU");
+ /*! @retval status */
+ GT_setFailureReason(curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE1_halResetCtrl",
+ status,
+ "Reset MMU_Release failed");
}
- else {
-#endif
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUIPUCORE1PROC_attach: Slave MMU "
- "is configured!");
- /*
- * Pull IPU MMU out of reset to make internal
- * memory "loadable"
- */
- status = VAYUIPUCORE1_halResetCtrl(
- object->halObject,
- Processor_ResetCtrlCmd_MMU_Release);
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason(curTrace,
- GT_4CLASS,
- "VAYUIPUCORE1_halResetCtrl",
- status,
- "Reset MMU_Release failed");
- }
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- }
-#endif
}
-#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
#endif
}
if ( (procHandle->bootMode == ProcMgr_BootMode_Boot)
|| (procHandle->bootMode == ProcMgr_BootMode_NoLoad_Pwr)) {
- if (object->params.mmuEnable) {
- GT_0trace(curTrace, GT_2CLASS,
- "VAYUIPUCORE1PROC_detach: Disabling Slave MMU ...");
+ GT_0trace(curTrace, GT_2CLASS,
+ "VAYUIPUCORE1PROC_detach: Disabling Slave MMU ...");
- status = VAYUIPUCORE1_halResetCtrl(object->halObject,
- Processor_ResetCtrlCmd_MMU_Reset);
+ status = VAYUIPUCORE1_halResetCtrl(object->halObject,
+ Processor_ResetCtrlCmd_MMU_Reset);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- /*! @retval status */
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "VAYUIPUCORE1_halResetCtrl",
- status,
- "Reset MMU failed");
- }
+ if (status < 0) {
+ /*! @retval status */
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUIPUCORE1_halResetCtrl",
+ status,
+ "Reset MMU failed");
+ }
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) */
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_Disable, NULL);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_Disable, NULL);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE1PROC_detach", status,
- "Failed to disable the slave MMU");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE1PROC_detach", status,
+ "Failed to disable the slave MMU");
}
+#endif
/* delete all dynamically added entries */
for (i = AddrTable_STATIC_COUNT; i <
}
if (*dstAddr == -1u) {
- if (!object->params.mmuEnable) {
- /* default to direct mapping (i.e. v=p) */
- *dstAddr = srcAddr;
- GT_2trace(curTrace, GT_1CLASS, "VAYUIPUCORE1PROC_translate: "
- "(default) srcAddr=0x%x --> dstAddr=0x%x",
- srcAddr, *dstAddr);
- }
- else {
- /* srcAddr not found in slave address space */
- status = PROCESSOR_E_INVALIDARG;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE1PROC_translate", status,
- "srcAddr not found in slave address space");
- }
+ /* srcAddr not found in slave address space */
+ status = PROCESSOR_E_INVALIDARG;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE1PROC_translate", status,
+ "srcAddr not found in slave address space");
}
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
}
* the assumption is that the ammu will be used.
*/
if (!found) {
- if (object->params.mmuEnable) {
- if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
- AddrTable_SIZE) {
- ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
- [AddrTable_count[PROCID_TO_IPU
- (procHandle->procId)]];
- ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
- ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
- ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
- ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
- ai->size = sglist[i].size;
- ai->isCached = sglist[i].isCached;
- ai->refCount++;
+ if (AddrTable_count[PROCID_TO_IPU(procHandle->procId)] !=
+ AddrTable_SIZE) {
+ ai = &AddrTable[PROCID_TO_IPU(procHandle->procId)]
+ [AddrTable_count[PROCID_TO_IPU
+ (procHandle->procId)]];
+ ai->addr[ProcMgr_AddrType_MasterKnlVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterUsrVirt] = -1u;
+ ai->addr[ProcMgr_AddrType_MasterPhys] = sglist[i].paddr;
+ ai->addr[ProcMgr_AddrType_SlaveVirt] = *dstAddr;
+ ai->addr[ProcMgr_AddrType_SlavePhys] = -1u;
+ ai->size = sglist[i].size;
+ ai->isCached = sglist[i].isCached;
+ ai->refCount++;
- AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
- }
- else {
- status = PROCESSOR_E_FAIL;
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE1PROC_map", status,
- "AddrTable_SIZE reached!");
- }
+ AddrTable_count[PROCID_TO_IPU(procHandle->procId)]++;
}
else {
- /* if mmu disabled, AddrTable not updated */
- ai = NULL;
+ status = PROCESSOR_E_FAIL;
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE1PROC_map", status,
+ "AddrTable_SIZE reached!");
}
}
if ((ai != NULL) && (ai->refCount == 1) && (status >= 0)) {
ai->isMapped = TRUE;
- if (object->params.mmuEnable) {
- /* add entry to L2 MMU */
- addEntryArgs.masterPhyAddr = sglist [i].paddr;
- addEntryArgs.size = sglist [i].size;
- addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- addEntryArgs.elementSize = ELEM_SIZE_16BIT;
- addEntryArgs.endianism = LITTLE_ENDIAN;
- addEntryArgs.mixedSize = MMU_TLBES;
+ /* add entry to L2 MMU */
+ addEntryArgs.masterPhyAddr = sglist [i].paddr;
+ addEntryArgs.size = sglist [i].size;
+ addEntryArgs.slaveVirtAddr = (UInt32)*dstAddr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ addEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ addEntryArgs.endianism = LITTLE_ENDIAN;
+ addEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_AddEntry, &addEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE1PROC_map", status,
- "Processor_MmuCtrlCmd_AddEntry failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE1PROC_map", status,
+ "Processor_MmuCtrlCmd_AddEntry failed");
}
+#endif
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
ai->mapMask = 0u;
ai->isMapped = FALSE;
- if (object->params.mmuEnable) {
- /* Remove the entry from the IPUCORE1 MMU also */
- deleteEntryArgs.size = size;
- deleteEntryArgs.slaveVirtAddr = addr;
- /* TBD: elementSize, endianism, mixedSized are
- * hard coded now, must be configurable later
- */
- deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
- deleteEntryArgs.endianism = LITTLE_ENDIAN;
- deleteEntryArgs.mixedSize = MMU_TLBES;
+ /* Remove the entry from the IPUCORE1 MMU also */
+ deleteEntryArgs.size = size;
+ deleteEntryArgs.slaveVirtAddr = addr;
+ /* TBD: elementSize, endianism, mixedSized are
+ * hard coded now, must be configurable later
+ */
+ deleteEntryArgs.elementSize = ELEM_SIZE_16BIT;
+ deleteEntryArgs.endianism = LITTLE_ENDIAN;
+ deleteEntryArgs.mixedSize = MMU_TLBES;
- status = VAYUIPU_halMmuCtrl(object->halObject,
- Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
+ status = VAYUIPU_halMmuCtrl(object->halObject,
+ Processor_MmuCtrlCmd_DeleteEntry, &deleteEntryArgs);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (status < 0) {
- GT_setFailureReason(curTrace, GT_4CLASS,
- "VAYUIPUCORE1PROC_unmap", status,
- "IPUCORE1 MMU configuration failed");
- }
-#endif
+ if (status < 0) {
+ GT_setFailureReason(curTrace, GT_4CLASS,
+ "VAYUIPUCORE1PROC_unmap", status,
+ "IPUCORE1 MMU configuration failed");
}
+#endif
}
}
}
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/Platform.c b/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/Platform.c
index 00772bdb784ed7bd98803cc7a16e2ecb996b41dc..e65add18d8f4368232d7fabe0552fad0a6c1c7c6 100644 (file)
extern unsigned int syslink_ipu_mem_size;
extern unsigned int syslink_dsp_mem_size;
-/*
- * Variable used to override default parameters
- * Use a string of form
- * String Syslink_Override_Params = "ProcMgr.proc[DSP].mmuEnable=TRUE;"
- * "ProcMgr.proc[IPU].mmuEnable=TRUE;";
- */
-String Syslink_Override_Params = "";
-
/** ============================================================================
* APIs.
}
else {
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
- cfg->params = Memory_alloc(NULL,
- String_len(Syslink_Override_Params) + 1, 0,
- NULL);
- if (cfg->params) {
- String_cpy(cfg->params, Syslink_Override_Params);
- }
-
- _ProcMgr_saveParams(cfg->params, String_len(cfg->params));
/* Set the MultiProc config as defined in SystemCfg.c */
config->multiProcConfig = _MultiProc_cfg;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/ipu/omap5430BenelliProc.c b/qnx/src/ipc3x_dev/ti/syslink/family/omap5430/ipu/omap5430BenelliProc.c
index 130ab9109db47ad21544ac9940355fc316235c13..1c2cb7d411628ceb9233bb27a2f0d7f3d73130f2 100644 (file)
/* number of carveouts */
#define NumCarveouts 1
-/* config param for core0 mmu */
-#ifndef SYSLINK_SYSBIOS_SMP
-#define PARAMS_mmuEnable "ProcMgr.proc[CORE0].mmuEnable="
-#else
-#define PARAMS_mmuEnable "ProcMgr.proc[IPU].mmuEnable="
-#endif
-#define PARAMS_mmuEnableDSP "ProcMgr.proc[DSP].mmuEnable="
-
/*!
* @brief OMAP5430BENELLIPROC Module state object
"OMAP5430BENELLIPROC_attach: Mapping memory regions");
/* search for dsp memory map */
- status = RscTable_process(procHandle->procId, TRUE,
+ status = RscTable_process(procHandle->procId,
TRUE, &memBlock.numEntries);
if (status < 0 || memBlock.numEntries > SYSLINK_MAX_MEMENTRIES) {
/*! @retval PROCESSOR_E_INVALIDARG Invalid argument */
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/Platform.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/Platform.c
index 899c0ebad558566670d9fb1b7ea2b1b9bfc26c4a..5b0a6c1b7a2897c01aa0c0d196155c8b643f6924 100644 (file)
Int32 _Platform_setup (Ipc_Config * cfg);
Int32 _Platform_destroy (void);
-extern String ProcMgr_sysLinkCfgParams;
-
-/*
- * Variable used to override default parameters
- * Use a string of form
- * String Syslink_Override_Params = "ProcMgr.proc[DSP1].mmuEnable=TRUE;"
- * "ProcMgr.proc[IPU1].mmuEnable=TRUE;";
- */
-String Syslink_Override_Params = "";
-
/** ============================================================================
* APIs.
Platform_overrideConfig (Platform_Config * config, Ipc_Config * cfg)
{
Int32 status = Platform_S_SUCCESS;
- char * pSL_PARAMS;
GT_1trace (curTrace, GT_ENTER, "Platform_overrideConfig", config);
else {
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
- /* assign config->params - overriding with SL_PARAMS env var, if set */
- pSL_PARAMS = getenv("SL_PARAMS");
- if (pSL_PARAMS != NULL) {
- GT_2trace(curTrace, GT_1CLASS, "Overriding SysLink_params \"%s\""
- " with SL_PARAMS \"%s\"\n", Syslink_Override_Params, pSL_PARAMS);
- cfg->params = Memory_alloc(NULL, String_len(pSL_PARAMS), 0, NULL);
- if (cfg->params) {
- String_cpy(cfg->params, pSL_PARAMS);
- }
- }
- else {
- cfg->params = Memory_alloc(NULL,
- String_len(Syslink_Override_Params) + 1, 0,
- NULL);
- if (cfg->params) {
- String_cpy(cfg->params, Syslink_Override_Params);
- }
- }
-
- _ProcMgr_saveParams(cfg->params, String_len(cfg->params));
-
/* Set the MultiProc config as defined in SystemCfg.c */
config->multiProcConfig = _MultiProc_cfg;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/IpcKnl.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/IpcKnl.h
index 862d37ce18d4f5018ceb86a36820dbbf81aa3058..91d3813476810b7a5c29de0740e44ba30bd7ab15 100644 (file)
*
* ============================================================================
*
- * Copyright (c) 2008-2009, Texas Instruments Incorporated
+ * Copyright (c) 2008-2014, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
UInt32 vAddr_dsp;
UInt32 pAddr_dsp;
String fileName_dsp;
- String params;
- /*!< instance params override */
} Ipc_Config;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspProc.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspProc.h
index c719d0a57a5d6c7b3d5c2e897d5cff84af7dbcfb..8b9b4a8214d8676da4be6af2a1abb69993154eed 100644 (file)
* @brief Configuration parameters specific to this processor.
*/
typedef struct VAYUDSPPROC_Params_tag {
- Bool mmuEnable;
- /*!< Determines if mmu should be used (enabled) */
UInt32 numMemEntries;
/*!< Number of memory regions to be configured. */
ProcMgr_AddrInfo memEntries[ProcMgr_MAX_MEMORY_REGIONS];
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuCore0Proc.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuCore0Proc.h
index ee4ca612f5a83d58a24a45b52646758f91f6f630..1d55addc3f92a92f05806cc54d077d8fc7b831bb 100644 (file)
* @brief Configuration parameters specific to this processor.
*/
typedef struct VAYUIPUCORE0PROC_Params_tag {
- Bool mmuEnable;
- /*!< Determines if mmu should be used (enabled) */
UInt32 numMemEntries;
/*!< Number of memory regions to be configured. */
ProcMgr_AddrInfo memEntries[ProcMgr_MAX_MEMORY_REGIONS];
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuCore1Proc.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUIpuCore1Proc.h
index 84ab2c096af1940bcacffa38b70827cd0e298012..5e817403fa2dfbbf2782cf44647e7ba9affca4e0 100644 (file)
* @brief Configuration parameters specific to this processor.
*/
typedef struct VAYUIPUCORE1PROC_Params_tag {
- Bool mmuEnable;
- /*!< Determines if mmu should be used (enabled) */
UInt32 numMemEntries;
/*!< Number of memory regions to be configured. */
ProcMgr_AddrInfo memEntries[ProcMgr_MAX_MEMORY_REGIONS];
diff --git a/qnx/src/ipc3x_dev/ti/syslink/resources/RscTable.c b/qnx/src/ipc3x_dev/ti/syslink/resources/RscTable.c
index 946328bd09673e9e4ce09f72006013996c713f7e..18acc6f400c89857d50b5358cf17cc1e6f431a2f 100644 (file)
}
Int
-RscTable_process (UInt16 procId, Bool mmuEnabled, Bool tryAlloc,
- UInt32 * numBlocks)
+RscTable_process (UInt16 procId, Bool tryAlloc, UInt32 * numBlocks)
{
Int status = 0;
Int ret = 0;
struct fw_rsc_carveout * cout = (struct fw_rsc_carveout *)entry;
UInt32 pa = 0;
if (cout->pa == 0) {
- if (mmuEnabled) {
- ret = Chunk_allocate (obj, cout->len, &pa);
- }
- else {
- pa = cout->da;
- }
+ ret = Chunk_allocate (obj, cout->len, &pa);
}
if (!ret) {
cout->pa = pa;
obj->memEntries[obj->numMemEntries].masterPhysAddr =
cout->pa;
obj->memEntries[obj->numMemEntries].size = cout->len;
- //if (mmuEnabled) {
- obj->memEntries[obj->numMemEntries].map = TRUE;
- obj->memEntries[obj->numMemEntries].mapMask =
- ProcMgr_SLAVEVIRT;
- //}
- //else
- // obj->memEntries[obj->numMemEntries].map = FALSE;
+ obj->memEntries[obj->numMemEntries].map = TRUE;
+ obj->memEntries[obj->numMemEntries].mapMask =
+ ProcMgr_SLAVEVIRT;
obj->memEntries[obj->numMemEntries].isCached = FALSE;
obj->memEntries[obj->numMemEntries].isValid = TRUE;
obj->numMemEntries++;
ret = -1;
}
- else if (obj->vringPa != dmem->pa &&
- (!tryAlloc || !mmuEnabled)) {
+ else if (obj->vringPa != dmem->pa && (!tryAlloc)) {
// defined pa does not match allocated pa, and
// either the mmu is disabled or the platform has
// not given permission to allocate on our own
obj->memEntries[obj->numMemEntries].masterPhysAddr =
dmem->pa;
obj->memEntries[obj->numMemEntries].size = dmem->len;
- //if (mmuEnabled) {
- obj->memEntries[obj->numMemEntries].map = TRUE;
- obj->memEntries[obj->numMemEntries].mapMask =
- ProcMgr_SLAVEVIRT;
- //}
- //else
- // obj->memEntries[obj->numMemEntries].map = FALSE;
+ obj->memEntries[obj->numMemEntries].map = TRUE;
+ obj->memEntries[obj->numMemEntries].mapMask =
+ ProcMgr_SLAVEVIRT;
obj->memEntries[obj->numMemEntries].isCached = FALSE;
obj->memEntries[obj->numMemEntries].isValid = TRUE;
obj->numMemEntries++;
if (!ret) {
// HACK: round up to multiple of 1MB, because we know this
// is the size of the remote entry
- if (mmuEnabled) {
- ret = Chunk_allocate(obj,
- ROUND_UP(vr_size + vr_bufs_size, 0x100000),
- &pa);
- }
- else {
- /*
- * TBD: if mmu is disabled, we need a way to specify
- * shared memory from which to allocate the vrings
- */
- }
+ ret = Chunk_allocate(obj,
+ ROUND_UP(vr_size + vr_bufs_size, 0x100000),
+ &pa);
}
else if (obj->vrings) {
Memory_free (NULL, obj->vrings,
diff --git a/qnx/src/ipc3x_dev/ti/syslink/resources/RscTable.h b/qnx/src/ipc3x_dev/ti/syslink/resources/RscTable.h
index fdd0bfef73ea34a33c329f547ecaa5ee6bfec0d9..03abd600e38f38e7cd7691cb574ba8e530494af5 100644 (file)
Int RscTable_free (RscTable_Handle * handle);
-Int RscTable_process (UInt16 procId, Bool mmuEnabled, Bool tryAlloc,
- UInt32 * numBlocks);
+Int RscTable_process (UInt16 procId, Bool tryAlloc, UInt32 * numBlocks);
Int RscTable_getMemEntries (UInt16 procId, SysLink_MemEntry * memEntries,
UInt32 * numMemEntries);