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raw | patch | inline | side by side (parent: 0cf3614)
raw | patch | inline | side by side (parent: 0cf3614)
author | Angela Stegmaier <angelabaker@ti.com> | |
Wed, 29 May 2013 16:12:25 +0000 (09:12 -0700) | ||
committer | Chris Ring <cring@ti.com> | |
Wed, 29 May 2013 16:15:29 +0000 (09:15 -0700) |
Currently, only MMU0 is being programmed for DSP1.
For EDMA traffic, there is a second MMU (MMU1), which
needs to be programmed. DSP1 applications which
use EDMA would want to also have the MMU1 programmed
so that the address space is the same.
This patch adds programming of the DSP MMU1
with the same entries to match the programming
of the DSP MMU0.
Additionally, this patch attaches an interrupt
to the DSP1 MMU1 for notification of MMU events.
No default interrupt is programmed for DSP1 MMU1,
so an unused MPU interrupt is selected for use and
the interrupt crossbar is programmed accordingly.
The interrupt selected is MPU interrupt 143.
For EDMA traffic, there is a second MMU (MMU1), which
needs to be programmed. DSP1 applications which
use EDMA would want to also have the MMU1 programmed
so that the address space is the same.
This patch adds programming of the DSP MMU1
with the same entries to match the programming
of the DSP MMU0.
Additionally, this patch attaches an interrupt
to the DSP1 MMU1 for notification of MMU events.
No default interrupt is programmed for DSP1 MMU1,
so an unused MPU interrupt is selected for use and
the interrupt crossbar is programmed accordingly.
The interrupt selected is MPU interrupt 143.
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c
index 5e6bb19005ba8640ee02c9224090a2fdc80c01ec..6781bb2e3399a3bd14726dd66446610ccec681a3 100644 (file)
Osal_printf("DSP:RST2 released!\n");
OUTREG32(addr, 0x2);
- /* enable MMU0 through global system register */
+ /* enable MMU0 and MMU1 through global system register */
val = INREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET);
- OUTREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET, (val & ~0x1) | 0x1);
- Osal_printf("DSP:SYS_MMU_CONFIG MMU0 enabled!\n");
+ OUTREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET, (val & ~0x11) | 0x11);
+ Osal_printf("DSP:SYS_MMU_CONFIG MMU0 and MMU1 enabled!\n");
}
break;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c b/qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c
index d8eec303f8adfa23c808a8e2769da25efcb47e9c..f531a92db07f4318afce59bb11634bfb711af6f7 100644 (file)
halObject->prmBase = mapInfo.dst;
}
- mapInfo.src = MMU_BASE;
- mapInfo.size = MMU_SIZE;
+ mapInfo.src = MMU0_BASE;
+ mapInfo.size = MMU0_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
- "Failure in Memory_map for MMU base registers");
- halObject->mmuBase = 0;
+ "Failure in Memory_map for MMU0 base registers");
+ halObject->mmu0Base = 0;
+ }
+ else {
+ halObject->mmu0Base = mapInfo.dst;
+ }
+
+ mapInfo.src = MMU1_BASE;
+ mapInfo.size = MMU1_SIZE;
+ mapInfo.isCached = FALSE;
+ status = Memory_map (&mapInfo);
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUDSP_phyShmemInit",
+ status,
+ "Failure in Memory_map for MMU1 base registers");
+ halObject->mmu1Base = 0;
}
else {
- halObject->mmuBase = mapInfo.dst;
+ halObject->mmu1Base = mapInfo.dst;
}
mapInfo.src = DSP_SYS_MMU_CONFIG_BASE;
halObject->ctrlModBase = 0 ;
}
- unmapInfo.addr = halObject->mmuBase;
- unmapInfo.size = MMU_SIZE;
+ unmapInfo.addr = halObject->mmu1Base;
+ unmapInfo.size = MMU1_SIZE;
+ unmapInfo.isCached = FALSE;
+ if (unmapInfo.addr != 0) {
+ status = Memory_unmap (&unmapInfo);
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "VAYUDSP_phyShmemExit",
+ status,
+ "Failure in Memory_Unmap for MMU base registers");
+ }
+ halObject->mmu1Base = 0 ;
+ }
+
+ unmapInfo.addr = halObject->mmu0Base;
+ unmapInfo.size = MMU0_SIZE;
unmapInfo.isCached = FALSE;
if (unmapInfo.addr != 0) {
status = Memory_unmap (&unmapInfo);
status,
"Failure in Memory_Unmap for MMU base registers");
}
- halObject->mmuBase = 0 ;
+ halObject->mmu0Base = 0 ;
}
unmapInfo.addr = halObject->mmuSysBase;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspEnabler.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspEnabler.c
index f1343f0e5b019d310cf43fef936f23368c751131..94035b62c0d2d5737d56fb21bfb5830bb07ce64e 100644 (file)
#define SIZE 0x4
static UInt32 iotlb_dump_cr (struct cr_regs *cr, char *buf);
-static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
- struct iotlb_entry *e);
+static Int load_iotlb_entry (UInt32 mmuBase, struct iotlb_entry *e);
static Int iotlb_cr_valid (struct cr_regs *cr);
-static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
+static Int rproc_mem_map (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
UInt32 mpu_addr, UInt32 ul_virt_addr,
UInt32 num_bytes, UInt32 map_attr);
-static Int rproc_mem_unmap (VAYUDSP_HalObject * halObject, UInt32 da,
- UInt32 num_bytes);
+static Int rproc_mem_unmap (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
+ UInt32 da, UInt32 num_bytes);
static Void iotlb_cr_to_e (struct cr_regs *cr, struct iotlb_entry *e)
e->mixed = cr->ram & MMU_RAM_MIXED;
}
-static Void iotlb_getLock (VAYUDSP_HalObject * halObject,
- struct iotlb_lock *l)
+static Void iotlb_getLock (UInt32 mmuBase, struct iotlb_lock *l)
{
ULONG reg;
- VAYUDsp_MMURegs * mmuRegs =
- (VAYUDsp_MMURegs *)halObject->mmuBase;
+ VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
reg = INREG32(&mmuRegs->LOCK);
l->base = MMU_LOCK_BASE(reg);
l->vict = MMU_LOCK_VICT(reg);
}
-static Void iotlb_setLock (VAYUDSP_HalObject * halObject,
- struct iotlb_lock *l)
+static Void iotlb_setLock (UInt32 mmuBase, struct iotlb_lock *l)
{
ULONG reg;
- VAYUDsp_MMURegs * mmuRegs =
- (VAYUDsp_MMURegs *)halObject->mmuBase;
+ VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
reg = (l->base << MMU_LOCK_BASE_SHIFT);
reg |= (l->vict << MMU_LOCK_VICT_SHIFT);
OUTREG32(&mmuRegs->LOCK, reg);
}
-static void omap4_tlb_read_cr (VAYUDSP_HalObject * halObject,
- struct cr_regs *cr)
+static void omap4_tlb_read_cr (UInt32 mmuBase, struct cr_regs *cr)
{
- VAYUDsp_MMURegs * mmuRegs =
- (VAYUDsp_MMURegs *)halObject->mmuBase;
+ VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
cr->cam = INREG32(&mmuRegs->READ_CAM);
cr->ram = INREG32(&mmuRegs->READ_RAM);
}
/* only used for iotlb iteration in for-loop */
-static struct cr_regs __iotlb_read_cr (VAYUDSP_HalObject * halObject,
- int n)
+static struct cr_regs __iotlb_read_cr (UInt32 mmuBase, int n)
{
struct cr_regs cr;
struct iotlb_lock l;
- iotlb_getLock(halObject, &l);
+ iotlb_getLock(mmuBase, &l);
l.vict = n;
- iotlb_setLock(halObject, &l);
- omap4_tlb_read_cr(halObject, &cr);
+ iotlb_setLock(mmuBase, &l);
+ omap4_tlb_read_cr(mmuBase, &cr);
return cr;
}
#define for_each_iotlb_cr(n, __i, cr) \
for (__i = 0; \
- (__i < (n)) && (cr = __iotlb_read_cr(halObject, __i), TRUE); \
+ (__i < (n)) && (cr = __iotlb_read_cr(mmuBase, __i), TRUE); \
__i++)
static Int save_tlbs (VAYUDSP_HalObject * halObject, UINT32 procId)
Int i =0;
struct cr_regs cr_tmp;
struct iotlb_lock l;
+ UInt32 mmuBase;
- iotlb_getLock(halObject, &l);
+ iotlb_getLock(halObject->mmu0Base, &l);
- halObject->mmuObj.nrTlbs = l.base;
- for_each_iotlb_cr(halObject->mmuObj.nrTlbs, i, cr_tmp) {
- iotlb_cr_to_e(&cr_tmp, &halObject->mmuObj.tlbs[i]);
+ halObject->mmu0Obj.nrTlbs = l.base;
+ mmuBase = halObject->mmu0Base;
+
+ for_each_iotlb_cr(halObject->mmu0Obj.nrTlbs, i, cr_tmp) {
+ iotlb_cr_to_e(&cr_tmp, &halObject->mmu0Obj.tlbs[i]);
+ }
+
+ iotlb_getLock(halObject->mmu1Base, &l);
+
+ halObject->mmu1Obj.nrTlbs = l.base;
+ mmuBase = halObject->mmu1Base;
+
+ for_each_iotlb_cr(halObject->mmu1Obj.nrTlbs, i, cr_tmp) {
+ iotlb_cr_to_e(&cr_tmp, &halObject->mmu1Obj.tlbs[i]);
}
return 0;
/* Reset the base and victim values */
save.base = 0;
save.vict = 0;
- iotlb_setLock(halObject, &save);
+ iotlb_setLock(halObject->mmu0Base, &save);
+ iotlb_setLock(halObject->mmu1Base, &save);
+
+ for (i = 0; i < halObject->mmu0Obj.nrTlbs; i++) {
+ status = load_iotlb_entry(halObject->mmu0Base, &halObject->mmu0Obj.tlbs[i]);
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "restore_tlbs",
+ status,
+ "Error restoring the mmu0 tlbs");
+ goto err;
+ }
+ }
- for (i = 0; i < halObject->mmuObj.nrTlbs; i++) {
- status = load_iotlb_entry(halObject, &halObject->mmuObj.tlbs[i]);
+ for (i = 0; i < halObject->mmu1Obj.nrTlbs; i++) {
+ status = load_iotlb_entry(halObject->mmu1Base, &halObject->mmu1Obj.tlbs[i]);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"restore_tlbs",
status,
- "Error restoring the tlbs");
+ "Error restoring the mmu1 tlbs");
goto err;
}
}
return -ENOMEM;
}
- if (halObject->mmuBase == 0) {
+ if (halObject->mmu0Base == 0 || halObject->mmu1Base == 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"save_mmu_regs",
}
for (i = 0; i < MMU_REGS_SIZE; i++) {
- halObject->mmuObj.mmuRegs[i] = INREG32(halObject->mmuBase + (i * 4));
+ halObject->mmu0Obj.mmuRegs[i] = INREG32(halObject->mmu0Base + (i * 4));
+ halObject->mmu1Obj.mmuRegs[i] = INREG32(halObject->mmu1Base + (i * 4));
}
return 0;
return -ENOMEM;
}
- if (halObject->mmuBase == 0) {
+ if (halObject->mmu0Base == 0 || halObject->mmu1Base == 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"restore_mmu_regs",
}
for (i = 0; i < MMU_REGS_SIZE; i++) {
- OUTREG32(halObject->mmuBase + (i * 4), halObject->mmuObj.mmuRegs[i]);
+ OUTREG32(halObject->mmu0Base + (i * 4), halObject->mmu0Obj.mmuRegs[i]);
+ OUTREG32(halObject->mmu1Base + (i * 4), halObject->mmu1Obj.mmuRegs[i]);
}
return 0;
page_size = HW_PAGE_SIZE_4KB;
if (status == 0) {
- status = rproc_mem_map (halObject,
+ status = rproc_mem_map (halObject->mmu0Base,
+ halObject->mmu0Obj.pPtAttrs,
*phys_addr,
*dsp_addr,
page_size,
GT_4CLASS,
"add_entry_ext",
status,
- "benelli_mem_map failed");
+ "rproc_mem_map failed");
+ break;
+ }
+ status = rproc_mem_map (halObject->mmu1Base,
+ halObject->mmu1Obj.pPtAttrs,
+ *phys_addr,
+ *dsp_addr,
+ page_size,
+ flags);
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "add_entry_ext",
+ status,
+ "rproc_mem_map failed");
break;
}
mapped_size += entry_size;
return status;
}
-static Int __dump_tlb_entries (VAYUDSP_HalObject * halObject,
- struct cr_regs *crs, int num)
+static Int __dump_tlb_entries (UInt32 mmuBase, struct cr_regs *crs, int num)
{
int i;
struct iotlb_lock saved;
struct cr_regs tmp;
struct cr_regs *p = crs;
- iotlb_getLock(halObject, &saved);
+ iotlb_getLock(mmuBase, &saved);
for_each_iotlb_cr(num, i, tmp) {
if (!iotlb_cr_valid(&tmp))
continue;
*p++ = tmp;
}
- iotlb_setLock(halObject, &saved);
+ iotlb_setLock(mmuBase, &saved);
return p - crs;
}
memset(cr, 0, sizeof(struct cr_regs) * num);
- num = __dump_tlb_entries(halObject, cr, num);
+ /* Since MMU0 and MMU1 are programmed with the same entries, can just check MMU0 */
+ num = __dump_tlb_entries(halObject->mmu0Base, cr, num);
for (i = 0; i < num; i++)
{
p = cr + i;
* @obj: target iommu
* @buf: output buffer
**/
-static UInt32 dump_tlb_entries (VAYUDSP_HalObject * halObject,
- char *buf, UInt32 bytes)
+static UInt32 dump_tlb_entries (UInt32 mmuBase, char *buf, UInt32 bytes)
{
Int i, num;
struct cr_regs *cr;
}
memset(cr, 0, sizeof(struct cr_regs) * num);
- num = __dump_tlb_entries(halObject, cr, num);
+ num = __dump_tlb_entries(mmuBase, cr, num);
for (i = 0; i < num; i++)
p += iotlb_dump_cr(cr + i, p);
munmap(cr, sizeof(struct cr_regs) * num);
0);
if (MAP_FAILED != p)
{
- dump_tlb_entries(halObject, p, 1000);
+ dump_tlb_entries(halObject->mmu0Base, p, 1000);
+ dump_tlb_entries(halObject->mmu1Base, p, 1000);
munmap(p, 1000);
}
UInt32 i = 0;
UInt32 virt_addr = 0;
UInt32 reg;
- VAYUDsp_MMURegs * mmuRegs = NULL;
+ VAYUDsp_MMURegs * mmuRegs0 = NULL;
+ VAYUDsp_MMURegs * mmuRegs1 = NULL;
if (halObject == NULL) {
ret_val = -ENOMEM;
goto error_exit;
}
- if (halObject->mmuBase == 0) {
+ if (halObject->mmu0Base == 0 || halObject->mmu1Base == 0) {
ret_val = -ENOMEM;
GT_setFailureReason (curTrace,
GT_4CLASS,
"halObject->mmuBase is 0");
goto error_exit;
}
- mmuRegs = (VAYUDsp_MMURegs *)halObject->mmuBase;
+ mmuRegs0 = (VAYUDsp_MMURegs *)halObject->mmu0Base;
+ mmuRegs1 = (VAYUDsp_MMURegs *)halObject->mmu1Base;
+
+ /* Disable the MMU & TWL */
+ hw_mmu_disable(halObject->mmu0Base);
+ hw_mmu_twl_disable(halObject->mmu0Base);
/* Disable the MMU & TWL */
- hw_mmu_disable(halObject->mmuBase);
- hw_mmu_twl_disable(halObject->mmuBase);
+ hw_mmu_disable(halObject->mmu1Base);
+ hw_mmu_twl_disable(halObject->mmu1Base);
printf(" Programming Dsp memory regions\n");
printf("=========================================\n");
}
/* Set the TTB to point to the L1 page table's physical address */
- OUTREG32(&mmuRegs->TTB,
- ((struct pg_table_attrs *)(halObject->mmuObj.pPtAttrs))->l1_base_pa);
+ OUTREG32(&mmuRegs0->TTB,
+ ((struct pg_table_attrs *)(halObject->mmu0Obj.pPtAttrs))->l1_base_pa);
+ OUTREG32(&mmuRegs1->TTB,
+ ((struct pg_table_attrs *)(halObject->mmu1Obj.pPtAttrs))->l1_base_pa);
/* Enable the TWL */
- hw_mmu_twl_enable(halObject->mmuBase);
+ hw_mmu_twl_enable(halObject->mmu0Base);
+ hw_mmu_twl_enable(halObject->mmu1Base);
- hw_mmu_enable(halObject->mmuBase);
+ hw_mmu_enable(halObject->mmu0Base);
+ hw_mmu_enable(halObject->mmu1Base);
rproc_tlb_dump(halObject);
//Set the SYSCONFIG
- reg = INREG32(halObject->mmuBase + 0x10);
+ reg = INREG32(halObject->mmu0Base + 0x10);
reg&=0xFFFFFFEF;
reg|=0x11;
- OUTREG32(halObject->mmuBase+0x10, reg);
+ OUTREG32(halObject->mmu0Base+0x10, reg);
+
+ reg = INREG32(halObject->mmu1Base + 0x10);
+ reg&=0xFFFFFFEF;
+ reg|=0x11;
+ OUTREG32(halObject->mmu1Base+0x10, reg);
return 0;
error_exit:
*
*****************************************************/
-static Int rproc_set_twl (VAYUDSP_HalObject * halObject, Bool on)
+static Int rproc_set_twl (UInt32 mmuBase, Bool on)
{
Int status = 0;
VAYUDsp_MMURegs * mmuRegs = NULL;
ULONG reg;
- if (halObject == NULL) {
- status = -ENOMEM;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "benelli_set_twl",
- status,
- "halObject is NULL");
- }
- else if (halObject->mmuBase == 0) {
+ if (mmuBase == 0) {
status = -ENOMEM;
GT_setFailureReason (curTrace,
GT_4CLASS,
"benelli_set_twl",
status,
- "halObject->mmuBase is NULL");
+ "mmuBase is NULL");
}
else {
- mmuRegs = (VAYUDsp_MMURegs *)halObject->mmuBase;
+ mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
/* Setting MMU to Smart Idle Mode */
reg = INREG32(&mmuRegs->SYSCONFIG);
* All address & size arguments are assumed to be page aligned (in proc.c)
*
*/
-static Int rproc_mem_map (VAYUDSP_HalObject * halObject,
+static Int rproc_mem_map (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
UInt32 mpu_addr, UInt32 ul_virt_addr,
UInt32 num_bytes, UInt32 map_attr)
{
struct hw_mmu_map_attrs_t hw_attrs;
Int pg_i = 0;
- if (halObject == NULL) {
- status = -ENOMEM;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "benelli_mem_map",
- status,
- "halObject is NULL");
- }
- else if (halObject->mmuBase == 0) {
+ if (mmuBase == 0) {
status = -ENOMEM;
GT_setFailureReason (curTrace,
GT_4CLASS,
- "benelli_mem_map",
+ "rproc_mem_map",
status,
- "halObject->mmuBase is 0");
+ "mmuBase is 0");
}
else if (num_bytes == 0) {
status = -EINVAL;
GT_setFailureReason (curTrace,
GT_4CLASS,
- "benelli_mem_map",
+ "rproc_mem_map",
status,
"num_bytes is 0");
}
status = -EINVAL;
GT_setFailureReason (curTrace,
GT_4CLASS,
- "benelli_mem_map",
+ "rproc_mem_map",
status,
"MMU element size is zero");
}
if ((attrs & DSP_MAPPHYSICALADDR)) {
status = pte_update(mpu_addr, ul_virt_addr, num_bytes,
&hw_attrs,
- (struct pg_table_attrs *)halObject->mmuObj.pPtAttrs);
+ (struct pg_table_attrs *)p_pt_attrs);
}
/* Don't propogate Linux or HW status to upper layers */
* Roll out the mapped pages incase it failed in middle of
* mapping
*/
- if (pg_i)
- rproc_mem_unmap(halObject, ul_virt_addr,
+ if (pg_i) {
+ rproc_mem_unmap(mmuBase, p_pt_attrs, ul_virt_addr,
(pg_i * PAGE_SIZE));
+ }
}
/* In any case, flush the TLB
* This is called from here instead from pte_update to avoid
* unnecessary repetition while mapping non-contiguous physical
* regions of a virtual region */
- hw_mmu_tlb_flushAll(halObject->mmuBase);
+ hw_mmu_tlb_flushAll(mmuBase);
}
}
return status;
* So, instead of looking up the PTE address for every 4K block,
* we clear consecutive PTEs until we unmap all the bytes
*/
-static Int rproc_mem_unmap (VAYUDSP_HalObject * halObject,
+static Int rproc_mem_unmap (UInt32 mmuBase, struct pg_table_attrs * p_pt_attrs,
UInt32 da, UInt32 num_bytes)
{
UInt32 L1_base_va;
UInt32 temp;
UInt32 pAddr;
UInt32 numof4Kpages = 0;
- struct pg_table_attrs * p_pt_attrs = NULL;
- if (halObject == NULL) {
- status = -ENOMEM;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "rproc_mem_unmap",
- status,
- "halObject is NULL");
- }
- else if (halObject->mmuBase == 0) {
+ if (mmuBase == 0) {
status = -ENOMEM;
GT_setFailureReason (curTrace,
GT_4CLASS,
"rproc_mem_unmap",
status,
- "halObject->mmuBase is 0");
+ "mmuBase is 0");
}
- else if (halObject->mmuObj.pPtAttrs == NULL) {
+ else if (p_pt_attrs == NULL) {
status = -ENOMEM;
GT_setFailureReason (curTrace,
GT_4CLASS,
"rproc_mem_unmap",
status,
- "halObject->mmuObj.pPtAttrs is 0");
+ "p_pt_attrs is NULL");
}
else {
- p_pt_attrs = (struct pg_table_attrs *)halObject->mmuObj.pPtAttrs;
vaCurr = da;
rem_bytes = num_bytes;
rem_bytes_l2 = 0;
* get flushed
*/
EXIT_LOOP:
- hw_mmu_tlb_flushAll(halObject->mmuBase);
+ hw_mmu_tlb_flushAll(mmuBase);
return status;
}
UInt32 numMemEntries)
{
Int ret_val = 0;
- struct pg_table_attrs * p_pt_attrs = NULL;
+ struct pg_table_attrs * p_pt_attrs_0 = NULL;
+ struct pg_table_attrs * p_pt_attrs_1 = NULL;
- p_pt_attrs = init_mmu_page_attribs(0x10000, 14, 128);
- if (!p_pt_attrs) {
+ p_pt_attrs_0 = init_mmu_page_attribs(0x10000, 14, 128);
+ if (!p_pt_attrs_0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"rproc_setup",
"init_mmu_page_attribs failed");
}
else {
- halObject->mmuObj.pPtAttrs = p_pt_attrs;
- /* Disable TWL */
- ret_val = rproc_set_twl(halObject, FALSE);
- if (ret_val < 0) {
+ halObject->mmu0Obj.pPtAttrs = p_pt_attrs_0;
+ p_pt_attrs_1 = init_mmu_page_attribs(0x10000, 14, 128);
+ if (!p_pt_attrs_1) {
GT_setFailureReason (curTrace,
GT_4CLASS,
- "ipu_setup",
+ "rproc_setup",
ret_val,
- "benelli_set_twl to FALSE failed");
+ "init_mmu_page_attribs failed");
}
else {
- ret_val = rproc_mmu_init (halObject, memEntries,
- numMemEntries);
+ halObject->mmu1Obj.pPtAttrs = p_pt_attrs_1;
+
+ /* Disable TWL */
+ ret_val = rproc_set_twl(halObject->mmu0Base, FALSE);
if (ret_val < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"ipu_setup",
ret_val,
- "benelli_mmu_init failed");
+ "benelli_set_twl to FALSE failed");
}
else {
- ret_val = rproc_set_twl(halObject, TRUE);
+ ret_val = rproc_set_twl(halObject->mmu1Base, FALSE);
if (ret_val < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"ipu_setup",
ret_val,
- "ducati_set_twl to TRUE failed");
+ "benelli_set_twl to FALSE failed");
+ }
+ else {
+ ret_val = rproc_mmu_init (halObject, memEntries,
+ numMemEntries);
+ if (ret_val < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "ipu_setup",
+ ret_val,
+ "benelli_mmu_init failed");
+ }
+ else {
+ ret_val = rproc_set_twl(halObject->mmu0Base, TRUE);
+ if (ret_val < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "ipu_setup",
+ ret_val,
+ "ducati_set_twl to TRUE failed");
+ }
+ else {
+ ret_val = rproc_set_twl(halObject->mmu1Base, TRUE);
+ if (ret_val < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "ipu_setup",
+ ret_val,
+ "ducati_set_twl to TRUE failed");
+ }
+ }
+ }
}
}
}
}
if (ret_val < 0) {
- deinit_mmu_page_attribs(p_pt_attrs);
- halObject->mmuObj.pPtAttrs = NULL;
+ deinit_mmu_page_attribs(p_pt_attrs_0);
+ deinit_mmu_page_attribs(p_pt_attrs_1);
+ halObject->mmu0Obj.pPtAttrs = NULL;
+ halObject->mmu1Obj.pPtAttrs = NULL;
}
return ret_val;
{
shm_phys_addr_dsp = 0;
- if (halObject->mmuObj.pPtAttrs) {
- deinit_mmu_page_attribs(halObject->mmuObj.pPtAttrs);
- halObject->mmuObj.pPtAttrs = NULL;
+ if (halObject->mmu0Obj.pPtAttrs) {
+ deinit_mmu_page_attribs(halObject->mmu0Obj.pPtAttrs);
+ halObject->mmu0Obj.pPtAttrs = NULL;
+ }
+
+ if (halObject->mmu1Obj.pPtAttrs) {
+ deinit_mmu_page_attribs(halObject->mmu1Obj.pPtAttrs);
+ halObject->mmu1Obj.pPtAttrs = NULL;
}
}
-static Void iotlb_load_cr (VAYUDSP_HalObject * halObject,
- struct cr_regs *cr)
+static Void iotlb_load_cr (UInt32 mmuBase, struct cr_regs *cr)
{
ULONG reg;
- VAYUDsp_MMURegs * mmuRegs =
- (VAYUDsp_MMURegs *)halObject->mmuBase;
+ VAYUDsp_MMURegs * mmuRegs = (VAYUDsp_MMURegs *)mmuBase;
reg = cr->cam | MMU_CAM_V;
OUTREG32(&mmuRegs->CAM, reg);
* @obj: target iommu
* @e: an iommu tlb entry info
**/
-static Int load_iotlb_entry (VAYUDSP_HalObject * halObject,
- struct iotlb_entry *e)
+static Int load_iotlb_entry (UInt32 mmuBase, struct iotlb_entry *e)
{
Int err = 0;
struct iotlb_lock l;
struct cr_regs *cr;
- if (halObject == NULL) {
- err = -EINVAL;
- GT_setFailureReason (curTrace,
- GT_4CLASS,
- "load_iotlb_entry",
- err,
- "halObject is NULL");
- goto out;
- }
-
- if (halObject->mmuBase == NULL) {
+ if (mmuBase == NULL) {
err = -EINVAL;
GT_setFailureReason (curTrace,
GT_4CLASS,
"load_iotlb_entry",
err,
- "halObject->mmuBase is NULL");
+ "mmuBase is NULL");
goto out;
}
goto out;
}
- iotlb_getLock(halObject, &l);
+ iotlb_getLock(mmuBase, &l);
if (l.base == 32) {
err = -EBUSY;
goto out;
}
- iotlb_getLock(halObject, &l);
+ iotlb_getLock(mmuBase, &l);
} else {
l.vict = l.base;
- iotlb_setLock(halObject, &l);
+ iotlb_setLock(mmuBase, &l);
}
cr = iotlb_alloc_cr(e);
goto out;
}
- iotlb_load_cr(halObject, cr);
+ iotlb_load_cr(mmuBase, cr);
munmap(cr, sizeof(struct cr_regs));
if (e->prsvd)
/* increment victim for next tlb load */
if (++l.vict == 32)
l.vict = l.base;
- iotlb_setLock(halObject, &l);
+ iotlb_setLock(mmuBase, &l);
out:
return err;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c b/qnx/src/ipc3x_dev/ti/syslink/family/vayu/vayudsp/VAYUDspHalMmu.c
index e85d82c9125d9a8e30d8cdd6fb2d2b0bbfe5727c..47c92d6ae46ddabbf627dd154d2a9bfae61c2552 100644 (file)
*/
#define MMU_RAM_DEFAULT 0
+#define MPU_INT_OFFSET 32
+
/*!
* @brief Interrupt Id for DSP MMU faults
*/
-#define MMU_FAULT_INTERRUPT 60
+#define MMU_FAULT_INTR_DSP1_MMU0 60
+#define MMU_FAULT_INTR_DSP1_MMU1 143
+#define MMU_XBAR_INTR_DSP1_MMU1 145
/*!
* @brief CAM register field values
#define MMUPAGE_ALIGN(size, psz) (((size) + psz - 1) & ~(psz -1))
+/*!
+ * @brief offset in ctrl module to MMR LOCK reg.
+ */
+#define CTRL_MODULE_MMR_OFFSET 0x544
+
+/*!
+ * @brief offset in ctrl module to MPU INTs.
+ */
+#define CTRL_MODULE_MPU_OFFSET 0xA4C
+
+/*!
+ * @brief interrupt num at offset.
+ */
+#define CTRL_MODULE_INT_BASE 0x8
+
+/*!
+ * @brief interrupt num at offset.
+ */
+#define CTRL_MODULE_INT_m_OFFSET(m) CTRL_MODULE_MPU_OFFSET + \
+ ((((m) - CTRL_MODULE_INT_BASE) / 2) * 4) - \
+ (((m) > 131) ? 4 : 0)
+
/*!
* @def REG32
* @brief Regsiter access method.
_VAYUDSP_halMmuCheckAndClearFunc (Ptr arg)
{
VAYUDSP_HalObject * halObject = (VAYUDSP_HalObject *)arg;
- VAYUDSP_HalMmuObject * mmuObj = &(halObject->mmuObj);
+ VAYUDSP_HalMmuObject * mmuObj = &(halObject->mmu0Obj);
+ UInt32 mmuBase;
/* Check the interrupt status */
- mmuObj->mmuIrqStatus = REG32(halObject->mmuBase + MMU_MMU_IRQSTATUS_OFFSET);
+ mmuObj->mmuIrqStatus = REG32(halObject->mmu0Base + MMU_MMU_IRQSTATUS_OFFSET);
mmuObj->mmuIrqStatus &= MMU_IRQ_MASK;
- if (!(mmuObj->mmuIrqStatus))
- return (FALSE);
+ if (!(mmuObj->mmuIrqStatus)) {
+ mmuObj = &(halObject->mmu1Obj);
+
+ /* Check the interrupt status */
+ mmuObj->mmuIrqStatus = REG32(halObject->mmu1Base + MMU_MMU_IRQSTATUS_OFFSET);
+ mmuObj->mmuIrqStatus &= MMU_IRQ_MASK;
+ if (!(mmuObj->mmuIrqStatus)) {
+ return (FALSE);
+ }
+ else {
+ mmuBase = halObject->mmu1Base;
+ GT_0trace (curTrace, GT_4CLASS,
+ "****************** DSP-MMU1 Fault ******************");
+ }
+ }
+ else {
+ mmuBase = halObject->mmu0Base;
+ GT_0trace (curTrace, GT_4CLASS,
+ "****************** DSP-MMU0 Fault ******************");
+ }
/* Get the fault address. */
- mmuObj->mmuFaultAddr = REG32(halObject->mmuBase + MMU_MMU_FAULT_AD_OFFSET);
+ mmuObj->mmuFaultAddr = REG32(mmuBase + MMU_MMU_FAULT_AD_OFFSET);
/* Print the fault information */
- GT_0trace (curTrace, GT_4CLASS,
- "****************** DSP-MMU Fault ******************");
GT_1trace (curTrace, GT_4CLASS,
"**** addr: 0x%x", mmuObj->mmuFaultAddr);
if (mmuObj->mmuIrqStatus & MMU_IRQ_TLBMISS)
"**************************************************");
/* Clear the interrupt and disable further interrupts. */
- REG32(halObject->mmuBase + MMU_MMU_IRQENABLE_OFFSET) = 0x0;
- REG32(halObject->mmuBase + MMU_MMU_IRQSTATUS_OFFSET) = mmuObj->mmuIrqStatus;
+ REG32(mmuBase + MMU_MMU_IRQENABLE_OFFSET) = 0x0;
+ REG32(mmuBase + MMU_MMU_IRQSTATUS_OFFSET) = mmuObj->mmuIrqStatus;
/* This is not a shared interrupt, so interrupt has always occurred */
/*! @retval TRUE Interrupt has occurred. */
ProcMgr_AddrInfo * memTable)
{
Int status = PROCESSOR_SUCCESS;
- VAYUDSP_HalMmuObject * mmuObj;
+ VAYUDSP_HalMmuObject * mmu0Obj, *mmu1Obj;
OsalIsr_Params isrParams;
+ UInt32 reg = 0;
GT_3trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuEnable",
halObject, numMemEntries, memTable);
* configure any default regions.
* memTable may also be NULL.
*/
- mmuObj = &(halObject->mmuObj);
+ mmu0Obj = &(halObject->mmu0Obj);
+ mmu1Obj = &(halObject->mmu1Obj);
+
+ /* Program the MMR lock registers to access the SCM
+ * IRQ crossbar register address range */
+ REG32(halObject->ctrlModBase + CTRL_MODULE_MMR_OFFSET) = 0xF757FDC0;
+
+ /* Program the IntXbar */
+ reg = REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1));
+ if ((MMU_FAULT_INTR_DSP1_MMU1 - CTRL_MODULE_INT_BASE) % 2) {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
+ (reg & 0x0000FFFF) | (MMU_XBAR_INTR_DSP1_MMU1 << 16);
+ }
+ else {
+ REG32(halObject->ctrlModBase + CTRL_MODULE_INT_m_OFFSET(MMU_FAULT_INTR_DSP1_MMU1)) =
+ (reg & 0xFFFF0000) | (MMU_XBAR_INTR_DSP1_MMU1);
+ }
/* Create the ISR to listen for MMU Faults */
isrParams.sharedInt = FALSE;
isrParams.checkAndClearFxn = &_VAYUDSP_halMmuCheckAndClearFunc;
isrParams.fxnArgs = halObject;
- isrParams.intId = MMU_FAULT_INTERRUPT;
- mmuObj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
+ isrParams.intId = MMU_FAULT_INTR_DSP1_MMU0;
+ mmu0Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
+ halObject,
+ &isrParams);
+ isrParams.intId = MMU_FAULT_INTR_DSP1_MMU1;
+ mmu1Obj->isrHandle = OsalIsr_create (&_VAYUDSP_halMmuInt_isr,
halObject,
&isrParams);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
- if (mmuObj->isrHandle == NULL) {
+ if (mmu0Obj->isrHandle == NULL || mmu1Obj->isrHandle == NULL) {
/*! @retval PROCESSOR_E_FAIL OsalIsr_create failed */
status = PROCESSOR_E_FAIL;
GT_setFailureReason (curTrace,
else {
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
- status = OsalIsr_install (mmuObj->isrHandle);
+ status = OsalIsr_install (mmu0Obj->isrHandle);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
status,
"OsalIsr_install failed");
}
+ else {
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+
+ status = OsalIsr_install (mmu1Obj->isrHandle);
+
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_VAYUDSP_halMmuEnable",
+ status,
+ "OsalIsr_install failed");
+ }
+ }
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
if ((status >= 0) && (numMemEntries != 0)) {
{
Int status = PROCESSOR_SUCCESS;
Int tmpStatus = PROCESSOR_SUCCESS;
- VAYUDSP_HalMmuObject * mmuObj;
+ VAYUDSP_HalMmuObject * mmu0Obj, *mmu1Obj;
GT_1trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuDisable", halObject);
GT_assert (curTrace, (halObject != NULL));
- mmuObj = &(halObject->mmuObj);
+ mmu0Obj = &(halObject->mmu0Obj);
+ mmu1Obj = &(halObject->mmu1Obj);
- status = OsalIsr_uninstall (mmuObj->isrHandle);
+ status = OsalIsr_uninstall (mmu0Obj->isrHandle);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
GT_setFailureReason (curTrace,
}
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ status = OsalIsr_uninstall (mmu1Obj->isrHandle);
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ if (status < 0) {
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_VAYUDSP_halMmuDisable",
+ status,
+ "OsalIsr_uninstall failed");
+ }
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ tmpStatus =
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+ OsalIsr_delete (&(mmu0Obj->isrHandle));
+#if !defined(SYSLINK_BUILD_OPTIMIZE)
+ if ((status >= 0) && (tmpStatus < 0)) {
+ status = tmpStatus;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_VAYUDSP_halMmuDisable",
+ status,
+ "OsalIsr_delete failed");
+ }
+#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
+
#if !defined(SYSLINK_BUILD_OPTIMIZE)
tmpStatus =
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
- OsalIsr_delete (&(mmuObj->isrHandle));
+ OsalIsr_delete (&(mmu1Obj->isrHandle));
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if ((status >= 0) && (tmpStatus < 0)) {
status = tmpStatus;
UInt32 * iopgd = NULL;
UInt32 currentEntrySize;
VAYUDSP_HalMmuEntryInfo currentEntry;
- VAYUDSP_HalMmuObject * mmuObj;
+ VAYUDSP_HalMmuObject * mmu0Obj, *mmu1Obj;
//UInt32 clearBytes = 0;
GT_2trace (curTrace, GT_ENTER, "_VAYUDSP_halMmuDeleteEntry",
GT_assert (curTrace, (entry != NULL));
GT_assert (curTrace, (entry->size != 0));
- mmuObj = &(halObject->mmuObj);
+ mmu0Obj = &(halObject->mmu0Obj);
+ mmu1Obj = &(halObject->mmu1Obj);
/* Add the entry (or entries) */
Memory_copy(¤tEntry,
_VAYUDSP_halMmuPteSet (VAYUDSP_HalObject * halObject,
VAYUDSP_HalMmuEntryInfo* setPteInfo)
{
- VAYUDSP_HalMmuObject * mmuObj;
+ VAYUDSP_HalMmuObject * mmu0Obj, *mmu1Obj;
struct iotlb_entry tlb_entry;
Int status = PROCESSOR_SUCCESS;
GT_assert (curTrace, (halObject != NULL));
GT_assert (curTrace, (setPteInfo != NULL));
- mmuObj = &(halObject->mmuObj);
- GT_assert(curTrace, (mmuObj != NULL));
+ mmu0Obj = &(halObject->mmu0Obj);
+ GT_assert(curTrace, (mmu0Obj != NULL));
+ mmu1Obj = &(halObject->mmu1Obj);
+ GT_assert(curTrace, (mmu1Obj != NULL));
switch (setPteInfo->size) {
case PAGE_SIZE_16MB:
tlb_entry.da = setPteInfo->slaveVirtAddr;
tlb_entry.pa = setPteInfo->masterPhyAddr;
- if (VAYUDSP_InternalMMU_PteSet(halObject->mmuBase, &tlb_entry)){
+ if (VAYUDSP_InternalMMU_PteSet(halObject->mmu0Base, &tlb_entry)){
+ status = PROCESSOR_E_STOREENTERY;
+ GT_setFailureReason (curTrace,
+ GT_4CLASS,
+ "_VAYUDSP_halMmuPteSet",
+ status,
+ "iopgtable_store_entry failed!");
+ }
+ if (VAYUDSP_InternalMMU_PteSet(halObject->mmu1Base, &tlb_entry)){
status = PROCESSOR_E_STOREENTERY;
GT_setFailureReason (curTrace,
GT_4CLASS,
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspHal.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspHal.h
index 2f971f5dc5d4ab372aa0da6cbbf10e6862891cc7..cc2fbfe1f57c12fb9f98804c1ff2931e2ca65dfa 100644 (file)
/*!< Virtual base address of the General Control module. */
UInt32 bootStatBase;
/*!< Virtual base address of the General Control module. */
- UInt32 mmuBase;
+ UInt32 mmu0Base;
+ /*!< Base address of the MMU module. */
+ UInt32 mmu1Base;
/*!< Base address of the MMU module. */
UInt32 mmuSysBase;
/*!< Base address of the MMU module. */
/*!< Base address of the control module. */
UInt32 procId;
/*!< Processor ID. */
- VAYUDSP_HalMmuObject mmuObj;
+ VAYUDSP_HalMmuObject mmu0Obj;
+ /*!< MMU abstraction. */
+ VAYUDSP_HalMmuObject mmu1Obj;
/*!< MMU abstraction. */
} VAYUDSP_HalObject;
diff --git a/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h b/qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h
index eb2bb6142d3dbc959d0a070526900dd572d3d522..5ce2cd7bc6a72cb6f33f0c7de699a8833ed5cb43 100644 (file)
*/
#define DSP_SYS_MMU_CONFIG_SIZE 0x1000
-#define MMU_BASE 0x40D01000
+#define MMU0_BASE 0x40D01000
/*!
* @brief size to be ioremapped.
*/
-#define MMU_SIZE 0x1000
+#define MMU0_SIZE 0x1000
+
+#define MMU1_BASE 0x40D02000
+/*!
+ * @brief size to be ioremapped.
+ */
+#define MMU1_SIZE 0x1000
/*!
* @def CTRL_MODULE_BASE