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raw | patch | inline | side by side (parent: 0756d19)
raw | patch | inline | side by side (parent: 0756d19)
| author | Sam Nelson <sam.nelson@ti.com> | |
| Sun, 21 Oct 2018 20:41:25 +0000 (16:41 -0400) | ||
| committer | Sam Nelson <sam.nelson@ti.com> | |
| Tue, 23 Oct 2018 01:22:08 +0000 (21:22 -0400) |
Add code to build separate test images for R5F0, R5F1.
R5F0 images can be used AS-IS with R5F cores in Lock step mode
Note the DDR memory is partitioned according to the Linux device tree
nodes for r5f-0 and r5f-1
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
R5F0 images can be used AS-IS with R5F cores in Lock step mode
Note the DDR memory is partitioned according to the Linux device tree
nodes for r5f-0 and r5f-1
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
| ipc-bios.bld | patch | blob | history | |
| packages/ti/ipc/tests/R5FLink.cmd | patch | blob | history | |
| packages/ti/ipc/tests/R5FLink1.cmd | [new file with mode: 0644] | patch | blob |
| packages/ti/ipc/tests/R5f1_mpu_am65xx.cfg | [new file with mode: 0644] | patch | blob |
| packages/ti/ipc/tests/R5fmpu_am65xx.cfg | patch | blob | history | |
| packages/ti/ipc/tests/messageq_common.cfg.xs | patch | blob | history | |
| packages/ti/ipc/tests/package.bld | patch | blob | history | |
| packages/ti/ipc/tests/ping_rpmsg_common.cfg.xs | patch | blob | history |
diff --git a/ipc-bios.bld b/ipc-bios.bld
index bae3eacb69919d02ecab7d6f5ac0f0206910fb54..d5567854c0d9127393dd82f59b12af054a9e816f 100644 (file)
--- a/ipc-bios.bld
+++ b/ipc-bios.bld
if (targetName.match(/elf\.R5F$/)) {
switch (platform) {
case 'AM65XX':
- target.platforms.$add("ti.platforms.cortexR:AM65X");
+ target.platforms.$add("ti.platforms.cortexR:AM65X:false:R5F0");
+ target.platforms.$add("ti.platforms.cortexR:AM65X:false:R5F1");
break;
default:
index 97a69efd2c0d08f99f9743ce06df358a077ef1de..6921f538cfc2cd9a96087adbe9d290773c12835a 100644 (file)
* 9C17_0000 ???7_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
*/
-#define EXT_CODE_BASE 0x9C200000
-#define EXT_DATA_BASE 0x9C300000
-#define RAM0_ADDR 0x41C00000
#define ATCM_START 0x00000000
+#define BTCM_START 0x41010000
+#define RAM0_ADDR 0x41C00000
+
+#define EXT_BASE 0x9C000000
-e __VECS_ENTRY_POINT
MEMORY{
- ATCM (RWX) : origin=ATCM_START, length=0x00008000
- BTCM (RWX) : origin=0x41010000, length=0x00008000
- RAM0 (RW) : origin=RAM0_ADDR length=0x00080000
- EXT_CODE (RWX) : origin=EXT_CODE_BASE length=0x00100000
- EXT_DATA (RW) : origin=EXT_DATA_BASE length=0x00100000
- EXT_HEAP (RW) : origin=0x9C400000 length=0x00300000
- TRACE_BUF (RW) : origin=0x9C100000 length=0x00060000
- EXC_DATA (RW) : origin=0x9C160000 length=0x00010000
- PM_DATA (RW) : origin=0x9C170000 length=0x00020000
+ ATCM (RWX) : origin=ATCM_START length=0x00008000
+ BTCM (RWX) : origin=BTCM_START length=0x00008000
+ RAM0 (RW) : origin=RAM0_ADDR length=0x00080000
+ DMA_REGION (RW) : origin=EXT_BASE length=0x00100000
+ TRACE_BUF (RW) : origin=(EXT_BASE+0x100000) length=0x00080000
+ RSRC_TABLE (RW) : origin=(EXT_BASE+0x180000) length=0x00080000
+ EXT_CODE (RWX) : origin=(EXT_BASE+0x200000) length=0x00100000
+ EXT_DATA (RW) : origin=(EXT_BASE+0x300000) length=0x00100000
+ EXT_HEAP (RW) : origin=(EXT_BASE+0x400000) length=0x00300000
+
}
/*----------------------------------------------------------------------------*/
*(.text:ti_sysbios_family_arm_v7r_Cache_*)
*(.text:xdc_runtime_Startup_reset*)
} > ATCM
+
.resource_table : {
__RESOURCE_TABLE = .;
- } > EXT_DATA_BASE
+ } > RSRC_TABLE
.tracebuf : {} > TRACE_BUF
}
diff --git a/packages/ti/ipc/tests/R5FLink1.cmd b/packages/ti/ipc/tests/R5FLink1.cmd
--- /dev/null
@@ -0,0 +1,72 @@
+/*----------------------------------------------------------------------------*/
+/* R5FLink.cmd */
+/* */
+/* (c) Texas Instruments 2017-2018, All rights reserved. */
+/* */
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+--retain="*(.intvecs)"
+--retain="*(.intvecsNew)"
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+
+/* Memory Map for AM65X platform
+ *
+ * --- External Memory ---
+ * Virtual Physical Size Comment
+ * ------------------------------------------------------------------------
+ * 9C20_0000 ???0_0000 10_0000 ( 1 MB) EXT_CODE
+ * 9C30_0000 ???0_0000 10_0000 ( 2 MB) EXT_DATA
+ * 9C40_0000 ???0_0000 30_0000 ( 3 MB) EXT_HEAP
+ * 9C10_0000 ???0_0000 6_0000 ( 384 kB) TRACE_BUF
+ * 9C16_0000 ???6_0000 1_0000 ( 64 kB) EXC_DATA
+ * 9C17_0000 ???7_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
+ */
+
+#define ATCM_START 0x00000000
+#define BTCM_START 0x41010000
+#define RAM0_ADDR 0x41C00000
+
+#define EXT_BASE 0x9B000000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY{
+ ATCM (RWX) : origin=ATCM_START length=0x00008000
+ BTCM (RWX) : origin=BTCM_START length=0x00008000
+ RAM0 (RW) : origin=RAM0_ADDR length=0x00080000
+ DMA_REGION (RW) : origin=EXT_BASE length=0x00100000
+ TRACE_BUF (RW) : origin=(EXT_BASE+0x100000) length=0x00080000
+ RSRC_TABLE (RW) : origin=(EXT_BASE+0x180000) length=0x00080000
+ EXT_CODE (RWX) : origin=(EXT_BASE+0x200000) length=0x00100000
+ EXT_DATA (RW) : origin=(EXT_BASE+0x300000) length=0x00100000
+ EXT_HEAP (RW) : origin=(EXT_BASE+0x400000) length=0x00300000
+
+}
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+SECTIONS{
+ .vecs : {
+ __VECS_ENTRY_POINT = .;
+ } > ATCM_START
+
+ .init_text : {
+ boot.*(.text)
+ *(.text:ti_sysbios_family_arm_MPU_*)
+ *(.text:ti_sysbios_family_arm_v7r_Cache_*)
+ *(.text:xdc_runtime_Startup_reset*)
+ } > ATCM
+
+ .resource_table : {
+ __RESOURCE_TABLE = .;
+ } > RSRC_TABLE
+
+ .tracebuf : {} > TRACE_BUF
+}
+/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/ipc/tests/R5f1_mpu_am65xx.cfg b/packages/ti/ipc/tests/R5f1_mpu_am65xx.cfg
--- /dev/null
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2017-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+ Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+ Strongly Ordered & Shareable */
+attrs.tex = 0;
+attrs.cacheable = false;
+attrs.bufferable = false;
+attrs.shareable = true;
+/*--------------------------------------------------------------*/
+attrs.noExecute = true;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true
+/* The following 4 lines set the memory to be
+ Outer and Inner write-back, write-allocate & Shareable */
+attrs.tex = 1;
+attrs.cacheable = true;
+attrs.bufferable = true;
+attrs.shareable = false;
+/*--------------------------------------------------------------*/
+attrs.noExecute = false;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+ Outer and Inner write-back, write-allocate & not shareable */
+attrs.tex = 1;
+attrs.cacheable = true;
+attrs.bufferable = true;
+attrs.shareable = false;
+/*--------------------------------------------------------------*/
+attrs.noExecute = false;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+ Outer and Inner write-back, write-allocate & not shareable */
+attrs.tex = 1;
+attrs.cacheable = true;
+attrs.bufferable = true;
+attrs.shareable = false;
+/*--------------------------------------------------------------*/
+attrs.noExecute = false;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+ Outer and Inner write-back, write-allocate & not shareable */
+attrs.tex = 1;
+attrs.cacheable = true;
+attrs.bufferable = true;
+attrs.shareable = false;
+/*--------------------------------------------------------------*/
+attrs.noExecute = false;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_512K, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+ Outer and Inner write-back, write-allocate & not shareable */
+attrs.tex = 1;
+attrs.cacheable = true;
+attrs.bufferable = true;
+attrs.shareable = false; /* NOTE: Setting it true will make it non-cacheable */
+/*--------------------------------------------------------------*/
+attrs.noExecute = true;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_512K, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+ Outer and Inner write-back, write-allocate & shareable */
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false; /* NOTE: Setting it true will make it non-cacheable */
+attrs.tex = 1;
+/*--------------------------------------------------------------*/
+attrs.noExecute = false;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x9B000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+/* The following 4 lines set the memory to be
+ Outer and Inner write-back, write-allocate & shareable */
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = true; /* NOTE: Setting it true will make it non-cacheable */
+attrs.tex = 1;
+
+/*--------------------------------------------------------------*/
+attrs.noExecute = false;
+//attrs.accPerm = 1; /* RW at PL1 */
+attrs.accPerm = 0x3; /* RW at PL1 & 2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0x9B000000, MPU.RegionSize_2M, attrs);
index 00b2446837179ef5670f34bcd982f34fe85c9ccf..db94b6042bf9c39f156fcef9e6f3e2ec95ec70c4 100644 (file)
/*
- * Copyright (c) 2017, Texas Instruments Incorporated
+ * Copyright (c) 2017-2018, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
attrs.cacheable = true;
attrs.shareable = false; /* NOTE: Setting it true will make it non-cacheable */
attrs.tex = 1;
-
/*--------------------------------------------------------------*/
attrs.noExecute = false;
//attrs.accPerm = 1; /* RW at PL1 */
attrs.accPerm = 0x3; /* RW at PL1 & 2 */
attrs.tex = 1;
attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(7, 0x9C000000, MPU.RegionSize_1M, attrs);
+MPU.setRegionMeta(7, 0x9C000000, MPU.RegionSize_2M, attrs);
diff --git a/packages/ti/ipc/tests/messageq_common.cfg.xs b/packages/ti/ipc/tests/messageq_common.cfg.xs
index 90222ec05ef8eea5f340e1f41f5d3c866c9559d1..723a7589780a57ffa9c57927edf5131af7b888d4 100644 (file)
Diags.ALWAYS_ON);
*/
}
-else if (Program.platformName.match(/^ti\.platforms\.cortexR:AM65X/) &&
+else if (Program.platformName.match(/^ti\.platforms\.cortexR\:AM65X/) &&
Program.cpu.attrs.cpuCore.match(/^R5$/)) {
print("messageq_common.cfg.xs cpuCore:" + Program.cpu.attrs.cpuCore);
Resource.loadSymbol = "__RESOURCE_TABLE";
var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
- MultiProc.setConfig("R5F-0", ["HOST", "R5F-0", "R5F-1"]);
xdc.loadPackage('ti.sdo.ipc.family.am65xx');
xdc.useModule('ti.sdo.ipc.family.am65xx.InterruptR5f');
xdc.useModule('ti.sysbios.xdcruntime.GateThreadSupport');
var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
- xdc.loadCapsule("R5fmpu_am65xx.cfg");
var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
/* TODO: Need to check on equivalent for K3 */
/* Add idle function */
xdc.useModule('ti.sdo.ipc.family.am65xx.Power');
Idle.addFunc('&Power_Idle');
+ var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+
+ if (Program.platformName.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/)) {
+ xdc.loadCapsule("R5fmpu_am65xx.cfg");
+ MultiProc.setConfig("R5F-0", ["HOST", "R5F-0", "R5F-1"]);
+ Core.id = 0;
+ Clock.timerId = 0;
+ } else if (Program.platformName.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/)) {
+ xdc.loadCapsule("R5f1_mpu_am65xx.cfg");
+ MultiProc.setConfig("R5F-1", ["HOST", "R5F-0", "R5F-1"]);
+ Core.id = 1;
+ Clock.timerId = 1;
+ }
}
else {
index 15039154045fce95ef66545c3081619ad71ce2a8..a20db1c741d5888e13f970ad4de5587e2cde97f3 100644 (file)
/* Note the EXT_CODE and EXT_DATA sections are specified in the
Linker command file
*/
-Build.platformTable["ti.platforms.cortexR:AM65X"] = {
+Build.platformTable["ti.platforms.cortexR:AM65X:false:R5F0"] = {
+
+ codeMemory : "EXT_CODE",
+ dataMemory : "EXT_DATA",
+ stackMemory: "EXT_DATA",
+};
+
+Build.platformTable["ti.platforms.cortexR:AM65X:false:R5F1"] = {
codeMemory : "EXT_CODE",
dataMemory : "EXT_DATA",
cfgScript: "gatempapp",
defs: "-D DSP_1" + extraDefs
}).addObjects(["messageq_fault.c"]);
- } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X/) &&
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/) &&
(targ.isa == "v7R")) {
Pkg.addExecutable(name + "/messageq_fault", targ, platform, {
cfgScript: "rpmsg_transport",
- defs: extraDefs,
+ defs: " -DAM65X_R5F_0" + extraDefs,
lopts: "-l R5FLink.cmd",
}).addObjects(["messageq_fault.c"]);
+
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/) &&
+ (targ.isa == "v7R")) {
+ Pkg.addExecutable(name + "/messageq_fault", targ, platform, {
+ cfgScript: "rpmsg_transport",
+ defs: " -DAM65X_R5F_1" + extraDefs,
+ lopts: "-l R5FLink1.cmd",
+ }).addObjects(["messageq_fault.c"]);
+
} else {
Pkg.addExecutable(name + "/messageq_fault", targ, platform, {
cfgScript: "rpmsg_transport",
}
/* ping_rpmsg */
- if (platform.match(/^ti\.platforms\.cortexR\:AM65X/) &&
+ if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/) &&
(targ.isa == "v7R")) {
Pkg.addExecutable(name + "/ping_rpmsg", targ, platform, {
cfgScript: "ping_rpmsg",
- defs: extraDefs,
+ defs: " -DAM65X_R5F_0" + extraDefs,
lopts: "-l R5FLink.cmd",
}).addObjects(["ping_rpmsg.c"]);
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/) &&
+ (targ.isa == "v7R")) {
+ Pkg.addExecutable(name + "/ping_rpmsg", targ, platform, {
+ cfgScript: "ping_rpmsg",
+ defs: " -DAM65X_R5F_1" + extraDefs,
+ lopts: "-l R5FLink1.cmd",
+ }).addObjects(["ping_rpmsg.c"]);
+
} else {
Pkg.addExecutable(name + "/ping_rpmsg", targ, platform, {
cfgScript: "ping_rpmsg",
}
/* ping_tasks */
- if (platform.match(/^ti\.platforms\.cortexR\:AM65X/) &&
+ if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/) &&
(targ.isa == "v7R")) {
Pkg.addExecutable(name + "/ping_tasks", targ, platform, {
cfgScript: "ping_rpmsg",
- defs: extraDefs,
+ defs: " -DAM65X_R5F_0" + extraDefs,
lopts: "-l R5FLink.cmd",
}).addObjects(["ping_tasks.c", "ping_tasks_main.c"]);
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/) &&
+ (targ.isa == "v7R")) {
+ Pkg.addExecutable(name + "/ping_tasks", targ, platform, {
+ cfgScript: "ping_rpmsg",
+ defs: " -DAM65X_R5F_1" + extraDefs,
+ lopts: "-l R5FLink1.cmd",
+ }).addObjects(["ping_tasks.c", "ping_tasks_main.c"]);
+
} else {
Pkg.addExecutable(name + "/ping_tasks", targ, platform, {
cfgScript: "ping_rpmsg",
}
/* messageq_multi */
- if (platform.match(/^ti\.platforms\.cortexR\:AM65X/) &&
+ if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/) &&
(targ.isa == "v7R")) {
Pkg.addExecutable(name + "/messageq_multi", targ, platform, {
cfgScript: "rpmsg_transport",
- defs: "-D BENCHMARK" + extraDefs,
+ defs: "-D BENCHMARK -DAM65X_R5F_0" + extraDefs,
lopts: "-l R5FLink.cmd",
}).addObjects(["messageq_multi.c"]);
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/) &&
+ (targ.isa == "v7R")) {
+ Pkg.addExecutable(name + "/messageq_multi", targ, platform, {
+ cfgScript: "rpmsg_transport",
+ defs: "-D BENCHMARK -DAM65X_R5F_1" + extraDefs,
+ lopts: "-l R5FLink1.cmd",
+ }).addObjects(["messageq_multi.c"]);
+
} else {
Pkg.addExecutable(name + "/messageq_multi", targ, platform, {
cfgScript: "rpmsg_transport",
}
/* messageq_multimulti */
- if (platform.match(/^ti\.platforms\.cortexR\:AM65X/) &&
+ if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/) &&
(targ.isa == "v7R")) {
Pkg.addExecutable(name + "/messageq_multimulti", targ, platform, {
cfgScript: "rpmsg_transport",
- defs: "-D BENCHMARK" + extraDefs,
+ defs: "-D BENCHMARK -DAM65X_R5F_0" + extraDefs,
lopts: "-l R5FLink.cmd",
}).addObjects(["messageq_multimulti.c"]);
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/) &&
+ (targ.isa == "v7R")) {
+ Pkg.addExecutable(name + "/messageq_multimulti", targ, platform, {
+ cfgScript: "rpmsg_transport",
+ defs: "-D BENCHMARK -DAM65X_R5F_1" + extraDefs,
+ lopts: "-l R5FLink1.cmd",
+ }).addObjects(["messageq_multimulti.c"]);
+
} else {
Pkg.addExecutable(name + "/messageq_multimulti", targ, platform, {
cfgScript: "rpmsg_transport",
cfgScript: "rpmsg_transport",
defs: "-D BENCHMARK -D IPU" + extraDefs
}).addObjects(["messageq_single.c"]);
- } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X/) &&
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/) &&
(targ.isa == "v7R")) {
Pkg.addExecutable(name + "/messageq_single", targ, platform, {
cfgScript: "rpmsg_transport",
- defs: "-D BENCHMARK " + extraDefs,
+ defs: "-D BENCHMARK -DAM65X_R5F_0" + extraDefs,
lopts: "-l R5FLink.cmd",
}).addObjects(["messageq_single.c" ]);
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/) &&
+ (targ.isa == "v7R")) {
+ Pkg.addExecutable(name + "/messageq_single", targ, platform, {
+ cfgScript: "rpmsg_transport",
+ defs: "-D BENCHMARK -DAM65X_R5F_1" + extraDefs,
+ lopts: "-l R5FLink1.cmd",
+ }).addObjects(["messageq_single.c" ]);
+
} else {
Pkg.addExecutable(name + "/messageq_single", targ, platform, {
cfgScript: "rpmsg_transport",
/* TODO: NameServerApp.xe66 too big for K2E's 512 KB L2SRAM */
if (!platform.match(/^ti.platforms.evmC66AK2E/)) {
/* NameServerApp */
- if (platform.match(/^ti\.platforms\.cortexR\:AM65X/) &&
+ if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/) &&
+ (targ.isa == "v7R")) {
+ Pkg.addExecutable(name + "/NameServerApp", targ, platform, {
+ cfgScript: "nameserverapp",
+ defs: " -DAM65X_R5F_0",
+ lopts: "-l R5FLink.cmd",
+ }).addObjects(["NameServerApp.c"]);
+ } else if (platform.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/) &&
(targ.isa == "v7R")) {
Pkg.addExecutable(name + "/NameServerApp", targ, platform, {
cfgScript: "nameserverapp",
+ defs: " -DAM65X_R5F_1",
lopts: "-l R5FLink.cmd",
}).addObjects(["NameServerApp.c"]);
} else {
diff --git a/packages/ti/ipc/tests/ping_rpmsg_common.cfg.xs b/packages/ti/ipc/tests/ping_rpmsg_common.cfg.xs
index a115533d933d5881bbee6cfa0b736b890e755509..de7c3245fa1a2b1f04f2bc2f49e376cbcf43f2ae 100644 (file)
Resource.loadSymbol = "__RESOURCE_TABLE";
var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
- MultiProc.setConfig("R5F-0", ["HOST", "R5F-0", "R5F-1"]);
-
- xdc.loadCapsule("R5fmpu_am65xx.cfg");
var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
/* TODO: Need to check on equivalent for K3 */
xdc.useModule('ti.sdo.ipc.family.am65xx.Power');
Idle.addFunc('&Power_Idle');
+ var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+ var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+
+ if (Program.platformName.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F0/)) {
+ xdc.loadCapsule("R5fmpu_am65xx.cfg");
+ MultiProc.setConfig("R5F-0", ["HOST", "R5F-0", "R5F-1"]);
+ Core.id = 0;
+ Clock.timerId = 0;
+ } else if (Program.platformName.match(/^ti\.platforms\.cortexR\:AM65X\:false\:R5F1/)) {
+ xdc.loadCapsule("R5f1_mpu_am65xx.cfg");
+ MultiProc.setConfig("R5F-1", ["HOST", "R5F-0", "R5F-1"]);
+ Core.id = 1;
+ Clock.timerId = 1;
+ }
+
}else {
throw("ping_rpmsg_common.cfg: Did not match any platform!"
+ " platform:" + Program.platformName + "cpuCore:"