Add support for watchdog timers for DSP1 and IPU1 in QNX
authorvwan@ti.com <vwan@ti.com>
Tue, 31 Mar 2015 19:59:33 +0000 (12:59 -0700)
committerRobert Tivy <rtivy@ti.com>
Fri, 17 Apr 2015 22:16:49 +0000 (15:16 -0700)
This commit refactors the code that manages the GP Timers to allow more
timers to be used as watchdog timers. Namely, interrupts from timers
7, 8 and 10 all trigger recovery, being used as watchdog timers for IPU1
and DSP1.

The list of watchdog timers to CPU assignment can now be configured in
qnx/src/cfg/dra7xx/GptCfg.c.

Signed-off-by: VW <vwan@ti.com>
qnx/src/cfg/dra7xx/GptCfg.c [new file with mode: 0644]
qnx/src/ipc3x_dev/ti/syslink/build/Qnx/resmgr/common.mk
qnx/src/ipc3x_dev/ti/syslink/family/vayu/Gpt.c [moved from qnx/src/ipc3x_dev/ti/syslink/family/vayu/gptimers.c with 55% similarity]
qnx/src/ipc3x_dev/ti/syslink/family/vayu/Gpt.h [moved from qnx/src/ipc3x_dev/ti/syslink/family/vayu/gptimers.h with 71% similarity]
qnx/src/ipc3x_dev/ti/syslink/family/vayu/Platform.c
qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/Ipc.c

diff --git a/qnx/src/cfg/dra7xx/GptCfg.c b/qnx/src/cfg/dra7xx/GptCfg.c
new file mode 100644 (file)
index 0000000..6eea911
--- /dev/null
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*============================================================================
+ *  @file   GptCfg.c
+ *
+ *  @brief  GP Timer configuration
+ */
+
+#include <ti/ipc/Std.h>
+#include <Gpt.h>
+
+/*
+ *  ======== ti_ipc_Gpt_cfg ========
+ *  The GP Timer configuration object
+ */
+Gpt_Config ti_ipc_Gpt_cfg = {
+    /* List the processor that uses each timer as a watchdog timer */
+    .wdtOwnerProcessor   = {
+        NULL,     /* GPT_TIMER_1 */
+        NULL,     /* GPT_TIMER_2 */
+        NULL,     /* GPT_TIMER_3 */
+        "IPU2",   /* GPT_TIMER_4 */
+        NULL,     /* GPT_TIMER_5 */
+        NULL,     /* GPT_TIMER_6 */
+        "IPU1",   /* GPT_TIMER_7 */
+        "IPU1",   /* GPT_TIMER_8 */
+        "IPU2",   /* GPT_TIMER_9 */
+        "DSP1",   /* GPT_TIMER_10 */
+        NULL      /* GPT_TIMER_11 */
+    }
+};
index c87cfadf1af32c279cf78e3765d41cbb8eeb17bf..f95cef0170f5d90daeae68b254a10a870615dcb0 100644 (file)
@@ -135,7 +135,8 @@ EXTRA_SRCVPATH+=$(IPC_ROOT)/ti/syslink/family/common        \
                $(IPC_ROOT)/ti/syslink/family/$(IPC_PLATFORM)   \
                $(IPC_ROOT)/ti/syslink/family/$(IPC_PLATFORM)/$(IPC_PLATFORM)dsp        \
                $(IPC_ROOT)/ti/syslink/family/$(IPC_PLATFORM)/$(IPC_PLATFORM)ipu        \
-                $(IPC_REPO)/qnx/src/api/gates
+                $(IPC_REPO)/qnx/src/api/gates \
+                $(IPC_REPO)/qnx/src/cfg/dra7xx
 
 EXCLUDE_OBJS = GateMP.o
 endif
similarity index 55%
rename from qnx/src/ipc3x_dev/ti/syslink/family/vayu/gptimers.c
rename to qnx/src/ipc3x_dev/ti/syslink/family/vayu/Gpt.c
index 72558458ad9bba2663e77bfcef951e1bf6cd43bf..bb7405e810a65d0f5711d926a42726294850b545 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, Texas Instruments Incorporated
+ * Copyright (c) 2014-2015, Texas Instruments Incorporated
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -46,7 +46,7 @@
 #include <ti/syslink/utils/Trace.h>
 #include <MultiProc.h>
 #include <_MultiProc.h>
-#include <gptimers.h>
+#include <Gpt.h>
 
 
 /* Start a software forced wake-up */
 #define CM_IPU_TIMER7_CLKCTRL_OFFSET      0x68
 #define CM_IPU_TIMER8_CLKCTRL_OFFSET      0x70
 
-/* Timer base addresses and size */
-#define GPTIMER4_BASE 0x48036000
-#define GPTIMER9_BASE 0x4803E000
+/* Size of timer register sets */
 #define TIMER_REG_SIZE 0x1000
 
+/* Timer physical base addresses */
+static uint32_t gptPhyBase[GPT_TIMER_NUM] = {
+    0x4AE18000,  /* GPT_TIMER_1  */
+    0x48032000,  /* GPT_TIMER_2  */
+    0x48034000,  /* GPT_TIMER_3  */
+    0x48036000,  /* GPT_TIMER_4  */
+    0x48820000,  /* GPT_TIMER_5  */
+    0x48822000,  /* GPT_TIMER_6  */
+    0x48824000,  /* GPT_TIMER_7  */
+    0x48826000,  /* GPT_TIMER_8  */
+    0x4803E000,  /* GPT_TIMER_9  */
+    0x48086000,  /* GPT_TIMER_10 */
+    0x48088000,  /* GPT_TIMER_11 */
+};
+
 /*
  * Interrupts for GPTimers used as watchdog
  * They correspond to MPU_IRQ numbers + 32
+ * This works for Timers 1-11
  */
-#define VAYU_IRQ_GPT4 (40 + 32)
-#define VAYU_IRQ_GPT9 (45 + 32)
-
-typedef enum {
-    GPTIMER_4 = 0,
-    GPTIMER_9,
-    GPTIMER_MAX
-} gpt_Nums;
+#define VAYU_IRQ_GPT(x)  (37 + (x) + 32)
 
 /* GPTimer registers */
-typedef struct gpt_Regs {
+typedef struct Gpt_Regs {
     uint32_t tidr;
     uint32_t space[3];
     uint32_t tiocp_cfg;
@@ -130,32 +137,30 @@ typedef struct gpt_Regs {
     uint32_t tcvr;
     uint32_t tocr;
     uint32_t towr;
-} gpt_Regs;
+} Gpt_Regs;
 
 /*
  * Defines the state object, which contains all the module
  * specific information.
  */
-struct gpt_module_object {
+struct Gpt_module_object {
     uintptr_t cmCoreAonBaseVa;
     /* base address to CM_CORE_AON__IPU */
     bool isSetup;
     /* Indicates whether the module is setup. */
-    bool isAttached;
+    bool isAttached[MultiProc_MAXPROCESSORS];
     /* Indicates whether the module is attached. */
-    OsalIsr_Handle gpt4IsrObject;
-    /* ISR handle for gpt4 WDT */
-    OsalIsr_Handle gpt9IsrObject;
-    /* ISR handle for gpt9 WDT */
-    void *         gpt4BaseAddr;
-    /* Base address of GPTimer 4 registers */
-    void *         gpt9BaseAddr;
-    /* Base address of GPTimer 9 registers */
+    OsalIsr_Handle gptIsrObjects[GPT_TIMER_NUM];
+    /* ISR handle for Watchdog timers */
+    void *         gptBaseAddr[GPT_TIMER_NUM];
+    /* Virtual base addresses of GPTimer registers */
     ProcMgr_Handle proc_handles[MultiProc_MAXPROCESSORS];
     /* Array of processor handles */
+    char **  wdtOwnerProcessor;
+    /* Define the processor which owns a given gptimer as watchdog timer */
 };
 
-static struct gpt_module_object gptState = {
+static struct Gpt_module_object gptState = {
     .cmCoreAonBaseVa = NULL,
     .isSetup = false
 };
@@ -197,7 +202,7 @@ static int disable(uintptr_t reg)
 }
 
 /* Enable GP timers (only the ones in PD_IPU for now) */
-static int gpt_enable()
+static int Gpt_enable()
 {
     /* make sure abe clock domain is enabled as it is source for gpt5-8 */
     out32((uintptr_t)(gptState.cmCoreAonBaseVa + CM_IPU_CLKSTCTRL_OFFSET),
@@ -228,7 +233,7 @@ static int gpt_enable()
 }
 
 /* Disable GP timers (only the ones in PD_IPU for now) */
-static int gpt_disable()
+static int Gpt_disable()
 {
     disable(gptState.cmCoreAonBaseVa + CM_IPU_TIMER5_CLKCTRL_OFFSET);
     disable(gptState.cmCoreAonBaseVa + CM_IPU_TIMER6_CLKCTRL_OFFSET);
@@ -243,13 +248,23 @@ static int gpt_disable()
 }
 
 /* Setup module */
-int gpt_setup()
+int Gpt_setup(Gpt_Config * cfg)
 {
+    int i;
     int retval = EOK;
 
+    if (cfg == NULL) {
+        return -EINVAL;
+    }
+
     if (gptState.isSetup == false) {
         gptState.isSetup = true;
 
+        gptState.wdtOwnerProcessor = cfg->wdtOwnerProcessor;
+
+        memset(gptState.gptIsrObjects, 0, sizeof(gptState.gptIsrObjects));
+        memset(gptState.proc_handles, 0, sizeof(gptState.proc_handles));
+
         gptState.cmCoreAonBaseVa = (uintptr_t)mmap_device_io(
             CM_CORE_AON__IPU_SIZE, CM_CORE_AON__IPU_BASE);
         if((uintptr_t)gptState.cmCoreAonBaseVa == MAP_DEVICE_FAILED) {
@@ -258,47 +273,48 @@ int gpt_setup()
             goto exit;
         }
 
-        gpt_enable();
-
-        gptState.gpt4BaseAddr = (void *)mmap_device_io(TIMER_REG_SIZE,
-            GPTIMER4_BASE);
-        if ((uintptr_t)gptState.gpt4BaseAddr == MAP_DEVICE_FAILED) {
-            retval = -ENOMEM;
-            gptState.gpt4BaseAddr = NULL;
-            goto exit;
-        }
-
-        gptState.gpt9BaseAddr = (void *)mmap_device_io(TIMER_REG_SIZE,
-            GPTIMER9_BASE);
-        if ((uintptr_t)gptState.gpt9BaseAddr == MAP_DEVICE_FAILED) {
-            retval = -ENOMEM;
-            gptState.gpt9BaseAddr = NULL;
-            goto exit;
+        Gpt_enable();
+
+        /* Map registers for watchdog timers */
+        for (i = 0; i < GPT_TIMER_NUM; i++) {
+            if (gptState.wdtOwnerProcessor[i] != NULL) {
+                gptState.gptBaseAddr[i] = (void *)mmap_device_io(
+                    TIMER_REG_SIZE, gptPhyBase[i]);
+                if ((uintptr_t)gptState.gptBaseAddr[i] ==
+                    MAP_DEVICE_FAILED) {
+                    retval = -ENOMEM;
+                    gptState.gptBaseAddr[i] = NULL;
+                    goto exit;
+                }
+            }
+            else {
+                gptState.gptBaseAddr[i] = NULL;
+            }
         }
     }
 
 exit:
     if (retval != EOK) {
-        gpt_destroy();
+        Gpt_destroy();
     }
     return retval;
 }
 
 /* Finalize module */
-int gpt_destroy()
+int Gpt_destroy()
 {
-    if (gptState.isSetup) {
-        if (gptState.gpt9BaseAddr) {
-            munmap((void *)gptState.gpt9BaseAddr, TIMER_REG_SIZE);
-            gptState.gpt9BaseAddr = NULL;
-        }
+    int i;
 
-        if (gptState.gpt4BaseAddr) {
-            munmap((void *)gptState.gpt4BaseAddr, TIMER_REG_SIZE);
-            gptState.gpt4BaseAddr = NULL;
+    if (gptState.isSetup) {
+        /* Unmap registers for watchdog timers */
+        for (i = 0; i < GPT_TIMER_NUM; i++) {
+            if (gptState.gptBaseAddr[i] != NULL) {
+                munmap((void *)gptState.gptBaseAddr[i], TIMER_REG_SIZE);
+                gptState.gptBaseAddr[i] = NULL;
+            }
         }
 
-        gpt_disable();
+        Gpt_disable();
 
         if (gptState.cmCoreAonBaseVa) {
             munmap((void *)gptState.cmCoreAonBaseVa, CM_CORE_AON__IPU_SIZE);
@@ -311,212 +327,178 @@ int gpt_destroy()
 }
 
 /* Watchdog interrupt handler */
-static Bool gpt_interrupt(Ptr fxnArgs)
+static Bool Gpt_interrupt(Ptr fxnArgs)
 {
-    int num;
-    /* Using IPU2's id since that is the offically supported IPU */
-    uint16_t ipu2_id = MultiProc_getId("IPU2");
+    Gpt_Nums       timer = (Gpt_Nums)fxnArgs;
+    int            num = timer + 1;   /* GP timer number */
+    ProcMgr_Handle procHandle;
 
     /* Trigger recovery by setting the ProcMgr state */
-    switch ((uint32_t)fxnArgs) {
-        case GPTIMER_4:
-            num = 4;
-            ProcMgr_setState(gptState.proc_handles[ipu2_id],
-                ProcMgr_State_Watchdog);
-            break;
-        case GPTIMER_9:
-            num = 9;
-            ProcMgr_setState(gptState.proc_handles[ipu2_id],
-                ProcMgr_State_Watchdog);
-            break;
-        default:
-            num = 0;
-            break;
+    if (gptState.wdtOwnerProcessor[timer] != NULL) {
+        procHandle = gptState.proc_handles[MultiProc_getId(
+            gptState.wdtOwnerProcessor[timer])];
+        if (procHandle != NULL) {
+            ProcMgr_setState(procHandle, ProcMgr_State_Watchdog);
+        }
+
     }
 
     GT_1trace(curTrace, GT_4CLASS,
-              "gpt_interrupt: GPTimer %d expired!", num);
+          "Gpt_interrupt: GPTimer %d expired!", num);
 
     return 0;
 }
 
 /* Interrupt clear function*/
-static Bool gpt_clr_interrupt(Ptr fxnArgs)
+static Bool Gpt_clr_interrupt(Ptr fxnArgs)
 {
     uintptr_t reg;
-    uint32_t num = (uint32_t)fxnArgs;
-    gpt_Regs *GPTRegs = NULL;
+    Gpt_Nums timer = (Gpt_Nums)fxnArgs;
+    Gpt_Regs *gptRegs = NULL;
 
-    if (num == GPTIMER_4) {
-        GPTRegs = gptState.gpt4BaseAddr;
-    }
-    else if (num == GPTIMER_9) {
-        GPTRegs = gptState.gpt9BaseAddr;
-    }
-    else {
+    gptRegs = gptState.gptBaseAddr[timer];
+
+    if (gptRegs == NULL) {
         return TRUE;
     }
 
-    reg = in32((uintptr_t)&GPTRegs->irqstatus);
+    reg = in32((uintptr_t)&gptRegs->irqstatus);
     reg |= 0x2;
 
     /*Clear Overflow event */
-    out32((uintptr_t)&GPTRegs->irqstatus, reg);
-    reg = in32((uintptr_t)&GPTRegs->irqstatus);
+    out32((uintptr_t)&gptRegs->irqstatus, reg);
+    reg = in32((uintptr_t)&gptRegs->irqstatus);
 
     /*Always return TRUE for ISR*/
     return TRUE;
 }
 
 /* Stop watchdog timer */
-static void gpt_wdt_stop(int num)
+static void Gpt_wdt_stop(int num)
 {
     uintptr_t reg;
-    gpt_Regs *GPTRegs = NULL;
+    Gpt_Regs *gptRegs = NULL;
 
-    if (num == GPTIMER_4) {
-        GPTRegs = gptState.gpt4BaseAddr;
-    }
-    else if (num == GPTIMER_9) {
-        GPTRegs = gptState.gpt9BaseAddr;
-    }
-    else {
+    gptRegs = gptState.gptBaseAddr[num];
+
+    if (gptRegs == NULL) {
         return;
     }
 
-    reg = in32((uintptr_t)&GPTRegs->tclr);
+    reg = in32((uintptr_t)&gptRegs->tclr);
     reg &= GPT_TCLR_STOP_MASK;
 
     /* Clear Overflow event */
-    out32((uintptr_t)&GPTRegs->tclr, reg);
+    out32((uintptr_t)&gptRegs->tclr, reg);
 
-    reg = in32((uintptr_t)&GPTRegs->twps);
+    reg = in32((uintptr_t)&gptRegs->twps);
     while (reg & GPT_TWPS_W_PEND_TCLR) {
-        reg = in32((uintptr_t)&GPTRegs->twps);
+        reg = in32((uintptr_t)&gptRegs->twps);
     }
 
     /* Clear status bits */
-    reg = in32((uintptr_t)&GPTRegs->irqstatus);
+    reg = in32((uintptr_t)&gptRegs->irqstatus);
     if (reg) {
-        out32((uintptr_t)&GPTRegs->irqstatus, reg);
+        out32((uintptr_t)&gptRegs->irqstatus, reg);
     }
 }
 
 /* Wire the Watchdog interrupts to trigger recovery */
-int gpt_wdt_attach(int proc_id)
+int Gpt_wdt_attach(int proc_id)
 {
     int retval = EOK;
+    int i;
     OsalIsr_Params isrParams;
 
     if (proc_id > MultiProc_MAXPROCESSORS) {
         return -EINVAL;
     }
 
-    /* Only do the setup once since we only have two watchdog timers */
-    if (gptState.isAttached) {
+    /* Only do the setup once per processor */
+    if (gptState.isAttached[proc_id]) {
         return EOK;
     }
 
-    if ((proc_id == MultiProc_getId("IPU1")) ||
-        (proc_id == MultiProc_getId("IPU2"))) {
-        gptState.isAttached = true;
-        isrParams.checkAndClearFxn = gpt_clr_interrupt;
-        isrParams.fxnArgs = (Ptr)GPTIMER_9;
-        isrParams.intId = VAYU_IRQ_GPT9;
-        isrParams.sharedInt = FALSE;
-        gptState.gpt9IsrObject =
-            OsalIsr_create(&gpt_interrupt,
+    gptState.isAttached[proc_id] = true;
+
+    for (i = 0; i < GPT_TIMER_NUM; i++) {
+        if ((gptState.wdtOwnerProcessor[i] != NULL) &&
+            (strcmp(gptState.wdtOwnerProcessor[i], MultiProc_getName(proc_id))
+            == 0)) {
+            isrParams.checkAndClearFxn = Gpt_clr_interrupt;
+            isrParams.fxnArgs = (Ptr)i;
+            isrParams.intId = VAYU_IRQ_GPT(i);
+            isrParams.sharedInt = FALSE;
+            gptState.gptIsrObjects[i] =
+                OsalIsr_create(&Gpt_interrupt,
                            isrParams.fxnArgs, &isrParams);
-        if(gptState.gpt9IsrObject != NULL) {
-            if (OsalIsr_install(gptState.gpt9IsrObject) < 0) {
-                retval = -ENOMEM;
+            if (gptState.gptIsrObjects[i] != NULL) {
+                if (OsalIsr_install(gptState.gptIsrObjects[i]) < 0) {
+                    retval = -ENOMEM;
+                }
             }
-        }
-        else {
-            retval = -ENOMEM;
-        }
-
-        isrParams.checkAndClearFxn = gpt_clr_interrupt;
-        isrParams.fxnArgs = (Ptr)GPTIMER_4;
-        isrParams.intId = VAYU_IRQ_GPT4;
-        isrParams.sharedInt = FALSE;
-        gptState.gpt4IsrObject =
-            OsalIsr_create(&gpt_interrupt,
-                           isrParams.fxnArgs, &isrParams);
-        if(gptState.gpt4IsrObject != NULL) {
-            if (OsalIsr_install(gptState.gpt4IsrObject) < 0) {
+            else {
                 retval = -ENOMEM;
             }
-        }
-        else {
-            retval = -ENOMEM;
-        }
-
 
-        if (retval >= 0) {
-            if (gptState.proc_handles[MultiProc_getId("IPU2")] == NULL) {
-                /* Using IPU2's entry since it is the offically supported IPU */
-                retval = ProcMgr_open(&gptState.proc_handles[
-                    MultiProc_getId("IPU2")], proc_id);
-            }
-        }
-        else {
-            if ((proc_id == MultiProc_getId("IPU1")) ||
-                (proc_id == MultiProc_getId("IPU2"))) {
-                if (gptState.gpt9IsrObject) {
-                    OsalIsr_uninstall(gptState.gpt9IsrObject);
-                    OsalIsr_delete(&gptState.gpt9IsrObject);
-                    gptState.gpt9IsrObject = NULL;
+            if (retval >= 0) {
+                if (gptState.proc_handles[proc_id] == NULL) {
+                    retval = ProcMgr_open(&gptState.proc_handles[proc_id], proc_id);
+                    if (retval < 0) {
+                        Gpt_wdt_detach(proc_id);
+                        retval = -EPERM;
+                        break;
+                    }
                 }
-
-                if (gptState.gpt4IsrObject) {
-                    OsalIsr_uninstall(gptState.gpt4IsrObject);
-                    OsalIsr_delete(&gptState.gpt4IsrObject);
-                    gptState.gpt4IsrObject = NULL;
+            }
+            else {
+                if (gptState.gptIsrObjects[i]) {
+                    OsalIsr_delete(&gptState.gptIsrObjects[i]);
+                    gptState.gptIsrObjects[i] = NULL;
                 }
+                break;
             }
         }
     }
+
     return retval;
 }
 
 /* Un-hook the Watchdog interrupt handler */
-int gpt_wdt_detach(int proc_id)
+int Gpt_wdt_detach(int proc_id)
 {
-    int retval = EOK;
+    int i;
 
     if (proc_id > MultiProc_MAXPROCESSORS) {
         return -EINVAL;
     }
 
-    if (gptState.isAttached) {
-        if ((proc_id == MultiProc_getId("IPU1")) ||
-            (proc_id == MultiProc_getId("IPU2"))) {
-            OsalIsr_uninstall(gptState.gpt9IsrObject);
-            OsalIsr_delete(&gptState.gpt9IsrObject);
-            gptState.gpt9IsrObject = NULL;
-
-            OsalIsr_uninstall(gptState.gpt4IsrObject);
-            OsalIsr_delete(&gptState.gpt4IsrObject);
-            gptState.gpt4IsrObject = NULL;
-
-            /* Using IPU2's entry since it is the offically supported IPU */
-            if (gptState.proc_handles[MultiProc_getId("IPU2")]) {
-                ProcMgr_close(&gptState.proc_handles[MultiProc_getId("IPU2")]);
-                gptState.proc_handles[MultiProc_getId("IPU2")] = NULL;
+    if (gptState.isAttached[proc_id]) {
+        for (i = 0; i < GPT_TIMER_NUM; i++) {
+            if ((gptState.wdtOwnerProcessor[i] != NULL) &&
+                (strcmp(gptState.wdtOwnerProcessor[i],
+                MultiProc_getName(proc_id))) == 0) {
+                /*
+                 * Stop the watchdog timers. We rely on the slave processors to
+                 * start them, but on unload the host should stop them to avoid
+                 * getting watchdog interrupts upon reload.
+                 */
+                Gpt_wdt_stop(i);
+
+                if (gptState.gptIsrObjects[i]) {
+                    OsalIsr_uninstall(gptState.gptIsrObjects[i]);
+                    OsalIsr_delete(&gptState.gptIsrObjects[i]);
+                    gptState.gptIsrObjects[i] = NULL;
+                }
+                if (gptState.proc_handles[proc_id]) {
+                    ProcMgr_close(&gptState.proc_handles[proc_id]);
+                    gptState.proc_handles[proc_id] = NULL;
+                }
             }
-
-            /*
-             * Stop the watchdog timers. We rely on the slave processors to
-             * start them, but on unload the host should stop them to avoid
-             * getting watchdog interrupts upon reload.
-             */
-            gpt_wdt_stop(GPTIMER_4);
-            gpt_wdt_stop(GPTIMER_9);
-
-            gptState.isAttached = false;
         }
+
+        gptState.isAttached[proc_id] = false;
     }
 
-    return retval;
+    return EOK;
 }
similarity index 71%
rename from qnx/src/ipc3x_dev/ti/syslink/family/vayu/gptimers.h
rename to qnx/src/ipc3x_dev/ti/syslink/family/vayu/Gpt.h
index 1370a42bce7f990aafa4b23011e355a348a49d17..ed2ed15235d9e7da674178debfd5640f4a4173dd 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, Texas Instruments Incorporated
+ * Copyright (c) 2014-2015, Texas Instruments Incorporated
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,8 +29,8 @@
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-#ifndef _GPTIMERS_H
-#define _GPTIMERS_H
+#ifndef _GPT_H
+#define _GPT_H
 
 #include <stdint.h>
 
 extern "C" {
 #endif
 
+/* List of timers */
+/* The QNX BSP fully enables GP Timers 1-11, thus we support the same set */
+typedef enum {
+    GPT_TIMER_1 = 0,
+    GPT_TIMER_2,
+    GPT_TIMER_3,
+    GPT_TIMER_4,
+    GPT_TIMER_5,
+    GPT_TIMER_6,
+    GPT_TIMER_7,
+    GPT_TIMER_8,
+    GPT_TIMER_9,
+    GPT_TIMER_10,
+    GPT_TIMER_11,
+    GPT_TIMER_NUM,
+    GPT_TIMER_INVALID
+} Gpt_Nums;
+
+typedef struct Gpt_Config {
+    char * wdtOwnerProcessor[GPT_TIMER_NUM];
+} Gpt_Config;
+
+/* Gpt configuration structure */
+extern Gpt_Config ti_ipc_Gpt_cfg;
+
 /* Enable GP timers */
-int gpt_setup();
+int Gpt_setup(Gpt_Config * cfg);
 
 /* Disable GP timers */
-int gpt_destroy();
+int Gpt_destroy();
 
 /* Wire the Watchdog interrupts to trigger recovery */
-int gpt_wdt_attach(int proc_id);
+int Gpt_wdt_attach(int proc_id);
 
 /* Un-hook the Watchdog interrupt handler */
-int gpt_wdt_detach(int proc_id);
+int Gpt_wdt_detach(int proc_id);
 
 #if defined (__cplusplus)
 }
 #endif /* defined (__cplusplus) */
 
-#endif /* _GPTIMERS_H */
+#endif /* _GPT_H */
index e5b155a25ae8270204712a4dd41482e4a1a57a57..48706678f7726ce18e5380d0012a9f350baf0203 100644 (file)
@@ -83,7 +83,7 @@
 #include <IpcKnl.h>
 #include <sys/mman.h>
 #include <GateHWSpinlock.h>
-#include <gptimers.h>
+#include <Gpt.h>
 
 #if defined (__cplusplus)
 extern "C" {
@@ -460,10 +460,10 @@ Platform_setup (Ipc_Config * cfg)
 
     /* Enable GP timers */
     if (status >= 0) {
-        status = gpt_setup();
+        status = Gpt_setup(&ti_ipc_Gpt_cfg);
         if (status < 0) {
             GT_setFailureReason(curTrace, GT_4CLASS, "Platform_setup",
-                    status, "gpt_setup failed!");
+                    status, "Gpt_setup failed!");
         }
     }
 
@@ -507,7 +507,7 @@ Platform_destroy (void)
     }
 
     /* disable GP timers */
-    gpt_destroy();
+    Gpt_destroy();
 
     /* Finalize elf loader */
     if (Platform_module->elfLoaderInitFlag == TRUE) {
index a88d218b6f071cee423322b95783f03fa39f9259..1dc5a61866375e53659c59ac9fd6187554966ed6 100644 (file)
@@ -44,7 +44,7 @@
 #include <ti/ipc/MessageQCopy.h>
 
 #if defined(IPC_PLATFORM_VAYU)
-#include <gptimers.h>
+#include <Gpt.h>
 #endif
 
 /*  ----------------------------------- utils Headers   */
@@ -216,7 +216,7 @@ Int Ipc_attach (UInt16 remoteProcId)
 
 #if !defined(IPC_DISABLE_WATCHDOG) && defined(IPC_PLATFORM_VAYU)
         if (status >= 0) {
-            status = gpt_wdt_attach(remoteProcId);
+            status = Gpt_wdt_attach(remoteProcId);
             if (status < 0) {
                 MessageQCopy_detach(remoteProcId);
             }
@@ -262,7 +262,7 @@ Int Ipc_detach (UInt16 remoteProcId)
 #endif
 
 #if !defined(IPC_DISABLE_WATCHDOG) && defined(IPC_PLATFORM_VAYU)
-        status = gpt_wdt_detach(remoteProcId);
+        status = Gpt_wdt_detach(remoteProcId);
 #endif
 
         status = MessageQCopy_detach (remoteProcId);