BIOS IPC: Vayu - Update AMMU and MMU Configuration
authorAngela Stegmaier <angelabaker@ti.com>
Wed, 24 Apr 2013 18:44:21 +0000 (13:44 -0500)
committerVW <vwan@ti.com>
Tue, 30 Apr 2013 17:28:04 +0000 (10:28 -0700)
In the 16_eng release, the mailbox virtual address
changed to 0x60000000 block.  This was previously where
the TILER addresses were mapped.  As a consequence, the
TILER mappings needed to be moved, and the AMMU config
as well as the resource table needed to be updated
to reflect the changes.  Also, as a result of the move,
the VRING virtual addresses for the IPU have changed.

TILER VA: Moved from 0x60000000 to 0xA0000000
Peripherals and VRING: Moved from 0xA0000000 to 0x60000000

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
packages/ti/configs/vayu/IpuAmmu.cfg
packages/ti/ipc/family/vayu/VirtQueue.c
packages/ti/ipc/remoteproc/rsc_table_vayu_ipu.h

index f9b97b37e0f88c835168546cb33f9541f6f93ba5..2939e51ef5394484d76a1f96bd10995d5ffcc780 100644 (file)
@@ -149,13 +149,13 @@ AMMU.largePages[0].size = AMMU.Large_512M;
 AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED;
 
-/* TILER & DMM regions: Large page (512M); cacheable */
+/* Peripheral regions: Large Page (512M); non-cacheable */
 /* config large page[1] to map 512MB VA 0x60000000 to L3 0x60000000 */
 AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
 AMMU.largePages[1].logicalAddress = 0x60000000;
 AMMU.largePages[1].translationEnabled = AMMU.Enable_NO;
 AMMU.largePages[1].size = AMMU.Large_512M;
-AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
 AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
 
 /* Private, Shared and IPC Data regions: Large page (512M); cacheable */
@@ -167,11 +167,11 @@ AMMU.largePages[2].size = AMMU.Large_512M;
 AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;
 
-/* Peripheral regions: Large Page (512M); non-cacheable */
+/* TILER & DMM regions: Large page (512M); cacheable */
 /* config large page[3] to map 512MB VA 0xA0000000 to L3 0xA0000000 */
 AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
 AMMU.largePages[3].logicalAddress = 0xA0000000;
 AMMU.largePages[3].translationEnabled = AMMU.Enable_NO;
 AMMU.largePages[3].size = AMMU.Large_512M;
-AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
 AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_POSTED;
index f7cdf2ce5c64c6e77ae04dbcff88aceca851ff36..438e1af4f4cc007e4d91d8b1ad2a837be37a3daf 100644 (file)
 #define NUM_QUEUES              4
 
 /* Predefined device addresses */
+#ifdef DSP
 #define IPC_MEM_VRING0          0xA0000000
 #define IPC_MEM_VRING1          0xA0004000
 #define IPC_MEM_VRING2          0xA0008000
 #define IPC_MEM_VRING3          0xA000c000
+#else
+#define IPC_MEM_VRING0          0x60000000
+#define IPC_MEM_VRING1          0x60004000
+#define IPC_MEM_VRING2          0x60008000
+#define IPC_MEM_VRING3          0x6000c000
+#endif
 
 /*
  * Sizes of the virtqueues (expressed in number of buffers supported,
index 36c8dc4066a12adb6d7921365d6a36cafcf1ae5e..6700b0dca6271d64c6ebd0905305958dd804f71d 100644 (file)
 #define L4_44XX_BASE            0x4a000000
 
 #define L4_PERIPHERAL_L4CFG     (L4_44XX_BASE)
-#define IPU_PERIPHERAL_L4CFG    0xAA000000
+#define IPU_PERIPHERAL_L4CFG    0x6A000000
 
 #define L4_PERIPHERAL_L4PER     0x48000000
-#define IPU_PERIPHERAL_L4PER    0xA8000000
+#define IPU_PERIPHERAL_L4PER    0x68000000
 
 #define L4_PERIPHERAL_L4EMU     0x54000000
-#define IPU_PERIPHERAL_L4EMU    0xB4000000
+#define IPU_PERIPHERAL_L4EMU    0x74000000
 
 #define L3_PERIPHERAL_DMM       0x4E000000
-#define IPU_PERIPHERAL_DMM      0xAE000000
+#define IPU_PERIPHERAL_DMM      0x6E000000
 
 #define L3_IVAHD_CONFIG         0x5A000000
-#define IPU_IVAHD_CONFIG        0xBA000000
+#define IPU_IVAHD_CONFIG        0x7A000000
 
 #define L3_IVAHD_SL2            0x5B000000
-#define IPU_IVAHD_SL2           0xBB000000
+#define IPU_IVAHD_SL2           0x7B000000
 
 #define L3_TILER_MODE_0_1       0x60000000
-#define IPU_TILER_MODE_0_1      0x60000000
+#define IPU_TILER_MODE_0_1      0xA0000000
 
 #define L3_TILER_MODE_2         0x70000000
-#define IPU_TILER_MODE_2        0x70000000
+#define IPU_TILER_MODE_2        0xB0000000
 
 #define L3_TILER_MODE_3         0x78000000
-#define IPU_TILER_MODE_3        0x78000000
+#define IPU_TILER_MODE_3        0xB8000000
 
 #define IPU_MEM_TEXT            0x0
 #define IPU_MEM_DATA            0x80000000
 #endif
 
 #define IPU_MEM_IPC_DATA        0x9F000000
-#define IPU_MEM_IPC_VRING       0xA0000000
-#define IPU_MEM_RPMSG_VRING0    0xA0000000
-#define IPU_MEM_RPMSG_VRING1    0xA0004000
-#define IPU_MEM_VRING_BUFS0     0xA0040000
-#define IPU_MEM_VRING_BUFS1     0xA0080000
+#define IPU_MEM_IPC_VRING       0x60000000
+#define IPU_MEM_RPMSG_VRING0    0x60000000
+#define IPU_MEM_RPMSG_VRING1    0x60004000
+#define IPU_MEM_VRING_BUFS0     0x60040000
+#define IPU_MEM_VRING_BUFS1     0x60080000
 
 #define IPU_MEM_IPC_VRING_SIZE  SZ_1M
 #define IPU_MEM_IPC_DATA_SIZE   SZ_1M