QNX IPC: DSP1 - Need to Enable DSP_SYSTEM Config for MMU0
authorAngela Stegmaier <angelabaker@ti.com>
Fri, 3 May 2013 14:02:31 +0000 (09:02 -0500)
committerAngela Stegmaier <angelabaker@ti.com>
Sat, 4 May 2013 16:43:50 +0000 (11:43 -0500)
If using DSP1 with the MMU enabled, need to also enable
the global config for MMU0 through the DSP_SYS_MMU_CONFIG
MMU0_EN bit.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspHalReset.c
qnx/src/ipc3x_dev/ti/syslink/family/common/vayu/vayudsp/VAYUDspPhyShmem.c
qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspHal.h
qnx/src/ipc3x_dev/ti/syslink/inc/knl/VAYUDspPhyShmem.h

index 842ad1734c7faa7381a29ec635d4d097571206a5..5e6bb19005ba8640ee02c9224090a2fdc80c01ec 100644 (file)
@@ -94,6 +94,8 @@ extern "C" {
 #define RM_DSP_RSTCTRL        0x410
 #define RM_DSP_RSTST          0x414
 
+#define DSP_SYS_MMU_CONFIG_OFFSET 0x18
+
 /* =============================================================================
  * APIs called by VAYUDSPPROC module
  * =============================================================================
@@ -114,6 +116,7 @@ VAYUDSP_halResetCtrl(Ptr halObj, VAYUDspHal_ResetCmd cmd)
     VAYUDSP_HalObject *     halObject = NULL;
     UInt32                  cmBase;
     UInt32                  prmBase;
+    UInt32                  mmuSysBase;
     UInt32                  addr;
     UInt32                  val;
     Int32                   counter = 10;
@@ -126,6 +129,7 @@ VAYUDSP_halResetCtrl(Ptr halObj, VAYUDspHal_ResetCmd cmd)
     halObject = (VAYUDSP_HalObject *)halObj;
     cmBase = halObject->cmBase;
     prmBase = halObject->prmBase;
+    mmuSysBase = halObject->mmuSysBase;
 
     switch (cmd) {
         case Processor_ResetCtrlCmd_Reset:
@@ -208,6 +212,11 @@ VAYUDSP_halResetCtrl(Ptr halObj, VAYUDspHal_ResetCmd cmd)
 #endif
             Osal_printf("DSP:RST2 released!\n");
             OUTREG32(addr, 0x2);
+
+            /* enable MMU0 through global system register */
+            val = INREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET);
+            OUTREG32(mmuSysBase + DSP_SYS_MMU_CONFIG_OFFSET, (val & ~0x1) | 0x1);
+            Osal_printf("DSP:SYS_MMU_CONFIG MMU0 enabled!\n");
         }
         break;
 
index c6875f5d86c8b19c7cc75624692040a5d1c543ab..189fe4b7baf589d8ef3b0fdae83077444f0c1c89 100644 (file)
@@ -206,6 +206,22 @@ VAYUDSP_phyShmemInit (Ptr halObj)
         halObject->mmuBase = mapInfo.dst;
     }
 
+    mapInfo.src      = DSP_SYS_MMU_CONFIG_BASE;
+    mapInfo.size     = DSP_SYS_MMU_CONFIG_SIZE;
+    mapInfo.isCached = FALSE;
+    status = Memory_map (&mapInfo);
+    if (status < 0) {
+        GT_setFailureReason (curTrace,
+                             GT_4CLASS,
+                             "VAYUDSP_phyShmemInit",
+                             status,
+                             "Failure in Memory_map for SYS MMU base registers");
+        halObject->mmuSysBase = 0;
+    }
+    else {
+        halObject->mmuSysBase = mapInfo.dst;
+    }
+
     GT_1trace(curTrace, GT_LEAVE, "<-- VAYUDSP_phyShmemInit: 0x%x", status);
 
     /*! @retval PROCESSOR_SUCCESS Operation successful */
@@ -249,6 +265,21 @@ VAYUDSP_phyShmemExit (Ptr halObj)
         halObject->mmuBase = 0 ;
     }
 
+    unmapInfo.addr = halObject->mmuSysBase;
+    unmapInfo.size = DSP_SYS_MMU_CONFIG_SIZE;
+    unmapInfo.isCached = FALSE;
+    if (unmapInfo.addr != 0) {
+        status = Memory_unmap (&unmapInfo);
+        if (status < 0) {
+            GT_setFailureReason (curTrace,
+                              GT_4CLASS,
+                              "VAYUDSP_phyShmemExit",
+                              status,
+                              "Failure in Memory_Unmap for SYS MMU base registers");
+        }
+        halObject->mmuSysBase = 0 ;
+    }
+
     unmapInfo.addr = halObject->cmBase;
     unmapInfo.size = CM_SIZE;
     unmapInfo.isCached = FALSE;
index 9d4d67eb6f3e775723b7a67668c94e7d80e8d156..a0d5f510267dbec7f87a648c42830f2ec86a1b06 100644 (file)
@@ -88,6 +88,8 @@ typedef struct VAYUDSP_HalObject_tag {
     /*!< Virtual base address of the General Control module. */
     UInt32                mmuBase;
     /*!< Base address of the MMU module. */
+    UInt32                mmuSysBase;
+    /*!< Base address of the MMU module. */
     UInt32                procId;
     /*!< Processor ID. */
     VAYUDSP_HalMmuObject mmuObj;
index cb0a7d64b9035d5c8e0db5fd9d5bb666e9cb84b4..824947091cb7114128d754a3c482c268e3fd296f 100644 (file)
@@ -112,6 +112,12 @@ extern "C" {
 
 #define CM_SIZE                 0x00002000
 
+#define DSP_SYS_MMU_CONFIG_BASE 0x40D00000
+/*!
+ *  @brief  size to be ioremapped.
+ */
+#define DSP_SYS_MMU_CONFIG_SIZE   0x1000
+
 #define MMU_BASE                0x40D01000
 /*!
  *  @brief  size to be ioremapped.