Fix an issue where disabling mailbox interrupts on DSP1 disables IPU interrupts
authorvwan@ti.com <vwan@ti.com>
Fri, 10 Oct 2014 23:44:42 +0000 (16:44 -0700)
committerRobert Tivy <rtivy@ti.com>
Sat, 11 Oct 2014 01:04:18 +0000 (18:04 -0700)
Signed-off-by: VW <vwan@ti.com>
qnx/src/ipc3x_dev/ti/syslink/ipc/hlos/knl/arch/vayu/VAYUIpcInt.c

index 2040e806df09a771854531f3b3f84879652afdee..da213d5c7e0a4d51ede82474ac49d45c5eb6b431 100644 (file)
@@ -1085,25 +1085,25 @@ VAYUIpcInt_interruptDisable (UInt16 procId, UInt32 intId)
         /*
          * Mailbox 5 is used for HOST<->DSP1 communication
          */
-        SET_BIT(REG(VAYUIpcInt_state.mailbox5Base + \
-                    MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)),
-                ( (DSP1_HOST_SUB_MBOX) << 1));
+        REG(VAYUIpcInt_state.mailbox5Base + \
+            MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)) =
+            1 << ((DSP1_HOST_SUB_MBOX) << 1);
     }
     else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU1]) {
         /*
          * Mailbox 5 is used for HOST<->IPU1 communication
          */
-        SET_BIT(REG(VAYUIpcInt_state.mailbox5Base + \
-                    MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)),
-                ( (IPU1_HOST_SUB_MBOX) << 1));
+        REG(VAYUIpcInt_state.mailbox5Base + \
+            MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)) =
+            1 << ((IPU1_HOST_SUB_MBOX) << 1);
     }
     else if (procId == VAYUIpcInt_state.procIds [VAYU_INDEX_IPU2]) {
         /*
          * Mailbox 6 is used for HOST<->IPU2 communication
          */
-        SET_BIT(REG(VAYUIpcInt_state.mailbox6Base + \
-                    MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)),
-                ( (IPU2_HOST_SUB_MBOX) << 1));
+        REG(VAYUIpcInt_state.mailbox6Base + \
+            MAILBOX_IRQENABLE_CLR_OFFSET + (0x10 * VAYU_HOST_USER_ID)) =
+            1 << ((IPU2_HOST_SUB_MBOX) << 1);
     }
 #if !defined(SYSLINK_BUILD_OPTIMIZE)
     else {