7 years agoDM36x: Enabled ethernet driver for dm36x csk ipnc_dm365_uboot_pp ti2016.05-pp-prealpha-36xcsk
DM36x: Enabled ethernet driver for dm36x csk
Changed reset configuration.
Configured phy registers.
Signed-off-by: bhargav <bhargav.a@pathpartnertech.com>
Changed reset configuration.
Configured phy registers.
Signed-off-by: bhargav <bhargav.a@pathpartnertech.com>
DM365 : Supports nand booting
Added ECC macro for nand in compliance with RBL.
Added nand boot args.
Signed-off-by: Sai Prasad <saiprasad.b@pathpartnertech.com>
Added ECC macro for nand in compliance with RBL.
Added nand boot args.
Signed-off-by: Sai Prasad <saiprasad.b@pathpartnertech.com>
DM365: Supports SD card booting
Added config and dts file for DM365
Verified the basic functionality.
Signed-off-by: Sai Prasad <saiprasad.b@pathpartnertech.com>
Added config and dts file for DM365
Verified the basic functionality.
Signed-off-by: Sai Prasad <saiprasad.b@pathpartnertech.com>
7 years agoboard: ti: am57xx-idk: Always fixup PRU Ethernet MAC addresses ipnc-ti-u-boot-2016.05 ti2016.01 ti2016.01-rc4
board: ti: am57xx-idk: Always fixup PRU Ethernet MAC addresses
We should not depend on CONFIG_DRIVER_TI_CPSW to fixup PRU Ethernet
MAC addresses. Always fix them up.
Signed-off-by: Roger Quadros <rogerq@ti.com>
We should not depend on CONFIG_DRIVER_TI_CPSW to fixup PRU Ethernet
MAC addresses. Always fix them up.
Signed-off-by: Roger Quadros <rogerq@ti.com>
net: cpsw: get chip clock information from DT
Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") enables the external chip clock
for RMII mode using private data. This data needs to be populated from
DT data. The above commit misses populating this data.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") enables the external chip clock
for RMII mode using private data. This data needs to be populated from
DT data. The above commit misses populating this data.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
am335x_evm: Don't fail SPL USB eth boot
In commit c3839fc5b8e9 ("board: am335x: Always set eth/eth1addr environment variable")
we got rid of setting usbnet_devaddr based on efuse.
However this causes SPL USB eth boot to fail as usbnet_devaddr is
not set. We bring back the code that sets usbnet_devaddr based on
efuse.
Fixes: c3839fc5b8e9 ("board: am335x: Always set eth/eth1addr environment variable")
Signed-off-by: Roger Quadros <rogerq@ti.com>
In commit c3839fc5b8e9 ("board: am335x: Always set eth/eth1addr environment variable")
we got rid of setting usbnet_devaddr based on efuse.
However this causes SPL USB eth boot to fail as usbnet_devaddr is
not set. We bring back the code that sets usbnet_devaddr based on
efuse.
Fixes: c3839fc5b8e9 ("board: am335x: Always set eth/eth1addr environment variable")
Signed-off-by: Roger Quadros <rogerq@ti.com>
driver: net: cpsw: add support for RGMII id mode support for am43xx variants
Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") missed update for am43xx variants.
Updating it here.
Fixes: 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection")
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Commit 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode
support and RMII clock source selection") missed update for am43xx variants.
Updating it here.
Fixes: 6ca5f482a38ce ("driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection")
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: dra7xx: Enable CMD_TIME
Enable CONFIG_CMD_TIME for all dra7xx platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable CONFIG_CMD_TIME for all dra7xx platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: am57xx: Enable CMD_TIME
Enable CONFIG_CMD_TIME for all am57x platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable CONFIG_CMD_TIME for all am57x platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: am43xx: Enable CMD_TIME
Enable CONFIG_CMD_TIME for all am43xx platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable CONFIG_CMD_TIME for all am43xx platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: am335x: Enable CMD_TIME
Enable CONFIG_CMD_TIME for all am335x platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable CONFIG_CMD_TIME for all am335x platforms
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
usb: phy: omap_usb_phy: Fix USB3_PHY DPLL configuration
The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.
This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.
Signed-off-by: Roger Quadros <rogerq@ti.com>
The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.
This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.
Signed-off-by: Roger Quadros <rogerq@ti.com>
dra7xx: Enable USB_PHY3 32KHz clock
DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.
Signed-off-by: Roger Quadros <rogerq@ti.com>
DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.
Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: AM57xx: AM43xx: Fix USB host
CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.
Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.
Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks")
Signed-off-by: Roger Quadros <rogerq@ti.com>
CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.
Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.
Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks")
Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAP
CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.
Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks"
Signed-off-by: Roger Quadros <rogerq@ti.com>
CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.
Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks"
Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: AM57xx EVM: enable driver model Ethernet driver
Now that we have driver model Ethernet driver
integrated, switch to using that instead of
unsupported legacy driver.
Ethernet continues to work before and after this
patch on AM572x GP EVM.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Now that we have driver model Ethernet driver
integrated, switch to using that instead of
unsupported legacy driver.
Ethernet continues to work before and after this
patch on AM572x GP EVM.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: AM57xx EVM: enable driver model AHCI driver
Now that we have AHCI driver integrated, switch
to use that instead of the unsupported legacy
driver.
This fixes broken SATA support on AM572x GP EVM.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Now that we have AHCI driver integrated, switch
to use that instead of the unsupported legacy
driver.
This fixes broken SATA support on AM572x GP EVM.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
configd: keystone2: env: Fix burn_uboot_spi command
Now the u-boot spi image is greater than 0x80000, increase the same
in env during spi erase.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now the u-boot spi image is greater than 0x80000, increase the same
in env during spi erase.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
drivers: net: phy: atheros: add separate config for AR8031
In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R <vigneshr@ti.com>
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R <vigneshr@ti.com>
ARM: OMAP4+: Fix DPLL programming sequence
All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
spl: Add an option to load a FIT containing U-Boot from UART
This provides a way to load a FIT containing U-Boot and a selection of device
tree files from UART.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This provides a way to load a FIT containing U-Boot and a selection of device
tree files from UART.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
spl: fit: Fix the number of bytes read when reading fdt from fit
sectors field is not being updated when reading fdt from fit image. Because of
this size_of(u-boot.bin) is being read when reading fdt. Fixing it by updating
the sectors field properly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
sectors field is not being updated when reading fdt from fit image. Because of
this size_of(u-boot.bin) is being read when reading fdt. Fixing it by updating
the sectors field properly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
spl: fit: Do not print selected dtb during fit load
No prints should be allowed during UART load.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
No prints should be allowed during UART load.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
include: configs: am335x: add Atheros phy support
In AM335x GP EVM, Atheros 8031 phy is used, enable the driver as
AM335x SoC RGMII delay mode has to be enabled in phy as mentioned
in the silicon errata Advisory 1.0.10
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
In AM335x GP EVM, Atheros 8031 phy is used, enable the driver as
AM335x SoC RGMII delay mode has to be enabled in phy as mentioned
in the silicon errata Advisory 1.0.10
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection
cpsw driver supports only selection of phy mode in control module
but control module has more setting like RGMII ID mode selection,
RMII clock source selection. So ported to cpsw-phy-sel driver
from kernel to u-boot.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
cpsw driver supports only selection of phy mode in control module
but control module has more setting like RGMII ID mode selection,
RMII clock source selection. So ported to cpsw-phy-sel driver
from kernel to u-boot.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
arm: omap: Introduce vcores_update function
This is needed in case of am57xx where in board detection is done
pretty late in the init sequence. The pmic registers for variants
of am57xx are different hence we need to assign them carefully based
on the board type. Add a function to assign omap_vcores after the
board detection is done.
Fixes: 888ea8611c1 ("ARM: dts: AM572x-IDK Initial Support")
Fixes: 1084ffa86a5 ("ARM: dts: AM571x-IDK Initial Support")
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
This is needed in case of am57xx where in board detection is done
pretty late in the init sequence. The pmic registers for variants
of am57xx are different hence we need to assign them carefully based
on the board type. Add a function to assign omap_vcores after the
board detection is done.
Fixes: 888ea8611c1 ("ARM: dts: AM572x-IDK Initial Support")
Fixes: 1084ffa86a5 ("ARM: dts: AM571x-IDK Initial Support")
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Merge branch 'master' of git://git.denx.de/u-boot into ti-u-boot-2016.05
* 'master' of git://git.denx.de/u-boot: (31 commits)
Prepare v2016.05
sunxi: Enable USB host in CHIP defconfig
test, tools: update tbot documentation
tests: py: fix NameError exception if bdi cmd is not supported
arm/arm64: Move barrier instructions into separate header
arm: socfpga: Update iomux and pll for c5 socdk RevE
warp7: Fix boot by selecting CONFIG_OF_LIBFDT
usb: gadget: dfu: discard dead code
dfu: avoid memory leak
usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA
usb: hub: Don't continue on get_port_status failure
usb: Assure Get Descriptor request is in separate microframe
usb: Wait after sending Set Configuration request
socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
mtd: cqspi: Simplify indirect read code
mtd: cqspi: Simplify indirect write code
arm: socfpga: socrates: Add 'time' command
ARM: socfpga: Disable USB OC protection on SoCrates
usb: Don't init pointer to zero, but NULL
usb: ehci-mx6: allow board_ehci_hcd_init to fail
...
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* 'master' of git://git.denx.de/u-boot: (31 commits)
Prepare v2016.05
sunxi: Enable USB host in CHIP defconfig
test, tools: update tbot documentation
tests: py: fix NameError exception if bdi cmd is not supported
arm/arm64: Move barrier instructions into separate header
arm: socfpga: Update iomux and pll for c5 socdk RevE
warp7: Fix boot by selecting CONFIG_OF_LIBFDT
usb: gadget: dfu: discard dead code
dfu: avoid memory leak
usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA
usb: hub: Don't continue on get_port_status failure
usb: Assure Get Descriptor request is in separate microframe
usb: Wait after sending Set Configuration request
socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
mtd: cqspi: Simplify indirect read code
mtd: cqspi: Simplify indirect write code
arm: socfpga: socrates: Add 'time' command
ARM: socfpga: Disable USB OC protection on SoCrates
usb: Don't init pointer to zero, but NULL
usb: ehci-mx6: allow board_ehci_hcd_init to fail
...
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Prepare v2016.05
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
sunxi: Enable USB host in CHIP defconfig
Reported-and-tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reported-and-tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
test, tools: update tbot documentation
update tbot documentation in U-Boot, as I just
merged the event system into tbots master
branch.
Signed-off-by: Heiko Schocher <hs@denx.de>
update tbot documentation in U-Boot, as I just
merged the event system into tbots master
branch.
Signed-off-by: Heiko Schocher <hs@denx.de>
tests: py: fix NameError exception if bdi cmd is not supported
test/py raises an error, if a board has not enabled bdi command
> pytest.skip('bdinfo command not supported')
E NameError: global name 'pytest' is not defined
import pytest in test/py/u_boot_utils.py fixes this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
test/py raises an error, if a board has not enabled bdi command
> pytest.skip('bdinfo command not supported')
E NameError: global name 'pytest' is not defined
import pytest in test/py/u_boot_utils.py fixes this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
ARM: DRA7: Revise DSP/IVA clock frequency update logic
The commit 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock
frequencies based on OPP") only updates the 'assigned-clock-rates'
property and expects that the 'assigned-clocks' property is already
defined in the existing DTBs. The kernel clock init configuration
logic requires both these properties to be defined in a clock
node inorder to properly update the clock frequencies. Enhance
the current frequency update logic to also add the 'assigned-clocks'
property so that the DSPEVE and IVA DPLLs are configured properly
even for kernels that do not have the OPP_NOM DPLL clock rate
configuration in the DTBs. The additional logic is a no-op for
kernels that do use DTBs with corresponding 'assigned-clocks'
property.
Signed-off-by: Suman Anna <s-anna@ti.com>
The commit 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock
frequencies based on OPP") only updates the 'assigned-clock-rates'
property and expects that the 'assigned-clocks' property is already
defined in the existing DTBs. The kernel clock init configuration
logic requires both these properties to be defined in a clock
node inorder to properly update the clock frequencies. Enhance
the current frequency update logic to also add the 'assigned-clocks'
property so that the DSPEVE and IVA DPLLs are configured properly
even for kernels that do not have the OPP_NOM DPLL clock rate
configuration in the DTBs. The additional logic is a no-op for
kernels that do use DTBs with corresponding 'assigned-clocks'
property.
Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: DRA7: Fix DSP OPP_HIGH clock rates on DRA722 SoCs
The commit 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock
frequencies based on OPP") defined different clock rates for
DSP at OPP_HIGH between DRA75x/AM572x and DRA72x/AM571x family
of SoCs. The DRA72x OPP_HIGH clock rate was based on the current
DRA72x Data Manual. The OPP_HIGH clock rate for AM571x is though
defined to be as the same as the AM572x SoCs - 750 MHz. The DRA7xx
DMs will be updated soon to mark the highest supported frequency
as 750 MHz. So, fixup the DSP OPP_HIGH clock rate accordingly.
The clock rates are also consolidated since they are identical
across all the DRA75x/AM572x, DRA72x/AM571x family of SoCs.
While at this, fix couple of minor typos, one a fix for the
IVA clock number macro in the IVA clock names definition, and
another a trace correction.
Fixes: 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock frequencies based on OPP")
Signed-off-by: Suman Anna <s-anna@ti.com>
The commit 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock
frequencies based on OPP") defined different clock rates for
DSP at OPP_HIGH between DRA75x/AM572x and DRA72x/AM571x family
of SoCs. The DRA72x OPP_HIGH clock rate was based on the current
DRA72x Data Manual. The OPP_HIGH clock rate for AM571x is though
defined to be as the same as the AM572x SoCs - 750 MHz. The DRA7xx
DMs will be updated soon to mark the highest supported frequency
as 750 MHz. So, fixup the DSP OPP_HIGH clock rate accordingly.
The clock rates are also consolidated since they are identical
across all the DRA75x/AM572x, DRA72x/AM571x family of SoCs.
While at this, fix couple of minor typos, one a fix for the
IVA clock number macro in the IVA clock names definition, and
another a trace correction.
Fixes: 539982820939 ("ARM: DRA7: Fixup DSPEVE and IVA clock frequencies based on OPP")
Signed-off-by: Suman Anna <s-anna@ti.com>
configs: remove am335x_icev2_defconfig
Now SPL will be able to select serial device dynamically, remove icev2
defconfig which is created to pass a separate serial device.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now SPL will be able to select serial device dynamically, remove icev2
defconfig which is created to pass a separate serial device.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
board: am335x: Allow to choose serial device dynamically
Different AM335x based platforms have different serial consoles. As serial
console is Kconfig option a separate defconfig has to be created for each
platform. So pass the serial device dynamically.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Different AM335x based platforms have different serial consoles. As serial
console is Kconfig option a separate defconfig has to be created for each
platform. So pass the serial device dynamically.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm/arm64: Move barrier instructions into separate header
Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.
Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.
This fixes compilation for 64-bit sunxi boards (Pine64).
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.
Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.
This fixes compilation for 64-bit sunxi boards (Pine64).
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
arm: socfpga: Update iomux and pll for c5 socdk RevE
Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
warp7: Fix boot by selecting CONFIG_OF_LIBFDT
CONFIG_OF_LIBFDT needs to be selected to avoid the following
boot problem:
reading zImage
6346216 bytes read in 118 ms (51.3 MiB/s)
Booting from mmc ...
reading imx7d-warp.dtb
32593 bytes read in 11 ms (2.8 MiB/s)
Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ]
FDT and ATAGS support not compiled in - hanging
### ERROR ### Please RESET the board ###
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
CONFIG_OF_LIBFDT needs to be selected to avoid the following
boot problem:
reading zImage
6346216 bytes read in 118 ms (51.3 MiB/s)
Booting from mmc ...
reading imx7d-warp.dtb
32593 bytes read in 11 ms (2.8 MiB/s)
Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ]
FDT and ATAGS support not compiled in - hanging
### ERROR ### Please RESET the board ###
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
ARM: dts: am335x: fix cd-gpios definition as per hardware design and dt binding docs
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In AM335x the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
As per mmc device tree binding documentation card detect gpio has
to be active low signal. When a hardware is designed with active
high card detect, gpio polarity has to be changed with
cd-inverted dt property.
In AM335x the card detect gpio is designed as active low gpio.
So correcting the dt card detect gpio definition.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
board: am335x-icev2: Don't prevent boot with older DTBs
Older DTBs might not have the pruss ethernet or cpsw ethernet nodes.
Don't prevent booting for such cases. Just print an informative message
instead.
Fixes: 154a8e6e3eb6 ("board: am335x-icev2: Support CPSW & PRUSS ethernet")
Signed-off-by: Roger Quadros <rogerq@ti.com>
Older DTBs might not have the pruss ethernet or cpsw ethernet nodes.
Don't prevent booting for such cases. Just print an informative message
instead.
Fixes: 154a8e6e3eb6 ("board: am335x-icev2: Support CPSW & PRUSS ethernet")
Signed-off-by: Roger Quadros <rogerq@ti.com>
configs: am335x-icev2: Enable HUSH parser
Enable HUSH parser for am335x-icev2
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Enable HUSH parser for am335x-icev2
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
configs: am335x-icev2: Disable NAND
NAND is not available on am335x-icev2 board. So do not enable it.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
NAND is not available on am335x-icev2 board. So do not enable it.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
am335x_evm: Switch to env on FAT SD by default, add am335x_evm_nandboot
- Re-org env sections so that we can fall back to env is in FAT on SD
card, for broader board compatibility
- Add am335x_evm_nandboot as example of NAND env
This is for the TI integration tree only as the plan for upstream is to
work towards env location being selectable via Kconfig
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
- Re-org env sections so that we can fall back to env is in FAT on SD
card, for broader board compatibility
- Add am335x_evm_nandboot as example of NAND env
This is for the TI integration tree only as the plan for upstream is to
work towards env location being selectable via Kconfig
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Merge branch 'master' of git://git.denx.de/u-boot-usb
usb: gadget: dfu: discard dead code
Reported by Coverity:
Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach this statement:
(f_dfu->strings + --i).s = ....
If calloc failed, i is still 0 and no need to call free,
so discard the dead code.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Reported by Coverity:
Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach this statement:
(f_dfu->strings + --i).s = ....
If calloc failed, i is still 0 and no need to call free,
so discard the dead code.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
dfu: avoid memory leak
When dfu_fill_entity fail, need to free dfu to avoid memory leak.
Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
When dfu_fill_entity fail, need to free dfu to avoid memory leak.
Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA
With patch c998da0d (usb: Change power-on / scanning timeout handling),
the USB scanning is started earlier and with a smaller timeout. This
resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not
getting detected any more. This patch now adds a 1 second delay (in
the host mode only) to the DWC2 driver before the scanning is started.
With this delay, now all problematic USB keys are detected successfully
again. And there is no need any more to change the delay / timeout
in the common USB code (usb_hub.c).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>
With patch c998da0d (usb: Change power-on / scanning timeout handling),
the USB scanning is started earlier and with a smaller timeout. This
resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not
getting detected any more. This patch now adds a 1 second delay (in
the host mode only) to the DWC2 driver before the scanning is started.
With this delay, now all problematic USB keys are detected successfully
again. And there is no need any more to change the delay / timeout
in the common USB code (usb_hub.c).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>
usb: hub: Don't continue on get_port_status failure
The code shouldn't continue probing the port if get_port_status() failed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
The code shouldn't continue probing the port if get_port_status() failed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
usb: Assure Get Descriptor request is in separate microframe
The Kingston DT Ultimate USB 3.0 stick is sensitive to this first
Get Descriptor request and if the request is not in a separate
microframe, the stick refuses to operate. Add slight delay, which
is enough for one microframe to pass on any USB spec revision.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
The Kingston DT Ultimate USB 3.0 stick is sensitive to this first
Get Descriptor request and if the request is not in a separate
microframe, the stick refuses to operate. Add slight delay, which
is enough for one microframe to pass on any USB spec revision.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
usb: Wait after sending Set Configuration request
Some devices, like the SanDisk Cruzer Pop need some time to process
the Set Configuration request, so wait a little until they are ready.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
Some devices, like the SanDisk Cruzer Pop need some time to process
the Set Configuration request, so wait a little until they are ready.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
Building without ethernet driver doesn't work. Fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
Building without ethernet driver doesn't work. Fix it.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
mtd: cqspi: Simplify indirect read code
The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
mtd: cqspi: Simplify indirect write code
The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.
This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.
This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
arm: socfpga: socrates: Add 'time' command
The time command is very helpful for performance and regressions tests.
So lets enable it on SoCrates.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
The time command is very helpful for performance and regressions tests.
So lets enable it on SoCrates.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
ARM: socfpga: Disable USB OC protection on SoCrates
This is mandatory, otherwise the USB does not work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
This is mandatory, otherwise the USB does not work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
usb: Don't init pointer to zero, but NULL
The pointer should always be inited to NULL, not zero (0). These are
two different things and not necessarily equal.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
The pointer should always be inited to NULL, not zero (0). These are
two different things and not necessarily equal.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
usb: ehci-mx6: allow board_ehci_hcd_init to fail
There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
While at it, that function (board_ehci_hcd_init) has actually two
documentation blocks... Use the correct function name for the
documentation block of board_usb_phy_mode.
Signed-off-by: Stefan Agner <stefan@agner.ch>
There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
While at it, that function (board_ehci_hcd_init) has actually two
documentation blocks... Use the correct function name for the
documentation block of board_usb_phy_mode.
Signed-off-by: Stefan Agner <stefan@agner.ch>
imx6: cache: disable L2 before touching Auxiliary Control Register
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
test/py: dfu: wait for USB device to go away at boot
It can take a while for a host machine to notice that a USB device has
disconnected, and process the change. At the end of the DFU test, we wait
up to 10 seconds for this to happen. This change makes the test wait the
same (up to) 10 seconds at the start of the test for any previously active
USB device-mode session to be cleaned up. Such as session might have been
used to download U-Boot into memory for example; this is certainly true
on my Tegra test systems. This changes should solve the DFU test
intermittency issues I've been seeing on some Tegra devices.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
It can take a while for a host machine to notice that a USB device has
disconnected, and process the change. At the end of the DFU test, we wait
up to 10 seconds for this to happen. This change makes the test wait the
same (up to) 10 seconds at the start of the test for any previously active
USB device-mode session to be cleaned up. Such as session might have been
used to download U-Boot into memory for example; this is certainly true
on my Tegra test systems. This changes should solve the DFU test
intermittency issues I've been seeing on some Tegra devices.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: am33xx: Fix DDR initialization delays
The current delays in the DDR initialization routines for am33xx
architectures are sometimes not running long enough leading to DDR
init errors. On am437x, this shows up as an L3 NOC error after the
kernel boots. This is due to the timer not being initialized
properly, but instead still containing the timer init values from
the boot ROM which cause timers to expire in 1/4th the time
required.
timer_init is typically not called until board_init_r, however on
am33xx/am43xx udelay is required in sdram_init which is called
from board_init_f, so a call to timer_init is required earlier.
Note that this issue introduced in v2015.01 by:
b352dde "am33xx: Drop timer_init call from s_init".
Although this could instead fixed by reverting said commit, it
would cause timer_init to be called twice in both SPL and non-SPL
cases. This gives a little more fine grained control and also
matches what is being done on omap-command and fsl-layerscape.
Signed-off-by: Russ Dill <russ.dill@ti.com>
The current delays in the DDR initialization routines for am33xx
architectures are sometimes not running long enough leading to DDR
init errors. On am437x, this shows up as an L3 NOC error after the
kernel boots. This is due to the timer not being initialized
properly, but instead still containing the timer init values from
the boot ROM which cause timers to expire in 1/4th the time
required.
timer_init is typically not called until board_init_r, however on
am33xx/am43xx udelay is required in sdram_init which is called
from board_init_f, so a call to timer_init is required earlier.
Note that this issue introduced in v2015.01 by:
b352dde "am33xx: Drop timer_init call from s_init".
Although this could instead fixed by reverting said commit, it
would cause timer_init to be called twice in both SPL and non-SPL
cases. This gives a little more fine grained control and also
matches what is being done on omap-command and fsl-layerscape.
Signed-off-by: Russ Dill <russ.dill@ti.com>
ARM: fix ifdefs in ARMv8 lowlevel_init()
Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.
In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:
- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.
An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.
Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.
In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:
- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.
An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.
Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
defconfig: k2g_evm: enable nand driver model
Enable nand driver model for k2g_evm as omap_gpmc supports
driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Enable nand driver model for k2g_evm as omap_gpmc supports
driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
ARM: dts: k2g: Add gpmc and elm nodes dtsi and dts files
Add gpmc and elm nodes to add support for nand in k2g evm.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add gpmc and elm nodes to add support for nand in k2g evm.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
keystone2: k2g: Add NAND support
k2g uses GPMC NAND instead of AEMIF/Davinci NAND.
Provide support for it.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
k2g uses GPMC NAND instead of AEMIF/Davinci NAND.
Provide support for it.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
keystone2: move platform specific NAND configs to platform specific header
Not all keystone 2 devices use Davinci NAND controller. Move the platform
specific NAND configurations into platform specific headers.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Not all keystone 2 devices use Davinci NAND controller. Move the platform
specific NAND configurations into platform specific headers.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
mtd: nand: omap: Fix build for SOC_KEYSTONE
There is no <asm/arch/mem.h> for Keystone so
don't include it for Keystone.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
There is no <asm/arch/mem.h> for Keystone so
don't include it for Keystone.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
memory: ti-gpmc: move omap gpmc driver to drivers/memory
gpmc driver is used by non OMAP SoCs from TI so move it
to a more generic location.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
gpmc driver is used by non OMAP SoCs from TI so move it
to a more generic location.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
k2g: enable GPMC/ELM module
Enabling GPMC PSC inorder to enable clocks to GPMC.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Enabling GPMC PSC inorder to enable clocks to GPMC.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
defconfig: am335x_evm: enable usb driver model
enable usb driver model for am335x evm as musb supports
driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
enable usb driver model for am335x evm as musb supports
driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
am335x_evm: enable usb ether gadget as it supports DM_ETH
Since usb ether gadget have support for driver model, so enable
usb ether gadget.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Since usb ether gadget have support for driver model, so enable
usb ether gadget.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
am33xx: board: init usb ether gadget for rndis support
Add usb ether gadget device with usb_ether_init() when
CONFIG_DM_ETH and CONFIG_USB_ETHER are defined.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add usb ether gadget device with usb_ether_init() when
CONFIG_DM_ETH and CONFIG_USB_ETHER are defined.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
drivers: usb: gadget: ether/rndis: convert driver to adopt device driver model
Adopt usb ether gadget and rndis driver to adopt driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Adopt usb ether gadget and rndis driver to adopt driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: gadget: ether: prepare driver for driver model migration
prepare driver for driver model migration
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
prepare driver for driver model migration
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: gadget: ether: use net device priv to pass usb ether priv
Use net device priv to pass usb ether priv and use it in
net device ops callback.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Use net device priv to pass usb ether priv and use it in
net device ops callback.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: gadget: ether: consolidate global devices to single struct
Consolidate the net device, usb eth device and gadget device
struct to single struct and a single global variable so that the
same can be passed as priv of ethernet driver.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Consolidate the net device, usb eth device and gadget device
struct to single struct and a single global variable so that the
same can be passed as priv of ethernet driver.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: gadget: ether: access network_started using local variable
network_started of struct eth_dev can be accessed using local
variable dev and no reason to access it with the global struct.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
network_started of struct eth_dev can be accessed using local
variable dev and no reason to access it with the global struct.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: gadget: ether: adopt to usb driver model
Convert usb ether gadget to adopt usb driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Convert usb ether gadget to adopt usb driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: musb: add ti musb peripheral driver with driver model support
Add a TI MUSB peripheral driver with driver model support and the
driver will be bound by the MUSB wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add a TI MUSB peripheral driver with driver model support and the
driver will be bound by the MUSB wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: musb: add ti musb host driver with driver model support
Add a TI MUSB host driver with driver model support and the
driver will be bound by the MUSB wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add a TI MUSB host driver with driver model support and the
driver will be bound by the MUSB wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: musb: adopt musb backend driver to driver model
Currently all backend driver ops uses hard coded physical
address, so to adopt the driver to DM, add device pointer to ops
call backs so that drivers can get physical addresses from the
usb driver priv/plat data.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Currently all backend driver ops uses hard coded physical
address, so to adopt the driver to DM, add device pointer to ops
call backs so that drivers can get physical addresses from the
usb driver priv/plat data.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
am33xx: board: probe misc drivers to register musb devices
MUSB wrapper driver is bound as MISC device and underlying usb
devices are bind to usb drivers based on dr_mode, so probing the
MISC wrapper driver to register musb devices.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
MUSB wrapper driver is bound as MISC device and underlying usb
devices are bind to usb drivers based on dr_mode, so probing the
MISC wrapper driver to register musb devices.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
drivers: usb: musb: add ti musb misc driver for wrapper
Add a misc driver for MUSB wrapper, so that based on dr_mode the
USB devices can bind to USB host or USB device drivers.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add a misc driver for MUSB wrapper, so that based on dr_mode the
USB devices can bind to USB host or USB device drivers.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
drivers: usb: common: add common code for usb drivers to use
Add common usb code which usb drivers makes use of it.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Add common usb code which usb drivers makes use of it.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
am33xx: board: do not register usb devices when CONFIG_DM_USB is defined
Do not register usb devices when CONFIG_DM_USB is define.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Do not register usb devices when CONFIG_DM_USB is define.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
configs: am335x: usb: do not define CONFIG_DM_USB for spl
Since OMAP's spl doesn't support DM currently, do not define
CONFIG_DM_USB for spl build.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Since OMAP's spl doesn't support DM currently, do not define
CONFIG_DM_USB for spl build.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
include/configs: panda: Fix `.sram' overflowed error
After adding high speed modes of MMC, the following errors
are seen with omap4_panda_defconfig.
u-boot-spl section `.data' will not fit in region `.sram'
region `.sram' overflowed by 144 bytes
Fix it for now by disabling CONFIG_SPL_EXT_SUPPORT since
EXT is unlikely to be used in SPL.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
After adding high speed modes of MMC, the following errors
are seen with omap4_panda_defconfig.
u-boot-spl section `.data' will not fit in region `.sram'
region `.sram' overflowed by 144 bytes
Fix it for now by disabling CONFIG_SPL_EXT_SUPPORT since
EXT is unlikely to be used in SPL.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
ARM: dts: dra7xx: am57xx: Enable high speed modes in MMC2
Add capabilities in MMC2 dt node to indicate it supports DDR, HS200
and HS modes. Also add iodelay values for the different MMC modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add capabilities in MMC2 dt node to indicate it supports DDR, HS200
and HS modes. Also add iodelay values for the different MMC modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
ARM: dts: am57xx: add "iov" property to mmc2
The IO lines in mmc2 is connected to 3.3v in the case of
am57xx-beagle-x15. Set the default IO voltage to 3.3v using "iov"
property.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The IO lines in mmc2 is connected to 3.3v in the case of
am57xx-beagle-x15. Set the default IO voltage to 3.3v using "iov"
property.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mmc: omap_hsmmc: Dont support HS200 and DDR modes for rev1.1
Since AM572x SR1.1 has erratas to limit the frequency of MMC1 to
96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1 and the driver
doesn't handle variable frequencies for MMC1 and MMC2, disable higher
speed modes for SR1.1
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Since AM572x SR1.1 has erratas to limit the frequency of MMC1 to
96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1 and the driver
doesn't handle variable frequencies for MMC1 and MMC2, disable higher
speed modes for SR1.1
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm
From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines
reset procedure section in TRM suggests to first poll the SRD/SRC bit
until it is set to 0x1. But looks like that bit is never set to 1 and there
is an observable delay of 1sec everytime the driver tries to reset DAT/CMD.
(The same is observed in linux kernel).
Reduce the time the driver waits for the controller to set the SRC/SRD bits
to 1 so that there is no observable delay.
TODO: Debug why the SRC/SRD bits are never set
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines
reset procedure section in TRM suggests to first poll the SRD/SRC bit
until it is set to 0x1. But looks like that bit is never set to 1 and there
is an observable delay of 1sec everytime the driver tries to reset DAT/CMD.
(The same is observed in linux kernel).
Reduce the time the driver waits for the controller to set the SRC/SRD bits
to 1 so that there is no observable delay.
TODO: Debug why the SRC/SRD bits are never set
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mmc: omap_hsmmc: Enable Auto command (CMD12) enable
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mmc: omap_hsmmc: Workaround for errata id i802
According to errata i802, DCRC error interrupts
(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.
The DCRC interrupt, occurs when the last tuning block fails
(the last ratio tested). The delay from CRC check until the
interrupt is asserted is bigger than the delay until assertion
of the tuning end flag. Assertion of tuning end flag is what
masks the interrupts. Because of this race, an erroneous DCRC
interrupt occurs.
The suggested workaround is to disable DCRC interrupts during
the tuning procedure which is implemented here.
TODO: Debug why other error interrupts are received during
tuning.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
According to errata i802, DCRC error interrupts
(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.
The DCRC interrupt, occurs when the last tuning block fails
(the last ratio tested). The delay from CRC check until the
interrupt is asserted is bigger than the delay until assertion
of the tuning end flag. Assertion of tuning end flag is what
masks the interrupts. Because of this race, an erroneous DCRC
interrupt occurs.
The suggested workaround is to disable DCRC interrupts during
the tuning procedure which is implemented here.
TODO: Debug why other error interrupts are received during
tuning.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mmc: omap_hsmmc: Add support to set IODELAY values
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met.
Add support to parse mux values and iodelay values from device tree
and set these depending on the enumerated MMC mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met.
Add support to parse mux values and iodelay values from device tree
and set these depending on the enumerated MMC mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
dm: core: compatible match should be in the order in which it is populated in dt
Find the compatible string match based on the order in which
it is populated in the device tree node rather than matching
based on the order in which it is populated in the drivers match
table.
This is required in order to get the right driver data.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Find the compatible string match based on the order in which
it is populated in the device tree node rather than matching
based on the order in which it is populated in the drivers match
table.
This is required in order to get the right driver data.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot
Add a new API to perform iodelay recalibration without isolate
io to be used in uboot.
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met. The MMC driver can use the new API to
set the IO delay values depending on the MMC mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add a new API to perform iodelay recalibration without isolate
io to be used in uboot.
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met. The MMC driver can use the new API to
set the IO delay values depending on the MMC mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
ARM: OMAP5: set mmc clock frequency to 192MHz
Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mmc: omap_hsmmc: Enable ADMA2
omap hsmmc host controller has ADMA2 feature. Enable it here
for better read and write throughput.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
omap hsmmc host controller has ADMA2 feature. Enable it here
for better read and write throughput.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
drivers: mmc: omap_hsmmc: use mmc_of_parse to populate mmc_config
Use the mmc_of_parse library function to populate mmc_config instead of
repeating the same code in host controller driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Use the mmc_of_parse library function to populate mmc_config instead of
repeating the same code in host controller driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>