1 /*
2 * Copyright (c) 2013-2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== custom_rsc_table_vayu_ipu.h ========
35 *
36 * Define the VAYU/DRA7xx custom resource table entries for all IPU cores. This will be
37 * incorporated into corresponding base images, and used by the remoteproc
38 * on the host-side to allocated/reserve resources.
39 *
40 */
42 #ifndef __CUSTOM_RSC_TABLE_VAYU_IPU_H__
43 #define __CUSTOM_RSC_TABLE_VAYU_IPU_H__
45 #include <ti/ipc/remoteproc/rsc_types.h>
47 /* IPU Memory Map */
48 #define L4_DRA7XX_BASE 0x4A000000
50 /* L4_CFG & L4_WKUP */
51 #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
52 #define IPU_PERIPHERAL_L4CFG 0x6A000000
54 #define L4_PERIPHERAL_L4PER1 0x48000000
55 #define IPU_PERIPHERAL_L4PER1 0x68000000
57 #define L4_PERIPHERAL_L4PER2 0x48400000
58 #define IPU_PERIPHERAL_L4PER2 0x68400000
60 #define L4_PERIPHERAL_L4PER3 0x48800000
61 #define IPU_PERIPHERAL_L4PER3 0x68800000
63 #define L4_PERIPHERAL_L4EMU 0x54000000
64 #define IPU_PERIPHERAL_L4EMU 0x74000000
66 #define L3_PERIPHERAL_DMM 0x4E000000
67 #define IPU_PERIPHERAL_DMM 0x6E000000
69 #define L3_IVAHD_CONFIG 0x5A000000
70 #define IPU_IVAHD_CONFIG 0x7A000000
72 #define L3_IVAHD_SL2 0x5B000000
73 #define IPU_IVAHD_SL2 0x7B000000
75 #define L3_TILER_MODE_0_1 0x60000000
76 #define IPU_TILER_MODE_0_1 0xA0000000
78 #define L3_TILER_MODE_2 0x70000000
79 #define IPU_TILER_MODE_2 0xB0000000
81 #define L3_TILER_MODE_3 0x78000000
82 #define IPU_TILER_MODE_3 0xB8000000
84 #define IPU_MEM_TEXT 0x0
85 #define IPU_MEM_DATA 0x80000000
87 #define IPU_MEM_IPC_DATA 0x9F000000
88 #define IPU_MEM_IPC_VRING 0x60000000
89 #define IPU_MEM_RPMSG_VRING0 0x60000000
90 #define IPU_MEM_RPMSG_VRING1 0x60004000
91 #define IPU_MEM_VRING_BUFS0 0x60040000
92 #define IPU_MEM_VRING_BUFS1 0x60080000
94 #define IPU_MEM_IPC_VRING_SIZE SZ_1M
95 #define IPU_MEM_IPC_DATA_SIZE SZ_1M
97 #define IPU_MEM_TEXT_SIZE (SZ_1M * 6)
99 /*
100 * IPU_MEM_DATA_SIZE contains the size of EXT_DATA + EXT_HEAP
101 * defined in the dce_ipu.cfg
102 */
103 #define IPU_MEM_DATA_SIZE (SZ_1M * 43)
105 /*
106 * Assign fixed RAM addresses to facilitate a fixed MMU table.
107 * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
108 */
109 /* See CMA BASE addresses in Linux side (for 3.8 & 3.12 kernels):
110 arch/arm/mach-omap2/remoteproc.c */
111 /* For 3.14 kernels version and above, look for CMA reserved memory node in
112 the board dts file. */
113 #define PHYS_MEM_IPC_VRING 0x95800000
115 /*
116 * Sizes of the virtqueues (expressed in number of buffers supported,
117 * and must be power of 2)
118 */
119 #define IPU_RPMSG_VQ0_SIZE 256
120 #define IPU_RPMSG_VQ1_SIZE 256
122 /* flip up bits whose indices represent features we support */
123 #define RPMSG_IPU_C0_FEATURES 1
125 struct my_resource_table {
126 struct resource_table base;
128 UInt32 offset[17]; /* Should match 'num' in actual definition */
130 /* rpmsg vdev entry */
131 struct fw_rsc_vdev rpmsg_vdev;
132 struct fw_rsc_vdev_vring rpmsg_vring0;
133 struct fw_rsc_vdev_vring rpmsg_vring1;
135 /* text carveout entry */
136 struct fw_rsc_carveout text_cout;
138 /* data carveout entry */
139 struct fw_rsc_carveout data_cout;
141 /* ipcdata carveout entry */
142 struct fw_rsc_carveout ipcdata_cout;
144 /* trace entry */
145 struct fw_rsc_trace trace;
147 /* devmem entry */
148 struct fw_rsc_devmem devmem0;
150 /* devmem entry */
151 struct fw_rsc_devmem devmem1;
153 /* devmem entry */
154 struct fw_rsc_devmem devmem2;
156 /* devmem entry */
157 struct fw_rsc_devmem devmem3;
159 /* devmem entry */
160 struct fw_rsc_devmem devmem4;
162 /* devmem entry */
163 struct fw_rsc_devmem devmem5;
165 /* devmem entry */
166 struct fw_rsc_devmem devmem6;
168 /* devmem entry */
169 struct fw_rsc_devmem devmem7;
171 /* devmem entry */
172 struct fw_rsc_devmem devmem8;
174 /* devmem entry */
175 struct fw_rsc_devmem devmem9;
177 /* devmem entry */
178 struct fw_rsc_devmem devmem10;
180 /* devmem entry */
181 struct fw_rsc_devmem devmem11;
182 };
184 extern char ti_trace_SysMin_Module_State_0_outbuf__A;
185 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
187 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
188 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
190 struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
191 1, /* we're the first version that implements this */
192 17, /* number of entries in the table */
193 0, 0, /* reserved, must be zero */
194 /* offsets to entries */
195 {
196 offsetof(struct my_resource_table, rpmsg_vdev),
197 offsetof(struct my_resource_table, text_cout),
198 offsetof(struct my_resource_table, data_cout),
199 offsetof(struct my_resource_table, ipcdata_cout),
200 offsetof(struct my_resource_table, trace),
201 offsetof(struct my_resource_table, devmem0),
202 offsetof(struct my_resource_table, devmem1),
203 offsetof(struct my_resource_table, devmem2),
204 offsetof(struct my_resource_table, devmem3),
205 offsetof(struct my_resource_table, devmem4),
206 offsetof(struct my_resource_table, devmem5),
207 offsetof(struct my_resource_table, devmem6),
208 offsetof(struct my_resource_table, devmem7),
209 offsetof(struct my_resource_table, devmem8),
210 offsetof(struct my_resource_table, devmem9),
211 offsetof(struct my_resource_table, devmem10),
212 offsetof(struct my_resource_table, devmem11),
213 },
215 /* rpmsg vdev entry */
216 {
217 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
218 RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
219 /* no config data */
220 },
221 /* the two vrings */
222 { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 },
223 { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },
225 {
226 TYPE_CARVEOUT,
227 IPU_MEM_TEXT, 0,
228 IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
229 },
231 {
232 TYPE_CARVEOUT,
233 IPU_MEM_DATA, 0,
234 IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA",
235 },
237 {
238 TYPE_CARVEOUT,
239 IPU_MEM_IPC_DATA, 0,
240 IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA",
241 },
243 {
244 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3",
245 },
247 {
248 TYPE_DEVMEM,
249 IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
250 IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING",
251 },
253 {
254 TYPE_DEVMEM,
255 IPU_TILER_MODE_0_1, L3_TILER_MODE_0_1,
256 SZ_256M, 0, 0, "IPU_TILER_MODE_0_1",
257 },
259 {
260 TYPE_DEVMEM,
261 IPU_TILER_MODE_2, L3_TILER_MODE_2,
262 SZ_128M, 0, 0, "IPU_TILER_MODE_2",
263 },
265 {
266 TYPE_DEVMEM,
267 IPU_TILER_MODE_3, L3_TILER_MODE_3,
268 SZ_128M, 0, 0, "IPU_TILER_MODE_3",
269 },
271 {
272 TYPE_DEVMEM,
273 IPU_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
274 SZ_16M, 0, 0, "IPU_PERIPHERAL_L4CFG",
275 },
277 {
278 TYPE_DEVMEM,
279 IPU_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
280 SZ_2M, 0, 0, "IPU_PERIPHERAL_L4PER1",
281 },
283 {
284 TYPE_DEVMEM,
285 IPU_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
286 SZ_4M, 0, 0, "IPU_PERIPHERAL_L4PER2",
287 },
289 {
290 TYPE_DEVMEM,
291 IPU_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
292 SZ_8M, 0, 0, "IPU_PERIPHERAL_L4PER3",
293 },
295 {
296 TYPE_DEVMEM,
297 IPU_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
298 SZ_16M, 0, 0, "IPU_PERIPHERAL_L4EMU",
299 },
301 {
302 TYPE_DEVMEM,
303 IPU_IVAHD_CONFIG, L3_IVAHD_CONFIG,
304 SZ_16M, 0, 0, "IPU_IVAHD_CONFIG",
305 },
307 {
308 TYPE_DEVMEM,
309 IPU_IVAHD_SL2, L3_IVAHD_SL2,
310 SZ_16M, 0, 0, "IPU_IVAHD_SL2",
311 },
313 {
314 TYPE_DEVMEM,
315 IPU_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
316 SZ_1M, 0, 0, "IPU_PERIPHERAL_DMM",
317 },
318 };
320 #endif /* __CUSTOM_RSC_TABLE_VAYU_IPU_H__ */