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raw | patch | inline | side by side (parent: 8097011)
| author | Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de> | |
| Thu, 9 May 2019 16:52:26 +0000 (18:52 +0200) | ||
| committer | Jan Kiszka <jan.kiszka@siemens.com> | |
| Sun, 12 May 2019 08:00:08 +0000 (10:00 +0200) |
Some sugar for the guidance of the reader. Use speaking name instead of
hard-coded constants.
This patch was supported by:
$ git grep -l "\.id = 0x1" | xargs sed -i 's/id = 0x1,/id = PCI_CAP_ID_PM,/'
$ git grep -l "\.id = 0x3" | xargs sed -i 's/id = 0x3,/id = PCI_CAP_ID_VPD,/'
$ git grep -l "\.id = 0x5" | xargs sed -i 's/id = 0x5,/id = PCI_CAP_ID_MSI,/'
$ git grep -l "\.id = 0x8" | xargs sed -i 's/id = 0x8,/id = PCI_CAP_ID_HT,/'
$ git grep -l "\.id = 0x9" | xargs sed -i 's/id = 0x9,/id = PCI_CAP_ID_VNDR,/'
$ git grep -l "\.id = 0xa" | xargs sed -i 's/id = 0xa,/id = PCI_CAP_ID_DBG,/'
$ git grep -l "\.id = 0xd" | xargs sed -i 's/id = 0xd,/id = PCI_CAP_ID_SSVID,/'
$ git grep -l "\.id = 0xf" | xargs sed -i 's/id = 0xf,/id = PCI_CAP_ID_SECDEV,/'
$ git grep -l "\.id = 0x10" | xargs sed -i 's/id = 0x10,/id = PCI_CAP_ID_EXP,/'
$ git grep -l "\.id = 0x11" | xargs sed -i 's/id = 0x11,/id = PCI_CAP_ID_MSIX,/'
$ git grep -l "\.id = 0x12" | xargs sed -i 's/id = 0x12,/id = PCI_CAP_ID_SATA,/'
$ git grep -l "\.id = 0x13" | xargs sed -i 's/id = 0x13,/id = PCI_CAP_ID_AF,/'
Extended cap ids were manually replaced.
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
hard-coded constants.
This patch was supported by:
$ git grep -l "\.id = 0x1" | xargs sed -i 's/id = 0x1,/id = PCI_CAP_ID_PM,/'
$ git grep -l "\.id = 0x3" | xargs sed -i 's/id = 0x3,/id = PCI_CAP_ID_VPD,/'
$ git grep -l "\.id = 0x5" | xargs sed -i 's/id = 0x5,/id = PCI_CAP_ID_MSI,/'
$ git grep -l "\.id = 0x8" | xargs sed -i 's/id = 0x8,/id = PCI_CAP_ID_HT,/'
$ git grep -l "\.id = 0x9" | xargs sed -i 's/id = 0x9,/id = PCI_CAP_ID_VNDR,/'
$ git grep -l "\.id = 0xa" | xargs sed -i 's/id = 0xa,/id = PCI_CAP_ID_DBG,/'
$ git grep -l "\.id = 0xd" | xargs sed -i 's/id = 0xd,/id = PCI_CAP_ID_SSVID,/'
$ git grep -l "\.id = 0xf" | xargs sed -i 's/id = 0xf,/id = PCI_CAP_ID_SECDEV,/'
$ git grep -l "\.id = 0x10" | xargs sed -i 's/id = 0x10,/id = PCI_CAP_ID_EXP,/'
$ git grep -l "\.id = 0x11" | xargs sed -i 's/id = 0x11,/id = PCI_CAP_ID_MSIX,/'
$ git grep -l "\.id = 0x12" | xargs sed -i 's/id = 0x12,/id = PCI_CAP_ID_SATA,/'
$ git grep -l "\.id = 0x13" | xargs sed -i 's/id = 0x13,/id = PCI_CAP_ID_AF,/'
Extended cap ids were manually replaced.
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
| configs/x86/e1000-demo.c | patch | blob | history | |
| configs/x86/f2a88xm-hd3.c | patch | blob | history | |
| configs/x86/imb-a180.c | patch | blob | history | |
| configs/x86/linux-x86-demo.c | patch | blob | history | |
| configs/x86/pci-demo.c | patch | blob | history | |
| configs/x86/qemu-x86.c | patch | blob | history | |
| include/jailhouse/cell-config.h | patch | blob | history | |
| include/jailhouse/pci_defs.h | [new file with mode: 0644] | patch | blob |
index 09ca9eac881b9bc2188e2c070b4f29b82dc98b3d..814f13ed467eb69837024a1fc984563f643838c9 100644 (file)
--- a/configs/x86/e1000-demo.c
+++ b/configs/x86/e1000-demo.c
.pci_caps = {
{ /* Intel e1000 @00:19.0 */
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0xd0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
index e73cbb063c75c3761c63e44d7885ae99fc039f6f..315d0e29b78840927637fa4a202806f84618579c 100644 (file)
.pci_caps = {
/* PCIDevice: 00:00.2 */
{
- .id = 0xf,
+ .id = PCI_CAP_ID_SECDEV,
.start = 0x40,
.len = 2,
.flags = 0,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x54,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x8,
+ .id = PCI_CAP_ID_HT,
.start = 0x64,
.len = 2,
.flags = 0,
/* PCIDevice: 00:01.0 */
/* PCIDevice: 00:01.1 */
{
- .id = 0x9,
+ .id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 2,
.flags = 0,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 00:03.1 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 2,
.flags = 0,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0xd,
+ .id = PCI_CAP_ID_SSVID,
.start = 0xb0,
.len = 2,
.flags = 0,
},
{
- .id = 0x8,
+ .id = PCI_CAP_ID_HT,
.start = 0xb8,
.len = 2,
.flags = 0,
/* PCIDevice: 00:10.0 */
/* PCIDevice: 00:10.1 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x70,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x11,
+ .id = PCI_CAP_ID_MSIX,
.start = 0x90,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0xa0,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:11.0 */
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x12,
+ .id = PCI_CAP_ID_SATA,
.start = 0x70,
.len = 2,
.flags = 0,
/* PCIDevice: 00:12.2 */
/* PCIDevice: 00:13.2 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0xc0,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0xa,
+ .id = PCI_CAP_ID_DBG,
.start = 0xe4,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:14.2 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 00:18.3 */
{
- .id = 0xf,
+ .id = PCI_CAP_ID_SECDEV,
.start = 0xf0,
.len = 2,
.flags = 0,
},
/* PCIDevice: 01:00.0 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x40,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0x70,
.len = 2,
.flags = 0,
},
{
- .id = 0x11,
+ .id = PCI_CAP_ID_MSIX,
.start = 0xb0,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x3,
+ .id = PCI_CAP_ID_VPD,
.start = 0xd0,
.len = 2,
.flags = 0,
diff --git a/configs/x86/imb-a180.c b/configs/x86/imb-a180.c
index 4faa0b41a39fa2ba8fb3c48dec6da2d13aa4da91..e0d86e3af12fd8b4589863eab3984bac3c70b950 100644 (file)
--- a/configs/x86/imb-a180.c
+++ b/configs/x86/imb-a180.c
/* PCIDevice: 00:01.0 */
/* PCIDevice: 00:01.1 */
{
- .id = 0x9,
+ .id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 2,
.flags = 0,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
/* PCIDevice: 00:02.3 */
/* PCIDevice: 00:02.4 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 2,
.flags = 0,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0xd,
+ .id = PCI_CAP_ID_SSVID,
.start = 0xb0,
.len = 2,
.flags = 0,
},
{
- .id = 0x8,
+ .id = PCI_CAP_ID_HT,
.start = 0xb8,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:10.0 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x70,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x11,
+ .id = PCI_CAP_ID_MSIX,
.start = 0x90,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0xa0,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:11.0 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x60,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x12,
+ .id = PCI_CAP_ID_SATA,
.start = 0x70,
.len = 2,
.flags = 0,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x13,
+ .id = PCI_CAP_ID_AF,
.start = 0xd0,
.len = 2,
.flags = 0,
/* PCIDevice: 00:12.2 */
/* PCIDevice: 00:13.2 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0xc0,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0xa,
+ .id = PCI_CAP_ID_DBG,
.start = 0xe4,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:14.2 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 00:18.3 */
{
- .id = 0xf,
+ .id = PCI_CAP_ID_SECDEV,
.start = 0xf0,
.len = 2,
.flags = 0,
/* PCIDevice: 01:00.3 */
/* PCIDevice: 02:00.0 */
{
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0x40,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0x70,
.len = 2,
.flags = 0,
},
{
- .id = 0x11,
+ .id = PCI_CAP_ID_MSIX,
.start = 0xb0,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x3,
+ .id = PCI_CAP_ID_VPD,
.start = 0xd0,
.len = 2,
.flags = 0,
index c8f18701bd569d2b4cca0678ed82dbbc55f7a1fb..cb89ec0a1e05d5afd3785c49163cd2aadbd95097 100644 (file)
.pci_caps = {
{ /* e1000e */
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0xc8,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0xd0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0xe0,
.len = 20,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x11,
+ .id = PCI_CAP_ID_MSIX,
.start = 0xa0,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x1 | JAILHOUSE_PCI_EXT_CAP,
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
- .id = 0x3 | JAILHOUSE_PCI_EXT_CAP,
+ .id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP,
.start = 0x140,
.len = 4,
.flags = 0,
diff --git a/configs/x86/pci-demo.c b/configs/x86/pci-demo.c
index 0b8c1aadb26552b8dbca75cf1d8256ee88b9b4c4..c7a5527aac9927b2b1dc97f929b1cd8ba8e4ff47 100644 (file)
--- a/configs/x86/pci-demo.c
+++ b/configs/x86/pci-demo.c
.pci_caps = {
{ /* Intel HDA @00:1b.0 */
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x60,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
diff --git a/configs/x86/qemu-x86.c b/configs/x86/qemu-x86.c
index 4d671cb2a00c6cb4e0014f117baaded162e3d0d8..fdfa8915858c8dfb415eaf67b94130040325daf7 100644 (file)
--- a/configs/x86/qemu-x86.c
+++ b/configs/x86/qemu-x86.c
.pci_caps = {
{ /* ICH HD audio */
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x60,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{ /* AHCI */
- .id = 0x12,
+ .id = PCI_CAP_ID_SATA,
.start = 0xa8,
.len = 2,
.flags = 0,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0x80,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{ /* virtio-9p-pci */
- .id = 0x11,
+ .id = PCI_CAP_ID_MSIX,
.start = 0x98,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{ /* e1000e */
- .id = 0x1,
+ .id = PCI_CAP_ID_PM,
.start = 0xc8,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x5,
+ .id = PCI_CAP_ID_MSI,
.start = 0xd0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x10,
+ .id = PCI_CAP_ID_EXP,
.start = 0xe0,
.len = 20,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x11,
+ .id = PCI_CAP_ID_MSIX,
.start = 0xa0,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
- .id = 0x1 | JAILHOUSE_PCI_EXT_CAP,
+ .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
- .id = 0x3 | JAILHOUSE_PCI_EXT_CAP,
+ .id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP,
.start = 0x140,
.len = 4,
.flags = 0,
index 63eb5fa5bb51b78f7849d95a6a39d3093c38949d..5739f332d8b77d053b8b06dee87cd34902dcd22a 100644 (file)
#define _JAILHOUSE_CELL_CONFIG_H
#include <jailhouse/console.h>
+#include <jailhouse/pci_defs.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
diff --git a/include/jailhouse/pci_defs.h b/include/jailhouse/pci_defs.h
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) OTH Regensburg, 2019
+ *
+ * Authors:
+ * Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ * Alternatively, you can use or redistribute this file under the following
+ * BSD license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define PCI_CAP_ID_PM 0x01 /* Power Management */
+#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
+#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
+#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
+#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
+#define PCI_CAP_ID_DBG 0x0A /* Debug port */
+#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
+#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
+#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
+#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
+#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
+#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
+
+#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
+#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */