rm-cfg: j721e: Partition generic IR resource across core0/core1 ti2019.06 ti2019.06-rc5 ti2020-rc1 ti2020.00-rc1
| author | Nikhil Devshatwar <nikhil.nd@ti.com> | |
| Thu, 23 Jan 2020 19:31:39 +0000 (01:01 +0530) | ||
| committer | Lokesh Vutla <lokeshvutla@ti.com> | |
| Fri, 24 Jan 2020 15:06:29 +0000 (20:36 +0530) | ||
| commit | 642da4e2a01ea5d8a553ae0d674839cd5e0715b9 | |
| tree | 0edabe9a926203b78f780c31ca62e4bdc1d5c3b3 | tree | snapshot (tar.xz tar.gz zip) |
| parent | f91482582808377f850866375d92638ae4c284eb | commit | diff |
rm-cfg: j721e: Partition generic IR resource across core0/core1
Main NAVSS interrupt router for MCU R5 subsystem is shared between
both CPU cores.
However, SYSFW models them to core specific devices where it
appears that the interrupt router is dedicated for each core.
MCU NAVSS IR is dedicated per MCU core but main NAVSS IR is not.
Due to this, drivers calling GET_RANGE gets the same range on
both cores, causing conflict in the interrupt partitioning.
Fix this by partitioning the shared interrupt pool between
MCU R5 core0 and core1.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Main NAVSS interrupt router for MCU R5 subsystem is shared between
both CPU cores.
However, SYSFW models them to core specific devices where it
appears that the interrupt router is dedicated for each core.
MCU NAVSS IR is dedicated per MCU core but main NAVSS IR is not.
Due to this, drivers calling GET_RANGE gets the same range on
both cores, causing conflict in the interrupt partitioning.
Fix this by partitioning the shared interrupt pool between
MCU R5 core0 and core1.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
| soc/j721e/evm/rm-cfg.c | diff | blob | history |