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raw | patch | inline | side by side (parent: 93c0ee5)
raw | patch | inline | side by side (parent: 93c0ee5)
| author | Dave Gerlach <d-gerlach@ti.com> | |
| Fri, 3 Apr 2020 03:01:21 +0000 (22:01 -0500) | ||
| committer | Dave Gerlach <d-gerlach@ti.com> | |
| Wed, 22 Apr 2020 14:24:38 +0000 (09:24 -0500) |
Update the AM65x SR2 RM board configuration to use ABI 3.0 resource type
definitions.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
definitions.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| include/soc/am65x_sr2/resasg_types.h | patch | blob | history | |
| soc/am65x_sr2/evm/rm-cfg.c | patch | blob | history | |
| soc/am65x_sr2/evm/sysfw_img_cfg.h | patch | blob | history |
index 91646d614f18606c6a606b3f77c8f7a1bc177f3b..c76590a4f9b01bfe58cc18204731db65fc32eb12 100644 (file)
#define RESASG_SUBTYPES_IA_CNT (0x0004U)
/**
- * IRQ subtypes definitions
+ * IR subtypes definitions
*/
-#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0003U)
-#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0000U)
-#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0004U)
-#define RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0 (0x0002U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0 (0x0003U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0 (0x0000U)
-#define RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0004U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0005U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0006U)
-#define RESASG_SUBTYPE_NAVSS0_CPTS0_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0007U)
-#define RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_PCIE1_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U)
-#define RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U)
-#define RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0 (0x0003U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0004U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0005U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0 (0x0007U)
-#define RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0 (0x0006U)
-#define RESASG_SUBTYPE_WKUP_DMSC0_CORTEX_M3_0_NVIC_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0000U)
-#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0001U)
-#define RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0 (0x0002U)
-#define RESASG_SUBTYPES_IRQ_CNT (0x003AU)
+#define RESASG_SUBTYPE_IR_OUTPUT (0x0000U)
+#define RESASG_SUBTYPES_IR_CNT (0x0001U)
/**
* Proxy subtypes definitions
/**
* Total number of unique resource types for SoC
*/
-#define RESASG_UTYPE_CNT 102U
+#define RESASG_UTYPE_CNT 52U
#endif /* RESASG_TYPES_H */
index 71927b30cb43ebedceefad826b7a73d9ba0e54ac..1894ac1c11db068a3ce6324dc7045d76fa56642a 100644 (file)
/*
* K3 System Firmware Resource Management Configuration Data
*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Andreas Dannenberg <dannenberg@ti.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
{
.start_resource = 16,
.num_resource = 240,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_IA_VINT),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0,
+ RESASG_SUBTYPE_IA_VINT),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 16,
.num_resource = 4592,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMASS_INTA0,
+ RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 0,
.num_resource = 64,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_IA_VINT),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0,
+ RESASG_SUBTYPE_IA_VINT),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 20480,
.num_resource = 1024,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA0,
+ RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 0,
.num_resource = 64,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_IA_VINT),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1,
+ RESASG_SUBTYPE_IA_VINT),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 22528,
.num_resource = 1024,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_MODSS_INTA1,
+ RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 8,
.num_resource = 248,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_IA_VINT),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
+ RESASG_SUBTYPE_IA_VINT),
.host_id = HOST_ID_R5_0,
},
{
.start_resource = 16392,
.num_resource = 992,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
+ RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
.host_id = HOST_ID_R5_0,
},
{
.start_resource = 17384,
.num_resource = 536,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0, RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_AGGR_0,
+ RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
.host_id = HOST_ID_R5_0,
},
{
.start_resource = 49152,
.num_resource = 1024,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 1,
.num_resource = 7,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_TX_HCHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 8,
.num_resource = 112,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_TX_CHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 120,
.num_resource = 32,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_ECHAN),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_TX_ECHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 2,
.num_resource = 6,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_HCHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 8,
.num_resource = 142,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_CHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 150,
.num_resource = 150,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 0,
.num_resource = 1,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 56320,
.num_resource = 256,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 0,
.num_resource = 2,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_HCHAN),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_TX_HCHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 2,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_TX_CHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 0,
.num_resource = 2,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_HCHAN),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_HCHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 2,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_CHAN),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 48,
.num_resource = 48,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 2,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_TX_CHAN),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_TX_CHAN),
.host_id = HOST_ID_R5_1,
},
{
.start_resource = 2,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_CHAN),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_CHAN),
.host_id = HOST_ID_R5_1,
},
{
.start_resource = 48,
.num_resource = 48,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
.host_id = HOST_ID_R5_1,
},
{
.start_resource = 0,
.num_resource = 1,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0, RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_UDMAP0,
+ RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 1,
.num_resource = 7,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_TX_H),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 8,
.num_resource = 112,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX),
- .host_id = HOST_ID_A53_2,
- },
- {
- .start_resource = 120,
- .num_resource = 32,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_TX),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 153,
.num_resource = 7,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_RX_H),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 160,
.num_resource = 142,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_RX),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 304,
.num_resource = 464,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_GP),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 0,
.num_resource = 1,
- .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES),
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_ERROR_OES),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 0,
.num_resource = 2,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_TX_H),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 2,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_TX),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 48,
.num_resource = 2,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_RX_H),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 50,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_RX),
.host_id = HOST_ID_A53_2,
},
{
.start_resource = 96,
.num_resource = 160,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_GP),
.host_id = HOST_ID_A53_2,
},
- {
- .start_resource = 0,
- .num_resource = 2,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX_H),
- .host_id = HOST_ID_R5_1,
- },
{
.start_resource = 2,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_TX),
- .host_id = HOST_ID_R5_1,
- },
- {
- .start_resource = 48,
- .num_resource = 2,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX_H),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_TX),
.host_id = HOST_ID_R5_1,
},
{
.start_resource = 50,
.num_resource = 46,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_UDMAP_RX),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_UDMAP_RX),
.host_id = HOST_ID_R5_1,
},
{
.start_resource = 96,
.num_resource = 160,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_GP),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_GP),
.host_id = HOST_ID_R5_1,
},
{
.start_resource = 0,
.num_resource = 1,
- .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0, RESASG_SUBTYPE_RA_ERROR_OES),
- .host_id = HOST_ID_A53_2,
- },
- {
- .start_resource = 80,
- .num_resource = 48,
- .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_RINGACC0,
+ RESASG_SUBTYPE_RA_ERROR_OES),
.host_id = HOST_ID_A53_2,
},
{
- .start_resource = 392,
+ .type = RESASG_UTYPE(AM6_DEV_CMPEVENT_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
.num_resource = 32,
- .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
- .host_id = HOST_ID_A53_2,
- },
- {
- .start_resource = 448,
- .num_resource = 50,
- .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0),
- .host_id = HOST_ID_A53_2,
- },
- {
- .start_resource = 498,
- .num_resource = 6,
- .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0),
- .host_id = HOST_ID_A53_2,
- },
- {
- .start_resource = 544,
- .num_resource = 16,
- .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0),
.host_id = HOST_ID_A53_2,
},
{
- .start_resource = 712,
- .num_resource = 16,
- .type = RESASG_UTYPE(AM6_DEV_GIC0, RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
- .host_id = HOST_ID_A53_2,
- },
- {
- .start_resource = 68,
- .num_resource = 28,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
+ .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_LVL_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
+ .num_resource = 64,
.host_id = HOST_ID_R5_0,
},
{
- .start_resource = 124,
- .num_resource = 16,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
+ .type = RESASG_UTYPE(AM6_DEV_MAIN2MCU_PLS_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
+ .num_resource = 48,
.host_id = HOST_ID_R5_0,
},
{
- .start_resource = 160,
+ .type = RESASG_UTYPE(AM6_DEV_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
.num_resource = 32,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
- .host_id = HOST_ID_R5_0,
- },
- {
- .start_resource = 224,
- .num_resource = 48,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU0, RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
- .host_id = HOST_ID_R5_0,
+ .host_id = HOST_ID_A53_2,
},
{
- .start_resource = 68,
- .num_resource = 28,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
- .host_id = HOST_ID_R5_0,
+ .type = RESASG_UTYPE(AM6_DEV_TIMESYNC_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
+ .num_resource = 40,
+ .host_id = HOST_ID_A53_2,
},
{
- .start_resource = 124,
+ .type = RESASG_UTYPE(AM6_DEV_WKUP_GPIOMUX_INTRTR0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 0,
.num_resource = 16,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
- .host_id = HOST_ID_R5_0,
+ .host_id = HOST_ID_A53_2,
},
{
- .start_resource = 192,
- .num_resource = 32,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
- .host_id = HOST_ID_R5_2,
+ .type = RESASG_UTYPE(AM6_DEV_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 16,
+ .num_resource = 136,
+ .host_id = HOST_ID_A53_2,
},
{
- .start_resource = 224,
- .num_resource = 48,
- .type = RESASG_UTYPE(AM6_DEV_MCU_ARMSS0_CPU1, RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
+ .type = RESASG_UTYPE(AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0, RESASG_SUBTYPE_IR_OUTPUT),
+ .start_resource = 4,
+ .num_resource = 28,
.host_id = HOST_ID_R5_0,
},
- {
- .start_resource = 46,
- .num_resource = 8,
- .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG0, RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
- .host_id = HOST_ID_ICSSG_0,
- },
- {
- .start_resource = 88,
- .num_resource = 8,
- .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG0, RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
- .host_id = HOST_ID_ICSSG_0,
- },
- {
- .start_resource = 46,
- .num_resource = 8,
- .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG1, RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
- .host_id = HOST_ID_ICSSG_1,
- },
- {
- .start_resource = 88,
- .num_resource = 8,
- .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG1, RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
- .host_id = HOST_ID_ICSSG_1,
- },
- {
- .start_resource = 46,
- .num_resource = 8,
- .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG2, RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
- .host_id = HOST_ID_ICSSG_2,
- },
- {
- .start_resource = 88,
- .num_resource = 8,
- .type = RESASG_UTYPE(AM6_DEV_PRU_ICSSG2, RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
- .host_id = HOST_ID_ICSSG_2,
- },
},
};
index 20436944180394a2780373a3f7822cb098a2d2db..a69f6c6d37338344bb44c9ff4a0b63efa48e1d44 100644 (file)
#ifndef SYSFW_IMG_CFG_H
#define SYSFW_IMG_CFG_H
-#define BOARDCFG_RM_RESASG_ENTRIES 65
+#define BOARDCFG_RM_RESASG_ENTRIES 50
#endif /* SYSFW_IMG_CFG_H */