soc/am62x/am62x_sec_proxy_info.c

   1 /*
   2  * AM62X Sec Proxy Info
   3  *
   4  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  *
  13  *    Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the
  16  *    distribution.
  17  *
  18  *    Neither the name of Texas Instruments Incorporated nor the names of
  19  *    its contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <tisci.h>
  36 #include <socinfo.h>
  37
  38 struct ti_sci_sec_proxy_info am62x_main_sp_info[] = {
  39         [0] = {70, "read", 35, "DM", "nonsec_low_priority_rx"},
  40         [1] = {69, "write", 11, "DM", "nonsec_MAIN_0_R5_1_response_tx"},
  41         [2] = {68, "write", 2, "DM", "nonsec_MAIN_0_R5_3_response_tx"},
  42         [3] = {67, "write", 6, "DM", "nonsec_A53_1_response_tx"},
  43         [4] = {66, "write", 6, "DM", "nonsec_A53_2_response_tx"},
  44         [5] = {65, "write", 6, "DM", "nonsec_A53_3_response_tx"},
  45         [6] = {64, "write", 6, "DM", "nonsec_M4_0_response_tx"},
  46         [7] = {63, "write", 2, "DM", "nonsec_GPU_response_tx"},
  47         [8] = {62, "write", 2, "DM", "nonsec_ICSSG_0_response_tx"},
  48         [9] = {61, "write", 4, "DM", "nonsec_TIFS2DM_response_tx"},
  49         [10] = {0, "read", 11, "MAIN_0_R5_0", "response"},
  50         [11] = {1, "write", 10, "MAIN_0_R5_0", "low_priority"},
  51         [12] = {2, "read", 11, "MAIN_0_R5_1", "response"},
  52         [13] = {3, "write", 10, "MAIN_0_R5_1", "low_priority"},
  53         [14] = {4, "read", 2, "MAIN_0_R5_2", "response"},
  54         [15] = {5, "write", 1, "MAIN_0_R5_2", "low_priority"},
  55         [16] = {6, "read", 2, "MAIN_0_R5_3", "response"},
  56         [17] = {7, "write", 1, "MAIN_0_R5_3", "low_priority"},
  57         [18] = {8, "read", 11, "A53_0", "response"},
  58         [19] = {9, "write", 10, "A53_0", "low_priority"},
  59         [20] = {10, "read", 6, "A53_1", "response"},
  60         [21] = {11, "write", 5, "A53_1", "low_priority"},
  61         [22] = {12, "read", 6, "A53_2", "response"},
  62         [23] = {13, "write", 5, "A53_2", "low_priority"},
  63         [24] = {14, "read", 6, "A53_3", "response"},
  64         [25] = {15, "write", 5, "A53_3", "low_priority"},
  65         [26] = {16, "read", 6, "M4_0", "response"},
  66         [27] = {17, "write", 5, "M4_0", "low_priority"},
  67         [28] = {18, "read", 2, "GPU", "response"},
  68         [29] = {19, "write", 1, "GPU", "low_priority"},
  69         [30] = {20, "read", 2, "ICSSG_0", "response"},
  70         [31] = {21, "write", 1, "ICSSG_0", "low_priority"},
  71         [32] = {22, "read", 4, "DM2TIFS", "response"},
  72         [33] = {23, "write", 2, "DM2TIFS", "low_priority"},
  73         [34] = {24, "read", 4, "TIFS2DM", "response"},
  74         [35] = {25, "write", 2, "TIFS2DM", "low_priority"},
  75 };