soc/am64x/am64x_clocks_info.c

   1 /*
   2  * AM64X Clocks Info
   3  *
   4  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  *
  13  *    Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the
  16  *    distribution.
  17  *
  18  *    Neither the name of Texas Instruments Incorporated nor the names of
  19  *    its contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <tisci.h>
  36 #include <socinfo.h>
  37
  38 struct ti_sci_clocks_info am64x_clocks_info[] = {
  39         [0] = {137, 0, "DEV_A53SS0_COREPAC_ARM_CLK_CLK", "Input clock"},
  40         [1] = {137, 1, "DEV_A53SS0_PLL_CTRL_CLK", "Input clock"},
  41         [2] = {137, 2, "DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Output clock"},
  42         [3] = {135, 0, "DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK", "Input clock"},
  43         [4] = {136, 0, "DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK", "Input clock"},
  44         [5] = {0, 0, "DEV_ADC0_ADC_CLK", "Input muxed clock"},
  45         [6] = {0, 1, "DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_ADC0_ADC_CLK"},
  46         [7] = {0, 2, "DEV_ADC0_ADC_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_ADC0_ADC_CLK"},
  47         [8] = {0, 3, "DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK", "Parent input clock option to DEV_ADC0_ADC_CLK"},
  48         [9] = {0, 4, "DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ADC0_ADC_CLK"},
  49         [10] = {0, 5, "DEV_ADC0_SYS_CLK", "Input clock"},
  50         [11] = {0, 6, "DEV_ADC0_VBUS_CLK", "Input clock"},
  51         [12] = {157, 0, "DEV_BOARD0_FSI_TX0_CLK_IN", "Input clock"},
  52         [13] = {157, 1, "DEV_BOARD0_FSI_TX1_CLK_IN", "Input clock"},
  53         [14] = {157, 2, "DEV_BOARD0_GPMC0_CLKLB_IN", "Input clock"},
  54         [15] = {157, 3, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
  55         [16] = {157, 4, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input muxed clock"},
  56         [17] = {157, 5, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"},
  57         [18] = {157, 6, "DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN"},
  58         [19] = {157, 7, "DEV_BOARD0_I2C0_SCL_IN", "Input clock"},
  59         [20] = {157, 8, "DEV_BOARD0_I2C1_SCL_IN", "Input clock"},
  60         [21] = {157, 9, "DEV_BOARD0_I2C2_SCL_IN", "Input clock"},
  61         [22] = {157, 10, "DEV_BOARD0_I2C3_SCL_IN", "Input clock"},
  62         [23] = {157, 11, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
  63         [24] = {157, 12, "DEV_BOARD0_MCU_I2C1_SCL_IN", "Input clock"},
  64         [25] = {157, 13, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
  65         [26] = {157, 14, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
  66         [27] = {157, 15, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
  67         [28] = {157, 16, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
  68         [29] = {157, 17, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
  69         [30] = {157, 18, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
  70         [31] = {157, 19, "DEV_BOARD0_MCU_TIMER_IO0_IN", "Input clock"},
  71         [32] = {157, 20, "DEV_BOARD0_MCU_TIMER_IO1_IN", "Input clock"},
  72         [33] = {157, 21, "DEV_BOARD0_MCU_TIMER_IO2_IN", "Input clock"},
  73         [34] = {157, 22, "DEV_BOARD0_MCU_TIMER_IO3_IN", "Input clock"},
  74         [35] = {157, 23, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
  75         [36] = {157, 24, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
  76         [37] = {157, 25, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  77         [38] = {157, 26, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  78         [39] = {157, 27, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  79         [40] = {157, 28, "DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  80         [41] = {157, 29, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  81         [42] = {157, 30, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  82         [43] = {157, 31, "DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  83         [44] = {157, 32, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  84         [45] = {157, 33, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  85         [46] = {157, 34, "DEV_BOARD0_OBSCLK0_IN_PARENT_SAM64_A53_256KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  86         [47] = {157, 35, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  87         [48] = {157, 36, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  88         [49] = {157, 37, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  89         [50] = {157, 38, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  90         [51] = {157, 39, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  91         [52] = {157, 40, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
  92         [53] = {157, 41, "DEV_BOARD0_OSPI0_LBCLKO_IN", "Input clock"},
  93         [54] = {157, 42, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"},
  94         [55] = {157, 43, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"},
  95         [56] = {157, 44, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"},
  96         [57] = {157, 45, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"},
  97         [58] = {157, 46, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"},
  98         [59] = {157, 47, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"},
  99         [60] = {157, 48, "DEV_BOARD0_RGMII1_TXC_IN", "Input clock"},
 100         [61] = {157, 49, "DEV_BOARD0_RGMII2_TXC_IN", "Input clock"},
 101         [62] = {157, 50, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
 102         [63] = {157, 51, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
 103         [64] = {157, 52, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
 104         [65] = {157, 53, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
 105         [66] = {157, 54, "DEV_BOARD0_SPI4_CLK_IN", "Input clock"},
 106         [67] = {157, 55, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
 107         [68] = {157, 56, "DEV_BOARD0_TIMER_IO0_IN", "Input clock"},
 108         [69] = {157, 57, "DEV_BOARD0_TIMER_IO10_IN", "Input clock"},
 109         [70] = {157, 58, "DEV_BOARD0_TIMER_IO11_IN", "Input clock"},
 110         [71] = {157, 59, "DEV_BOARD0_TIMER_IO1_IN", "Input clock"},
 111         [72] = {157, 60, "DEV_BOARD0_TIMER_IO2_IN", "Input clock"},
 112         [73] = {157, 61, "DEV_BOARD0_TIMER_IO3_IN", "Input clock"},
 113         [74] = {157, 62, "DEV_BOARD0_TIMER_IO4_IN", "Input clock"},
 114         [75] = {157, 63, "DEV_BOARD0_TIMER_IO5_IN", "Input clock"},
 115         [76] = {157, 64, "DEV_BOARD0_TIMER_IO6_IN", "Input clock"},
 116         [77] = {157, 65, "DEV_BOARD0_TIMER_IO7_IN", "Input clock"},
 117         [78] = {157, 66, "DEV_BOARD0_TIMER_IO8_IN", "Input clock"},
 118         [79] = {157, 67, "DEV_BOARD0_TIMER_IO9_IN", "Input clock"},
 119         [80] = {157, 68, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
 120         [81] = {157, 69, "DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Output clock"},
 121         [82] = {157, 70, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
 122         [83] = {157, 71, "DEV_BOARD0_FSI_RX0_CLK_OUT", "Output clock"},
 123         [84] = {157, 72, "DEV_BOARD0_FSI_RX1_CLK_OUT", "Output clock"},
 124         [85] = {157, 73, "DEV_BOARD0_FSI_RX2_CLK_OUT", "Output clock"},
 125         [86] = {157, 74, "DEV_BOARD0_FSI_RX3_CLK_OUT", "Output clock"},
 126         [87] = {157, 75, "DEV_BOARD0_FSI_RX4_CLK_OUT", "Output clock"},
 127         [88] = {157, 76, "DEV_BOARD0_FSI_RX5_CLK_OUT", "Output clock"},
 128         [89] = {157, 77, "DEV_BOARD0_GPMC0_CLKLB_OUT", "Output clock"},
 129         [90] = {157, 78, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
 130         [91] = {157, 79, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
 131         [92] = {157, 80, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
 132         [93] = {157, 81, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
 133         [94] = {157, 82, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
 134         [95] = {157, 83, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
 135         [96] = {157, 84, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
 136         [97] = {157, 85, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
 137         [98] = {157, 86, "DEV_BOARD0_MCU_SPI0_CLK_OUT", "Output clock"},
 138         [99] = {157, 87, "DEV_BOARD0_MCU_SPI1_CLK_OUT", "Output clock"},
 139         [100] = {157, 88, "DEV_BOARD0_MMC1_CLKLB_OUT", "Output clock"},
 140         [101] = {157, 89, "DEV_BOARD0_OSPI0_DQS_OUT", "Output clock"},
 141         [102] = {157, 90, "DEV_BOARD0_OSPI0_LBCLKO_OUT", "Output clock"},
 142         [103] = {157, 91, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"},
 143         [104] = {157, 92, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"},
 144         [105] = {157, 93, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"},
 145         [106] = {157, 94, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"},
 146         [107] = {157, 95, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"},
 147         [108] = {157, 96, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"},
 148         [109] = {157, 97, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"},
 149         [110] = {157, 98, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"},
 150         [111] = {157, 99, "DEV_BOARD0_RGMII1_RXC_OUT", "Output clock"},
 151         [112] = {157, 100, "DEV_BOARD0_RGMII1_TXC_OUT", "Output clock"},
 152         [113] = {157, 101, "DEV_BOARD0_RGMII2_RXC_OUT", "Output clock"},
 153         [114] = {157, 102, "DEV_BOARD0_RGMII2_TXC_OUT", "Output clock"},
 154         [115] = {157, 103, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
 155         [116] = {157, 104, "DEV_BOARD0_SPI0_CLK_OUT", "Output clock"},
 156         [117] = {157, 105, "DEV_BOARD0_SPI1_CLK_OUT", "Output clock"},
 157         [118] = {157, 106, "DEV_BOARD0_SPI2_CLK_OUT", "Output clock"},
 158         [119] = {157, 107, "DEV_BOARD0_SPI3_CLK_OUT", "Output clock"},
 159         [120] = {157, 108, "DEV_BOARD0_SPI4_CLK_OUT", "Output clock"},
 160         [121] = {157, 109, "DEV_BOARD0_TCK_OUT", "Output clock"},
 161         [122] = {1, 0, "DEV_CMP_EVENT_INTROUTER0_INTR_CLK", "Input clock"},
 162         [123] = {13, 0, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
 163         [124] = {13, 1, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
 164         [125] = {13, 2, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 165         [126] = {13, 3, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 166         [127] = {13, 4, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 167         [128] = {13, 5, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 168         [129] = {13, 6, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 169         [130] = {13, 7, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 170         [131] = {13, 8, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 171         [132] = {13, 9, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
 172         [133] = {13, 10, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
 173         [134] = {13, 11, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
 174         [135] = {13, 12, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
 175         [136] = {13, 13, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
 176         [137] = {13, 14, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
 177         [138] = {13, 15, "DEV_CPSW0_RGMII1_RXC_I", "Input clock"},
 178         [139] = {13, 16, "DEV_CPSW0_RGMII1_TXC_I", "Input clock"},
 179         [140] = {13, 17, "DEV_CPSW0_RGMII2_RXC_I", "Input clock"},
 180         [141] = {13, 18, "DEV_CPSW0_RGMII2_TXC_I", "Input clock"},
 181         [142] = {13, 19, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
 182         [143] = {13, 20, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
 183         [144] = {13, 21, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
 184         [145] = {13, 22, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
 185         [146] = {13, 23, "DEV_CPSW0_CPTS_GENF0", "Output clock"},
 186         [147] = {13, 24, "DEV_CPSW0_CPTS_GENF1", "Output clock"},
 187         [148] = {13, 25, "DEV_CPSW0_RGMII1_TXC_O", "Output clock"},
 188         [149] = {13, 26, "DEV_CPSW0_RGMII2_TXC_O", "Output clock"},
 189         [150] = {14, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
 190         [151] = {84, 0, "DEV_CPTS0_CPTS_RFT_CLK", "Input muxed clock"},
 191         [152] = {84, 1, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 192         [153] = {84, 2, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 193         [154] = {84, 3, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 194         [155] = {84, 4, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 195         [156] = {84, 5, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 196         [157] = {84, 6, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 197         [158] = {84, 7, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 198         [159] = {84, 8, "DEV_CPTS0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK"},
 199         [160] = {84, 9, "DEV_CPTS0_VBUSP_CLK", "Input clock"},
 200         [161] = {84, 10, "DEV_CPTS0_CPTS_GENF1", "Output clock"},
 201         [162] = {84, 11, "DEV_CPTS0_CPTS_GENF2", "Output clock"},
 202         [163] = {84, 12, "DEV_CPTS0_CPTS_GENF3", "Output clock"},
 203         [164] = {84, 13, "DEV_CPTS0_CPTS_GENF4", "Output clock"},
 204         [165] = {2, 0, "DEV_DBGSUSPENDROUTER0_INTR_CLK", "Input clock"},
 205         [166] = {16, 0, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
 206         [167] = {16, 1, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
 207         [168] = {16, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
 208         [169] = {16, 3, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
 209         [170] = {16, 4, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
 210         [171] = {16, 5, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
 211         [172] = {16, 6, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
 212         [173] = {16, 7, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
 213         [174] = {16, 8, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
 214         [175] = {16, 9, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
 215         [176] = {16, 10, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
 216         [177] = {16, 11, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
 217         [178] = {16, 12, "DEV_DCC0_VBUS_CLK", "Input clock"},
 218         [179] = {17, 0, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
 219         [180] = {17, 1, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
 220         [181] = {17, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
 221         [182] = {17, 3, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
 222         [183] = {17, 4, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
 223         [184] = {17, 5, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
 224         [185] = {17, 6, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
 225         [186] = {17, 7, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
 226         [187] = {17, 8, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
 227         [188] = {17, 9, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
 228         [189] = {17, 10, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
 229         [190] = {17, 11, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
 230         [191] = {17, 12, "DEV_DCC1_VBUS_CLK", "Input clock"},
 231         [192] = {18, 0, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
 232         [193] = {18, 1, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
 233         [194] = {18, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
 234         [195] = {18, 3, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
 235         [196] = {18, 4, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
 236         [197] = {18, 5, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
 237         [198] = {18, 6, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
 238         [199] = {18, 7, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
 239         [200] = {18, 8, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
 240         [201] = {18, 9, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
 241         [202] = {18, 10, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
 242         [203] = {18, 11, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
 243         [204] = {18, 12, "DEV_DCC2_VBUS_CLK", "Input clock"},
 244         [205] = {19, 0, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
 245         [206] = {19, 1, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
 246         [207] = {19, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
 247         [208] = {19, 3, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
 248         [209] = {19, 4, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
 249         [210] = {19, 5, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
 250         [211] = {19, 6, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
 251         [212] = {19, 7, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
 252         [213] = {19, 8, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
 253         [214] = {19, 9, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
 254         [215] = {19, 10, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
 255         [216] = {19, 11, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
 256         [217] = {19, 12, "DEV_DCC3_VBUS_CLK", "Input clock"},
 257         [218] = {20, 0, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input muxed clock"},
 258         [219] = {20, 1, "DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK"},
 259         [220] = {20, 2, "DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK"},
 260         [221] = {20, 3, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
 261         [222] = {20, 4, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
 262         [223] = {20, 5, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
 263         [224] = {20, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
 264         [225] = {20, 7, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
 265         [226] = {20, 8, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
 266         [227] = {20, 9, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
 267         [228] = {20, 10, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
 268         [229] = {20, 11, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
 269         [230] = {20, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
 270         [231] = {20, 13, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
 271         [232] = {20, 14, "DEV_DCC4_VBUS_CLK", "Input clock"},
 272         [233] = {21, 0, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
 273         [234] = {21, 1, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
 274         [235] = {21, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
 275         [236] = {21, 3, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
 276         [237] = {21, 4, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
 277         [238] = {21, 5, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"},
 278         [239] = {21, 6, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
 279         [240] = {21, 7, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
 280         [241] = {21, 8, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
 281         [242] = {21, 9, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
 282         [243] = {21, 10, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
 283         [244] = {21, 11, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
 284         [245] = {21, 12, "DEV_DCC5_VBUS_CLK", "Input clock"},
 285         [246] = {85, 0, "DEV_DDPA0_DDPA_CLK", "Input clock"},
 286         [247] = {138, 0, "DEV_DDR16SS0_DDRSS_DDR_PLL_CLK", "Input clock"},
 287         [248] = {138, 1, "DEV_DDR16SS0_PLL_CTRL_CLK", "Input clock"},
 288         [249] = {24, 0, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
 289         [250] = {24, 1, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
 290         [251] = {24, 2, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
 291         [252] = {24, 3, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
 292         [253] = {26, 0, "DEV_DMASS0_BCDMA_0_CLK", "Input clock"},
 293         [254] = {27, 0, "DEV_DMASS0_CBASS_0_CLK", "Input clock"},
 294         [255] = {28, 0, "DEV_DMASS0_INTAGGR_0_CLK", "Input clock"},
 295         [256] = {29, 0, "DEV_DMASS0_IPCSS_0_CLK", "Input clock"},
 296         [257] = {30, 0, "DEV_DMASS0_PKTDMA_0_CLK", "Input clock"},
 297         [258] = {31, 0, "DEV_DMASS0_PSILCFG_0_CLK", "Input clock"},
 298         [259] = {32, 0, "DEV_DMASS0_PSILSS_0_PDMA_MAIN0_CLK", "Input clock"},
 299         [260] = {32, 1, "DEV_DMASS0_PSILSS_0_PDMA_MAIN1_CLK", "Input clock"},
 300         [261] = {32, 2, "DEV_DMASS0_PSILSS_0_VD2CLK", "Input clock"},
 301         [262] = {33, 0, "DEV_DMASS0_RINGACC_0_CLK", "Input clock"},
 302         [263] = {51, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
 303         [264] = {52, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
 304         [265] = {53, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
 305         [266] = {54, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
 306         [267] = {86, 0, "DEV_EPWM0_VBUSP_CLK", "Input clock"},
 307         [268] = {87, 0, "DEV_EPWM1_VBUSP_CLK", "Input clock"},
 308         [269] = {88, 0, "DEV_EPWM2_VBUSP_CLK", "Input clock"},
 309         [270] = {89, 0, "DEV_EPWM3_VBUSP_CLK", "Input clock"},
 310         [271] = {90, 0, "DEV_EPWM4_VBUSP_CLK", "Input clock"},
 311         [272] = {91, 0, "DEV_EPWM5_VBUSP_CLK", "Input clock"},
 312         [273] = {92, 0, "DEV_EPWM6_VBUSP_CLK", "Input clock"},
 313         [274] = {93, 0, "DEV_EPWM7_VBUSP_CLK", "Input clock"},
 314         [275] = {94, 0, "DEV_EPWM8_VBUSP_CLK", "Input clock"},
 315         [276] = {59, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
 316         [277] = {60, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
 317         [278] = {62, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
 318         [279] = {63, 0, "DEV_ESM0_CLK", "Input clock"},
 319         [280] = {65, 0, "DEV_FSIRX0_FSI_RX_CK", "Input clock"},
 320         [281] = {65, 1, "DEV_FSIRX0_FSI_RX_LPBK_CK", "Input clock"},
 321         [282] = {65, 2, "DEV_FSIRX0_FSI_RX_VBUS_CLK", "Input clock"},
 322         [283] = {66, 0, "DEV_FSIRX1_FSI_RX_CK", "Input clock"},
 323         [284] = {66, 1, "DEV_FSIRX1_FSI_RX_LPBK_CK", "Input clock"},
 324         [285] = {66, 2, "DEV_FSIRX1_FSI_RX_VBUS_CLK", "Input clock"},
 325         [286] = {67, 0, "DEV_FSIRX2_FSI_RX_CK", "Input clock"},
 326         [287] = {67, 1, "DEV_FSIRX2_FSI_RX_LPBK_CK", "Input clock"},
 327         [288] = {67, 2, "DEV_FSIRX2_FSI_RX_VBUS_CLK", "Input clock"},
 328         [289] = {68, 0, "DEV_FSIRX3_FSI_RX_CK", "Input clock"},
 329         [290] = {68, 1, "DEV_FSIRX3_FSI_RX_LPBK_CK", "Input clock"},
 330         [291] = {68, 2, "DEV_FSIRX3_FSI_RX_VBUS_CLK", "Input clock"},
 331         [292] = {69, 0, "DEV_FSIRX4_FSI_RX_CK", "Input clock"},
 332         [293] = {69, 1, "DEV_FSIRX4_FSI_RX_LPBK_CK", "Input clock"},
 333         [294] = {69, 2, "DEV_FSIRX4_FSI_RX_VBUS_CLK", "Input clock"},
 334         [295] = {70, 0, "DEV_FSIRX5_FSI_RX_CK", "Input clock"},
 335         [296] = {70, 1, "DEV_FSIRX5_FSI_RX_LPBK_CK", "Input clock"},
 336         [297] = {70, 2, "DEV_FSIRX5_FSI_RX_VBUS_CLK", "Input clock"},
 337         [298] = {71, 0, "DEV_FSITX0_FSI_TX_PLL_CLK", "Input clock"},
 338         [299] = {71, 1, "DEV_FSITX0_FSI_TX_VBUS_CLK", "Input clock"},
 339         [300] = {71, 2, "DEV_FSITX0_FSI_TX_CK", "Output clock"},
 340         [301] = {72, 0, "DEV_FSITX1_FSI_TX_PLL_CLK", "Input clock"},
 341         [302] = {72, 1, "DEV_FSITX1_FSI_TX_VBUS_CLK", "Input clock"},
 342         [303] = {72, 2, "DEV_FSITX1_FSI_TX_CK", "Output clock"},
 343         [304] = {74, 0, "DEV_FSS0_FSAS_0_GCLK", "Input clock"},
 344         [305] = {75, 0, "DEV_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
 345         [306] = {75, 1, "DEV_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
 346         [307] = {75, 2, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
 347         [308] = {75, 3, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"},
 348         [309] = {75, 4, "DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK"},
 349         [310] = {75, 5, "DEV_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
 350         [311] = {75, 6, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
 351         [312] = {75, 7, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"},
 352         [313] = {75, 8, "DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK"},
 353         [314] = {75, 9, "DEV_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
 354         [315] = {76, 0, "DEV_GICSS0_VCLK_CLK", "Input clock"},
 355         [316] = {77, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
 356         [317] = {78, 0, "DEV_GPIO1_MMR_CLK", "Input clock"},
 357         [318] = {80, 0, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
 358         [319] = {80, 1, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
 359         [320] = {80, 2, "DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
 360         [321] = {80, 3, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
 361         [322] = {80, 4, "DEV_GPMC0_VBUSM_CLK", "Input clock"},
 362         [323] = {80, 5, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
 363         [324] = {61, 0, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
 364         [325] = {61, 1, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 365         [326] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 366         [327] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 367         [328] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 368         [329] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 369         [330] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 370         [331] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 371         [332] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
 372         [333] = {61, 9, "DEV_GTC0_VBUSP_CLK", "Input clock"},
 373         [334] = {102, 0, "DEV_I2C0_CLK", "Input clock"},
 374         [335] = {102, 1, "DEV_I2C0_PISCL", "Input clock"},
 375         [336] = {102, 2, "DEV_I2C0_PISYS_CLK", "Input clock"},
 376         [337] = {102, 3, "DEV_I2C0_PORSCL", "Output clock"},
 377         [338] = {103, 0, "DEV_I2C1_CLK", "Input clock"},
 378         [339] = {103, 1, "DEV_I2C1_PISCL", "Input clock"},
 379         [340] = {103, 2, "DEV_I2C1_PISYS_CLK", "Input clock"},
 380         [341] = {103, 3, "DEV_I2C1_PORSCL", "Output clock"},
 381         [342] = {104, 0, "DEV_I2C2_CLK", "Input clock"},
 382         [343] = {104, 1, "DEV_I2C2_PISCL", "Input clock"},
 383         [344] = {104, 2, "DEV_I2C2_PISYS_CLK", "Input clock"},
 384         [345] = {104, 3, "DEV_I2C2_PORSCL", "Output clock"},
 385         [346] = {105, 0, "DEV_I2C3_CLK", "Input clock"},
 386         [347] = {105, 1, "DEV_I2C3_PISCL", "Input clock"},
 387         [348] = {105, 2, "DEV_I2C3_PISYS_CLK", "Input clock"},
 388         [349] = {105, 3, "DEV_I2C3_PORSCL", "Output clock"},
 389         [350] = {83, 0, "DEV_LED0_LED_CLK", "Input clock"},
 390         [351] = {83, 1, "DEV_LED0_VBUSP_CLK", "Input clock"},
 391         [352] = {3, 0, "DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"},
 392         [353] = {98, 0, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
 393         [354] = {98, 1, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
 394         [355] = {98, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
 395         [356] = {98, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
 396         [357] = {98, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
 397         [358] = {98, 5, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
 398         [359] = {99, 0, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
 399         [360] = {99, 1, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
 400         [361] = {99, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
 401         [362] = {99, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
 402         [363] = {99, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
 403         [364] = {99, 5, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
 404         [365] = {141, 0, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
 405         [366] = {141, 1, "DEV_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"},
 406         [367] = {141, 2, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"},
 407         [368] = {141, 3, "DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK"},
 408         [369] = {141, 4, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
 409         [370] = {141, 5, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
 410         [371] = {142, 0, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
 411         [372] = {142, 1, "DEV_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
 412         [373] = {142, 2, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"},
 413         [374] = {142, 3, "DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK"},
 414         [375] = {142, 4, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
 415         [376] = {142, 5, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
 416         [377] = {143, 0, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
 417         [378] = {143, 1, "DEV_MCSPI2_IO_CLKSPII_CLK", "Input muxed clock"},
 418         [379] = {143, 2, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"},
 419         [380] = {143, 3, "DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK"},
 420         [381] = {143, 4, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
 421         [382] = {143, 5, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
 422         [383] = {144, 0, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
 423         [384] = {144, 1, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
 424         [385] = {144, 2, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
 425         [386] = {144, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
 426         [387] = {144, 4, "DEV_MCSPI3_VBUSP_CLK", "Input clock"},
 427         [388] = {144, 5, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
 428         [389] = {145, 0, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
 429         [390] = {145, 1, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input muxed clock"},
 430         [391] = {145, 2, "DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT", "Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK"},
 431         [392] = {145, 3, "DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK"},
 432         [393] = {145, 4, "DEV_MCSPI4_VBUSP_CLK", "Input clock"},
 433         [394] = {145, 5, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
 434         [395] = {23, 0, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
 435         [396] = {23, 1, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
 436         [397] = {23, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
 437         [398] = {23, 3, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
 438         [399] = {23, 4, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
 439         [400] = {23, 5, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
 440         [401] = {23, 6, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
 441         [402] = {23, 7, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
 442         [403] = {23, 8, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
 443         [404] = {23, 9, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
 444         [405] = {23, 10, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
 445         [406] = {23, 11, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
 446         [407] = {23, 12, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
 447         [408] = {64, 0, "DEV_MCU_ESM0_CLK", "Input clock"},
 448         [409] = {79, 0, "DEV_MCU_GPIO0_MMR_CLK", "Input clock"},
 449         [410] = {106, 0, "DEV_MCU_I2C0_CLK", "Input clock"},
 450         [411] = {106, 1, "DEV_MCU_I2C0_PISCL", "Input clock"},
 451         [412] = {106, 2, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
 452         [413] = {106, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"},
 453         [414] = {107, 0, "DEV_MCU_I2C1_CLK", "Input clock"},
 454         [415] = {107, 1, "DEV_MCU_I2C1_PISCL", "Input clock"},
 455         [416] = {107, 2, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"},
 456         [417] = {107, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"},
 457         [418] = {9, 0, "DEV_MCU_M4FSS0_CORE0_DAP_CLK", "Input clock"},
 458         [419] = {9, 1, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK", "Input muxed clock"},
 459         [420] = {9, 2, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"},
 460         [421] = {9, 3, "DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK"},
 461         [422] = {100, 0, "DEV_MCU_MCRC64_0_CLK", "Input clock"},
 462         [423] = {147, 0, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
 463         [424] = {147, 1, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK", "Input muxed clock"},
 464         [425] = {147, 2, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"},
 465         [426] = {147, 3, "DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK"},
 466         [427] = {147, 4, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
 467         [428] = {147, 5, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
 468         [429] = {148, 0, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
 469         [430] = {148, 1, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
 470         [431] = {148, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
 471         [432] = {148, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
 472         [433] = {148, 4, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
 473         [434] = {148, 5, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
 474         [435] = {5, 0, "DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK", "Input clock"},
 475         [436] = {140, 0, "DEV_MCU_PSC0_CLK", "Input clock"},
 476         [437] = {140, 1, "DEV_MCU_PSC0_SLOW_CLK", "Input clock"},
 477         [438] = {132, 0, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
 478         [439] = {132, 1, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
 479         [440] = {132, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
 480         [441] = {132, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
 481         [442] = {132, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
 482         [443] = {132, 5, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
 483         [444] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
 484         [445] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
 485         [446] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 486         [447] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 487         [448] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 488         [449] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 489         [450] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 490         [451] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 491         [452] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 492         [453] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
 493         [454] = {35, 10, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"},
 494         [455] = {48, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
 495         [456] = {48, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
 496         [457] = {48, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 497         [458] = {48, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 498         [459] = {48, 4, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 499         [460] = {48, 5, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 500         [461] = {48, 6, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 501         [462] = {48, 7, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 502         [463] = {48, 8, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 503         [464] = {48, 9, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
 504         [465] = {48, 10, "DEV_MCU_TIMER1_TIMER_PWM", "Output clock"},
 505         [466] = {49, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
 506         [467] = {49, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
 507         [468] = {49, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 508         [469] = {49, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 509         [470] = {49, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 510         [471] = {49, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 511         [472] = {49, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 512         [473] = {49, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 513         [474] = {49, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 514         [475] = {49, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
 515         [476] = {49, 10, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"},
 516         [477] = {50, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
 517         [478] = {50, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
 518         [479] = {50, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 519         [480] = {50, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 520         [481] = {50, 4, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 521         [482] = {50, 5, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 522         [483] = {50, 6, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 523         [484] = {50, 7, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 524         [485] = {50, 8, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 525         [486] = {50, 9, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
 526         [487] = {50, 10, "DEV_MCU_TIMER3_TIMER_PWM", "Output clock"},
 527         [488] = {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input clock"},
 528         [489] = {149, 1, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
 529         [490] = {160, 0, "DEV_MCU_UART1_FCLK_CLK", "Input clock"},
 530         [491] = {160, 1, "DEV_MCU_UART1_VBUSP_CLK", "Input clock"},
 531         [492] = {57, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"},
 532         [493] = {57, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
 533         [494] = {57, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
 534         [495] = {57, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
 535         [496] = {58, 0, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input muxed clock"},
 536         [497] = {58, 1, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"},
 537         [498] = {58, 2, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I"},
 538         [499] = {58, 3, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
 539         [500] = {58, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
 540         [501] = {58, 5, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
 541         [502] = {58, 6, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
 542         [503] = {58, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"},
 543         [504] = {108, 0, "DEV_MSRAM_256K0_CCLK_CLK", "Input clock"},
 544         [505] = {108, 1, "DEV_MSRAM_256K0_VCLK_CLK", "Input clock"},
 545         [506] = {109, 0, "DEV_MSRAM_256K1_CCLK_CLK", "Input clock"},
 546         [507] = {109, 1, "DEV_MSRAM_256K1_VCLK_CLK", "Input clock"},
 547         [508] = {110, 0, "DEV_MSRAM_256K2_CCLK_CLK", "Input clock"},
 548         [509] = {110, 1, "DEV_MSRAM_256K2_VCLK_CLK", "Input clock"},
 549         [510] = {111, 0, "DEV_MSRAM_256K3_CCLK_CLK", "Input clock"},
 550         [511] = {111, 1, "DEV_MSRAM_256K3_VCLK_CLK", "Input clock"},
 551         [512] = {112, 0, "DEV_MSRAM_256K4_CCLK_CLK", "Input clock"},
 552         [513] = {112, 1, "DEV_MSRAM_256K4_VCLK_CLK", "Input clock"},
 553         [514] = {113, 0, "DEV_MSRAM_256K5_CCLK_CLK", "Input clock"},
 554         [515] = {113, 1, "DEV_MSRAM_256K5_VCLK_CLK", "Input clock"},
 555         [516] = {163, 0, "DEV_PBIST0_CLK8_CLK", "Input clock"},
 556         [517] = {164, 0, "DEV_PBIST1_CLK8_CLK", "Input clock"},
 557         [518] = {165, 0, "DEV_PBIST2_CLK8_CLK", "Input clock"},
 558         [519] = {166, 0, "DEV_PBIST3_CLK8_CLK", "Input clock"},
 559         [520] = {114, 0, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"},
 560         [521] = {114, 1, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
 561         [522] = {114, 2, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 562         [523] = {114, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 563         [524] = {114, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 564         [525] = {114, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 565         [526] = {114, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 566         [527] = {114, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 567         [528] = {114, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 568         [529] = {114, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
 569         [530] = {114, 10, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"},
 570         [531] = {114, 11, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"},
 571         [532] = {114, 12, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"},
 572         [533] = {114, 13, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"},
 573         [534] = {114, 14, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"},
 574         [535] = {114, 15, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"},
 575         [536] = {114, 16, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"},
 576         [537] = {115, 0, "DEV_POSTDIV1_16FFT1_FREF_CLK", "Input clock"},
 577         [538] = {115, 1, "DEV_POSTDIV1_16FFT1_POSTDIV_CLKIN_CLK", "Input clock"},
 578         [539] = {115, 2, "DEV_POSTDIV1_16FFT1_HSDIVOUT5_CLK", "Output clock"},
 579         [540] = {115, 3, "DEV_POSTDIV1_16FFT1_HSDIVOUT6_CLK", "Output clock"},
 580         [541] = {116, 0, "DEV_POSTDIV4_16FF0_FREF_CLK", "Input clock"},
 581         [542] = {116, 1, "DEV_POSTDIV4_16FF0_POSTDIV_CLKIN_CLK", "Input clock"},
 582         [543] = {116, 2, "DEV_POSTDIV4_16FF0_HSDIVOUT5_CLK", "Output clock"},
 583         [544] = {116, 3, "DEV_POSTDIV4_16FF0_HSDIVOUT6_CLK", "Output clock"},
 584         [545] = {116, 4, "DEV_POSTDIV4_16FF0_HSDIVOUT7_CLK", "Output clock"},
 585         [546] = {116, 5, "DEV_POSTDIV4_16FF0_HSDIVOUT8_CLK", "Output clock"},
 586         [547] = {116, 6, "DEV_POSTDIV4_16FF0_HSDIVOUT9_CLK", "Output clock"},
 587         [548] = {117, 0, "DEV_POSTDIV4_16FF2_FREF_CLK", "Input clock"},
 588         [549] = {117, 1, "DEV_POSTDIV4_16FF2_POSTDIV_CLKIN_CLK", "Input clock"},
 589         [550] = {117, 2, "DEV_POSTDIV4_16FF2_HSDIVOUT5_CLK", "Output clock"},
 590         [551] = {117, 3, "DEV_POSTDIV4_16FF2_HSDIVOUT6_CLK", "Output clock"},
 591         [552] = {117, 4, "DEV_POSTDIV4_16FF2_HSDIVOUT7_CLK", "Output clock"},
 592         [553] = {117, 5, "DEV_POSTDIV4_16FF2_HSDIVOUT8_CLK", "Output clock"},
 593         [554] = {117, 6, "DEV_POSTDIV4_16FF2_HSDIVOUT9_CLK", "Output clock"},
 594         [555] = {81, 0, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"},
 595         [556] = {81, 1, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
 596         [557] = {81, 2, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
 597         [558] = {81, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"},
 598         [559] = {81, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 599         [560] = {81, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 600         [561] = {81, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 601         [562] = {81, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 602         [563] = {81, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 603         [564] = {81, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 604         [565] = {81, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 605         [566] = {81, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
 606         [567] = {81, 12, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I", "Input clock"},
 607         [568] = {81, 13, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I", "Input clock"},
 608         [569] = {81, 14, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I", "Input clock"},
 609         [570] = {81, 15, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I", "Input clock"},
 610         [571] = {81, 16, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"},
 611         [572] = {81, 17, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"},
 612         [573] = {81, 18, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"},
 613         [574] = {81, 19, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"},
 614         [575] = {81, 20, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"},
 615         [576] = {81, 21, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O", "Output clock"},
 616         [577] = {81, 22, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O", "Output clock"},
 617         [578] = {81, 23, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O", "Output clock"},
 618         [579] = {82, 0, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"},
 619         [580] = {82, 1, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
 620         [581] = {82, 2, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
 621         [582] = {82, 3, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"},
 622         [583] = {82, 4, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 623         [584] = {82, 5, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 624         [585] = {82, 6, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 625         [586] = {82, 7, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 626         [587] = {82, 8, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 627         [588] = {82, 9, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 628         [589] = {82, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 629         [590] = {82, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
 630         [591] = {82, 12, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I", "Input clock"},
 631         [592] = {82, 13, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I", "Input clock"},
 632         [593] = {82, 14, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I", "Input clock"},
 633         [594] = {82, 15, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I", "Input clock"},
 634         [595] = {82, 16, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"},
 635         [596] = {82, 17, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"},
 636         [597] = {82, 18, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"},
 637         [598] = {82, 19, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"},
 638         [599] = {82, 20, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"},
 639         [600] = {82, 21, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O", "Output clock"},
 640         [601] = {82, 22, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O", "Output clock"},
 641         [602] = {82, 23, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O", "Output clock"},
 642         [603] = {139, 0, "DEV_PSC0_CLK", "Input clock"},
 643         [604] = {139, 1, "DEV_PSC0_SLOW_CLK", "Input clock"},
 644         [605] = {118, 0, "DEV_PSRAMECC0_CLK_CLK", "Input clock"},
 645         [606] = {121, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"},
 646         [607] = {121, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
 647         [608] = {122, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"},
 648         [609] = {122, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
 649         [610] = {123, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"},
 650         [611] = {123, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"},
 651         [612] = {124, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"},
 652         [613] = {124, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"},
 653         [614] = {125, 0, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
 654         [615] = {125, 1, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
 655         [616] = {125, 2, "DEV_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI0_RTI_CLK"},
 656         [617] = {125, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
 657         [618] = {125, 4, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI0_RTI_CLK"},
 658         [619] = {125, 5, "DEV_RTI0_VBUSP_CLK", "Input clock"},
 659         [620] = {126, 0, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
 660         [621] = {126, 1, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
 661         [622] = {126, 2, "DEV_RTI1_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI1_RTI_CLK"},
 662         [623] = {126, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
 663         [624] = {126, 4, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI1_RTI_CLK"},
 664         [625] = {126, 5, "DEV_RTI1_VBUSP_CLK", "Input clock"},
 665         [626] = {130, 0, "DEV_RTI10_RTI_CLK", "Input muxed clock"},
 666         [627] = {130, 1, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI10_RTI_CLK"},
 667         [628] = {130, 2, "DEV_RTI10_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI10_RTI_CLK"},
 668         [629] = {130, 3, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI10_RTI_CLK"},
 669         [630] = {130, 4, "DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI10_RTI_CLK"},
 670         [631] = {130, 5, "DEV_RTI10_VBUSP_CLK", "Input clock"},
 671         [632] = {131, 0, "DEV_RTI11_RTI_CLK", "Input muxed clock"},
 672         [633] = {131, 1, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI11_RTI_CLK"},
 673         [634] = {131, 2, "DEV_RTI11_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI11_RTI_CLK"},
 674         [635] = {131, 3, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI11_RTI_CLK"},
 675         [636] = {131, 4, "DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI11_RTI_CLK"},
 676         [637] = {131, 5, "DEV_RTI11_VBUSP_CLK", "Input clock"},
 677         [638] = {127, 0, "DEV_RTI8_RTI_CLK", "Input muxed clock"},
 678         [639] = {127, 1, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI8_RTI_CLK"},
 679         [640] = {127, 2, "DEV_RTI8_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI8_RTI_CLK"},
 680         [641] = {127, 3, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI8_RTI_CLK"},
 681         [642] = {127, 4, "DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI8_RTI_CLK"},
 682         [643] = {127, 5, "DEV_RTI8_VBUSP_CLK", "Input clock"},
 683         [644] = {128, 0, "DEV_RTI9_RTI_CLK", "Input muxed clock"},
 684         [645] = {128, 1, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI9_RTI_CLK"},
 685         [646] = {128, 2, "DEV_RTI9_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_RTI9_RTI_CLK"},
 686         [647] = {128, 3, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_RTI9_RTI_CLK"},
 687         [648] = {128, 4, "DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3", "Parent input clock option to DEV_RTI9_RTI_CLK"},
 688         [649] = {128, 5, "DEV_RTI9_VBUSP_CLK", "Input clock"},
 689         [650] = {133, 0, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"},
 690         [651] = {133, 1, "DEV_SA2_UL0_X1_CLK", "Input clock"},
 691         [652] = {133, 2, "DEV_SA2_UL0_X2_CLK", "Input clock"},
 692         [653] = {162, 0, "DEV_SERDES_10G0_CLK", "Input clock"},
 693         [654] = {162, 1, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"},
 694         [655] = {162, 2, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
 695         [656] = {162, 3, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
 696         [657] = {162, 4, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
 697         [658] = {162, 5, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
 698         [659] = {162, 6, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"},
 699         [660] = {162, 7, "DEV_SERDES_10G0_IP2_LN0_TXCLK", "Input clock"},
 700         [661] = {162, 8, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"},
 701         [662] = {162, 9, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"},
 702         [663] = {162, 10, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"},
 703         [664] = {162, 11, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"},
 704         [665] = {162, 12, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"},
 705         [666] = {162, 13, "DEV_SERDES_10G0_IP2_LN0_REFCLK", "Output clock"},
 706         [667] = {162, 14, "DEV_SERDES_10G0_IP2_LN0_RXCLK", "Output clock"},
 707         [668] = {162, 15, "DEV_SERDES_10G0_IP2_LN0_RXFCLK", "Output clock"},
 708         [669] = {162, 16, "DEV_SERDES_10G0_IP2_LN0_TXFCLK", "Output clock"},
 709         [670] = {162, 17, "DEV_SERDES_10G0_IP2_LN0_TXMCLK", "Output clock"},
 710         [671] = {162, 18, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"},
 711         [672] = {150, 0, "DEV_SPINLOCK0_VCLK_CLK", "Input clock"},
 712         [673] = {15, 0, "DEV_STM0_ATB_CLK", "Input clock"},
 713         [674] = {15, 1, "DEV_STM0_CORE_CLK", "Input clock"},
 714         [675] = {15, 2, "DEV_STM0_VBUSP_CLK", "Input clock"},
 715         [676] = {36, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"},
 716         [677] = {36, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
 717         [678] = {36, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 718         [679] = {36, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 719         [680] = {36, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 720         [681] = {36, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 721         [682] = {36, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 722         [683] = {36, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 723         [684] = {36, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 724         [685] = {36, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 725         [686] = {36, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 726         [687] = {36, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 727         [688] = {36, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 728         [689] = {36, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 729         [690] = {36, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 730         [691] = {36, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 731         [692] = {36, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 732         [693] = {36, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
 733         [694] = {36, 18, "DEV_TIMER0_TIMER_PWM", "Output clock"},
 734         [695] = {37, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"},
 735         [696] = {37, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
 736         [697] = {37, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 737         [698] = {37, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 738         [699] = {37, 4, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 739         [700] = {37, 5, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 740         [701] = {37, 6, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 741         [702] = {37, 7, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 742         [703] = {37, 8, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 743         [704] = {37, 9, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 744         [705] = {37, 10, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 745         [706] = {37, 11, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 746         [707] = {37, 12, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 747         [708] = {37, 13, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 748         [709] = {37, 14, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 749         [710] = {37, 15, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 750         [711] = {37, 16, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 751         [712] = {37, 17, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
 752         [713] = {37, 18, "DEV_TIMER1_TIMER_PWM", "Output clock"},
 753         [714] = {46, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"},
 754         [715] = {46, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"},
 755         [716] = {46, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 756         [717] = {46, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 757         [718] = {46, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 758         [719] = {46, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 759         [720] = {46, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 760         [721] = {46, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 761         [722] = {46, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 762         [723] = {46, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 763         [724] = {46, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 764         [725] = {46, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 765         [726] = {46, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 766         [727] = {46, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 767         [728] = {46, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 768         [729] = {46, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 769         [730] = {46, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 770         [731] = {46, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
 771         [732] = {46, 18, "DEV_TIMER10_TIMER_PWM", "Output clock"},
 772         [733] = {47, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"},
 773         [734] = {47, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"},
 774         [735] = {47, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 775         [736] = {47, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 776         [737] = {47, 4, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 777         [738] = {47, 5, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 778         [739] = {47, 6, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 779         [740] = {47, 7, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 780         [741] = {47, 8, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 781         [742] = {47, 9, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 782         [743] = {47, 10, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 783         [744] = {47, 11, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 784         [745] = {47, 12, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 785         [746] = {47, 13, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 786         [747] = {47, 14, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 787         [748] = {47, 15, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 788         [749] = {47, 16, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 789         [750] = {47, 17, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
 790         [751] = {47, 18, "DEV_TIMER11_TIMER_PWM", "Output clock"},
 791         [752] = {38, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"},
 792         [753] = {38, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
 793         [754] = {38, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 794         [755] = {38, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 795         [756] = {38, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 796         [757] = {38, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 797         [758] = {38, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 798         [759] = {38, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 799         [760] = {38, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 800         [761] = {38, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 801         [762] = {38, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 802         [763] = {38, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 803         [764] = {38, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 804         [765] = {38, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 805         [766] = {38, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 806         [767] = {38, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 807         [768] = {38, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 808         [769] = {38, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
 809         [770] = {38, 18, "DEV_TIMER2_TIMER_PWM", "Output clock"},
 810         [771] = {39, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"},
 811         [772] = {39, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
 812         [773] = {39, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 813         [774] = {39, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 814         [775] = {39, 4, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 815         [776] = {39, 5, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 816         [777] = {39, 6, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 817         [778] = {39, 7, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 818         [779] = {39, 8, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 819         [780] = {39, 9, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 820         [781] = {39, 10, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 821         [782] = {39, 11, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 822         [783] = {39, 12, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 823         [784] = {39, 13, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 824         [785] = {39, 14, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 825         [786] = {39, 15, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 826         [787] = {39, 16, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 827         [788] = {39, 17, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
 828         [789] = {39, 18, "DEV_TIMER3_TIMER_PWM", "Output clock"},
 829         [790] = {40, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"},
 830         [791] = {40, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
 831         [792] = {40, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 832         [793] = {40, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 833         [794] = {40, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 834         [795] = {40, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 835         [796] = {40, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 836         [797] = {40, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 837         [798] = {40, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 838         [799] = {40, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 839         [800] = {40, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 840         [801] = {40, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 841         [802] = {40, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 842         [803] = {40, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 843         [804] = {40, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 844         [805] = {40, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 845         [806] = {40, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 846         [807] = {40, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
 847         [808] = {40, 18, "DEV_TIMER4_TIMER_PWM", "Output clock"},
 848         [809] = {41, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"},
 849         [810] = {41, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
 850         [811] = {41, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 851         [812] = {41, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 852         [813] = {41, 4, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 853         [814] = {41, 5, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 854         [815] = {41, 6, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 855         [816] = {41, 7, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 856         [817] = {41, 8, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 857         [818] = {41, 9, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 858         [819] = {41, 10, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 859         [820] = {41, 11, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 860         [821] = {41, 12, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 861         [822] = {41, 13, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 862         [823] = {41, 14, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 863         [824] = {41, 15, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 864         [825] = {41, 16, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 865         [826] = {41, 17, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
 866         [827] = {41, 18, "DEV_TIMER5_TIMER_PWM", "Output clock"},
 867         [828] = {42, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"},
 868         [829] = {42, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
 869         [830] = {42, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 870         [831] = {42, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 871         [832] = {42, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 872         [833] = {42, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 873         [834] = {42, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 874         [835] = {42, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 875         [836] = {42, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 876         [837] = {42, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 877         [838] = {42, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 878         [839] = {42, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 879         [840] = {42, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 880         [841] = {42, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 881         [842] = {42, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 882         [843] = {42, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 883         [844] = {42, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 884         [845] = {42, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
 885         [846] = {42, 18, "DEV_TIMER6_TIMER_PWM", "Output clock"},
 886         [847] = {43, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"},
 887         [848] = {43, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
 888         [849] = {43, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 889         [850] = {43, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 890         [851] = {43, 4, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 891         [852] = {43, 5, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 892         [853] = {43, 6, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 893         [854] = {43, 7, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 894         [855] = {43, 8, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 895         [856] = {43, 9, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 896         [857] = {43, 10, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 897         [858] = {43, 11, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 898         [859] = {43, 12, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 899         [860] = {43, 13, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 900         [861] = {43, 14, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 901         [862] = {43, 15, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 902         [863] = {43, 16, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 903         [864] = {43, 17, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
 904         [865] = {43, 18, "DEV_TIMER7_TIMER_PWM", "Output clock"},
 905         [866] = {44, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"},
 906         [867] = {44, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
 907         [868] = {44, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 908         [869] = {44, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 909         [870] = {44, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 910         [871] = {44, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 911         [872] = {44, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 912         [873] = {44, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 913         [874] = {44, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 914         [875] = {44, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 915         [876] = {44, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 916         [877] = {44, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 917         [878] = {44, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 918         [879] = {44, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 919         [880] = {44, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 920         [881] = {44, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 921         [882] = {44, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 922         [883] = {44, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
 923         [884] = {44, 18, "DEV_TIMER8_TIMER_PWM", "Output clock"},
 924         [885] = {45, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"},
 925         [886] = {45, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
 926         [887] = {45, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 927         [888] = {45, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 928         [889] = {45, 4, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 929         [890] = {45, 5, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 930         [891] = {45, 6, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 931         [892] = {45, 7, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 932         [893] = {45, 8, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 933         [894] = {45, 9, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 934         [895] = {45, 10, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 935         [896] = {45, 11, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 936         [897] = {45, 12, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 937         [898] = {45, 13, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 938         [899] = {45, 14, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 939         [900] = {45, 15, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 940         [901] = {45, 16, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 941         [902] = {45, 17, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
 942         [903] = {45, 18, "DEV_TIMER9_TIMER_PWM", "Output clock"},
 943         [904] = {151, 0, "DEV_TIMERMGR0_VCLK_CLK", "Input clock"},
 944         [905] = {6, 0, "DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK", "Input clock"},
 945         [906] = {146, 0, "DEV_UART0_FCLK_CLK", "Input muxed clock"},
 946         [907] = {146, 1, "DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0", "Parent input clock option to DEV_UART0_FCLK_CLK"},
 947         [908] = {146, 2, "DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART0_FCLK_CLK"},
 948         [909] = {146, 3, "DEV_UART0_VBUSP_CLK", "Input clock"},
 949         [910] = {152, 0, "DEV_UART1_FCLK_CLK", "Input muxed clock"},
 950         [911] = {152, 1, "DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1", "Parent input clock option to DEV_UART1_FCLK_CLK"},
 951         [912] = {152, 2, "DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART1_FCLK_CLK"},
 952         [913] = {152, 3, "DEV_UART1_VBUSP_CLK", "Input clock"},
 953         [914] = {153, 0, "DEV_UART2_FCLK_CLK", "Input muxed clock"},
 954         [915] = {153, 1, "DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2", "Parent input clock option to DEV_UART2_FCLK_CLK"},
 955         [916] = {153, 2, "DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART2_FCLK_CLK"},
 956         [917] = {153, 3, "DEV_UART2_VBUSP_CLK", "Input clock"},
 957         [918] = {154, 0, "DEV_UART3_FCLK_CLK", "Input muxed clock"},
 958         [919] = {154, 1, "DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3", "Parent input clock option to DEV_UART3_FCLK_CLK"},
 959         [920] = {154, 2, "DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART3_FCLK_CLK"},
 960         [921] = {154, 3, "DEV_UART3_VBUSP_CLK", "Input clock"},
 961         [922] = {155, 0, "DEV_UART4_FCLK_CLK", "Input muxed clock"},
 962         [923] = {155, 1, "DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4", "Parent input clock option to DEV_UART4_FCLK_CLK"},
 963         [924] = {155, 2, "DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART4_FCLK_CLK"},
 964         [925] = {155, 3, "DEV_UART4_VBUSP_CLK", "Input clock"},
 965         [926] = {156, 0, "DEV_UART5_FCLK_CLK", "Input muxed clock"},
 966         [927] = {156, 1, "DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5", "Parent input clock option to DEV_UART5_FCLK_CLK"},
 967         [928] = {156, 2, "DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART5_FCLK_CLK"},
 968         [929] = {156, 3, "DEV_UART5_VBUSP_CLK", "Input clock"},
 969         [930] = {158, 0, "DEV_UART6_FCLK_CLK", "Input muxed clock"},
 970         [931] = {158, 1, "DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6", "Parent input clock option to DEV_UART6_FCLK_CLK"},
 971         [932] = {158, 2, "DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_UART6_FCLK_CLK"},
 972         [933] = {158, 3, "DEV_UART6_VBUSP_CLK", "Input clock"},
 973         [934] = {161, 0, "DEV_USB0_ACLK_CLK", "Input clock"},
 974         [935] = {161, 1, "DEV_USB0_CLK_LPM_CLK", "Input clock"},
 975         [936] = {161, 2, "DEV_USB0_PCLK_CLK", "Input clock"},
 976         [937] = {161, 3, "DEV_USB0_PIPE_REFCLK", "Input clock"},
 977         [938] = {161, 4, "DEV_USB0_PIPE_RXCLK", "Input clock"},
 978         [939] = {161, 5, "DEV_USB0_PIPE_RXFCLK", "Input clock"},
 979         [940] = {161, 6, "DEV_USB0_PIPE_TXFCLK", "Input clock"},
 980         [941] = {161, 7, "DEV_USB0_PIPE_TXMCLK", "Input clock"},
 981         [942] = {161, 8, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
 982         [943] = {161, 9, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
 983         [944] = {161, 10, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
 984         [945] = {161, 11, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
 985         [946] = {161, 12, "DEV_USB0_PIPE_TXCLK", "Output clock"},
 986         [947] = {95, 0, "DEV_VTM0_FIX_REF2_CLK", "Input clock"},
 987         [948] = {95, 1, "DEV_VTM0_FIX_REF_CLK", "Input clock"},
 988         [949] = {95, 2, "DEV_VTM0_VBUSP_CLK", "Input clock"},
 989 };