Bump up version to 0.2
[k3conf/k3conf.git] / soc / am64x / am64x_sec_proxy_info.c
1 /*
2  * AM64X Sec Proxy Info
3  *
4  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5  *
6  *  Redistribution and use in source and binary forms, with or without
7  *  modification, are permitted provided that the following conditions
8  *  are met:
9  *
10  *    Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  *
13  *    Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the
16  *    distribution.
17  *
18  *    Neither the name of Texas Instruments Incorporated nor the names of
19  *    its contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_sec_proxy_info am64x_main_sp_info[] = {
39         [0] = {0, "read", 11, "MAIN_0_R5_0", "response"},
40         [1] = {1, "write", 10, "MAIN_0_R5_0", "low_priority"},
41         [2] = {2, "read", 11, "MAIN_0_R5_1", "response"},
42         [3] = {3, "write", 10, "MAIN_0_R5_1", "low_priority"},
43         [4] = {4, "read", 2, "MAIN_0_R5_2", "response"},
44         [5] = {5, "write", 1, "MAIN_0_R5_2", "low_priority"},
45         [6] = {6, "read", 2, "MAIN_0_R5_3", "response"},
46         [7] = {7, "write", 1, "MAIN_0_R5_3", "low_priority"},
47         [8] = {8, "read", 11, "A53_0", "response"},
48         [9] = {9, "write", 10, "A53_0", "low_priority"},
49         [10] = {10, "read", 6, "A53_1", "response"},
50         [11] = {11, "write", 5, "A53_1", "low_priority"},
51         [12] = {12, "read", 6, "A53_2", "response"},
52         [13] = {13, "write", 5, "A53_2", "low_priority"},
53         [14] = {14, "read", 6, "A53_3", "response"},
54         [15] = {15, "write", 5, "A53_3", "low_priority"},
55         [16] = {16, "read", 6, "M4_0", "response"},
56         [17] = {17, "write", 5, "M4_0", "low_priority"},
57         [18] = {18, "read", 6, "MAIN_1_R5_0", "response"},
58         [19] = {19, "write", 5, "MAIN_1_R5_0", "low_priority"},
59         [20] = {20, "read", 6, "MAIN_1_R5_1", "response"},
60         [21] = {21, "write", 5, "MAIN_1_R5_1", "low_priority"},
61         [22] = {22, "read", 2, "MAIN_1_R5_2", "response"},
62         [23] = {23, "write", 1, "MAIN_1_R5_2", "low_priority"},
63         [24] = {24, "read", 2, "MAIN_1_R5_3", "response"},
64         [25] = {25, "write", 1, "MAIN_1_R5_3", "low_priority"},
65         [26] = {26, "read", 2, "ICSSG_0", "response"},
66         [27] = {27, "write", 1, "ICSSG_0", "low_priority"},
67 };