soc: am65x: Add Devices info
[k3conf/k3conf.git] / soc / am65x / am65x_devices_info.c
1 /*
2  * SoC Device Info
3  *
4  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  *  Redistribution and use in source and binary forms, with or without
7  *  modification, are permitted provided that the following conditions
8  *  are met:
9  *
10  *    Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  *
13  *    Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the
16  *    distribution.
17  *
18  *    Neither the name of Texas Instruments Incorporated nor the names of
19  *    its contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_devices_info am65x_devices_info[] = {
39          [0] = {0, "AM6_DEV_MCU_ADC0"},
40          [1] = {1, "AM6_DEV_MCU_ADC1"},
41          [2] = {2, "AM6_DEV_CAL0"},
42          [3] = {3, "AM6_DEV_CMPEVENT_INTRTR0"},
43          [4] = {5, "AM6_DEV_MCU_CPSW0"},
44          [5] = {6, "AM6_DEV_CPT2_AGGR0"},
45          [6] = {7, "AM6_DEV_MCU_CPT2_AGGR0"},
46          [7] = {8, "AM6_DEV_STM0"},
47          [8] = {9, "AM6_DEV_DCC0"},
48          [9] = {10, "AM6_DEV_DCC1"},
49          [10] = {11, "AM6_DEV_DCC2"},
50          [11] = {12, "AM6_DEV_DCC3"},
51          [12] = {13, "AM6_DEV_DCC4"},
52          [13] = {14, "AM6_DEV_DCC5"},
53          [14] = {15, "AM6_DEV_DCC6"},
54          [15] = {16, "AM6_DEV_DCC7"},
55          [16] = {17, "AM6_DEV_MCU_DCC0"},
56          [17] = {18, "AM6_DEV_MCU_DCC1"},
57          [18] = {19, "AM6_DEV_MCU_DCC2"},
58          [19] = {20, "AM6_DEV_DDRSS0"},
59          [20] = {21, "AM6_DEV_DEBUGSS_WRAP0"},
60          [21] = {22, "AM6_DEV_WKUP_DMSC0"},
61          [22] = {23, "AM6_DEV_TIMER0"},
62          [23] = {24, "AM6_DEV_TIMER1"},
63          [24] = {25, "AM6_DEV_TIMER10"},
64          [25] = {26, "AM6_DEV_TIMER11"},
65          [26] = {27, "AM6_DEV_TIMER2"},
66          [27] = {28, "AM6_DEV_TIMER3"},
67          [28] = {29, "AM6_DEV_TIMER4"},
68          [29] = {30, "AM6_DEV_TIMER5"},
69          [30] = {31, "AM6_DEV_TIMER6"},
70          [31] = {32, "AM6_DEV_TIMER7"},
71          [32] = {33, "AM6_DEV_TIMER8"},
72          [33] = {34, "AM6_DEV_TIMER9"},
73          [34] = {35, "AM6_DEV_MCU_TIMER0"},
74          [35] = {36, "AM6_DEV_MCU_TIMER1"},
75          [36] = {37, "AM6_DEV_MCU_TIMER2"},
76          [37] = {38, "AM6_DEV_MCU_TIMER3"},
77          [38] = {39, "AM6_DEV_ECAP0"},
78          [39] = {40, "AM6_DEV_EHRPWM0"},
79          [40] = {41, "AM6_DEV_EHRPWM1"},
80          [41] = {42, "AM6_DEV_EHRPWM2"},
81          [42] = {43, "AM6_DEV_EHRPWM3"},
82          [43] = {44, "AM6_DEV_EHRPWM4"},
83          [44] = {45, "AM6_DEV_EHRPWM5"},
84          [45] = {46, "AM6_DEV_ELM0"},
85          [46] = {47, "AM6_DEV_MMCSD0"},
86          [47] = {48, "AM6_DEV_MMCSD1"},
87          [48] = {49, "AM6_DEV_EQEP0"},
88          [49] = {50, "AM6_DEV_EQEP1"},
89          [50] = {51, "AM6_DEV_EQEP2"},
90          [51] = {52, "AM6_DEV_ESM0"},
91          [52] = {53, "AM6_DEV_MCU_ESM0"},
92          [53] = {54, "AM6_DEV_WKUP_ESM0"},
93          [54] = {55, "AM6_DEV_MCU_FSS0"},
94          [55] = {56, "AM6_DEV_GIC0"},
95          [56] = {57, "AM6_DEV_GPIO0"},
96          [57] = {58, "AM6_DEV_GPIO1"},
97          [58] = {59, "AM6_DEV_WKUP_GPIO0"},
98          [59] = {60, "AM6_DEV_GPMC0"},
99          [60] = {61, "AM6_DEV_GTC0"},
100          [61] = {62, "AM6_DEV_PRU_ICSSG0"},
101          [62] = {63, "AM6_DEV_PRU_ICSSG1"},
102          [63] = {64, "AM6_DEV_PRU_ICSSG2"},
103          [64] = {65, "AM6_DEV_GPU0"},
104          [65] = {66, "AM6_DEV_CCDEBUGSS0"},
105          [66] = {67, "AM6_DEV_DSS0"},
106          [67] = {68, "AM6_DEV_DEBUGSS0"},
107          [68] = {69, "AM6_DEV_EFUSE0"},
108          [69] = {70, "AM6_DEV_PSC0"},
109          [70] = {71, "AM6_DEV_MCU_DEBUGSS0"},
110          [71] = {72, "AM6_DEV_MCU_EFUSE0"},
111          [72] = {73, "AM6_DEV_PBIST0"},
112          [73] = {74, "AM6_DEV_PBIST1"},
113          [74] = {75, "AM6_DEV_MCU_PBIST0"},
114          [75] = {76, "AM6_DEV_PLLCTRL0"},
115          [76] = {77, "AM6_DEV_WKUP_PLLCTRL0"},
116          [77] = {78, "AM6_DEV_MCU_ROM0"},
117          [78] = {79, "AM6_DEV_WKUP_PSC0"},
118          [79] = {80, "AM6_DEV_WKUP_VTM0"},
119          [80] = {81, "AM6_DEV_DEBUGSUSPENDRTR0"},
120          [81] = {82, "AM6_DEV_CBASS0"},
121          [82] = {83, "AM6_DEV_CBASS_DEBUG0"},
122          [83] = {84, "AM6_DEV_CBASS_FW0"},
123          [84] = {85, "AM6_DEV_CBASS_INFRA0"},
124          [85] = {86, "AM6_DEV_ECC_AGGR0"},
125          [86] = {87, "AM6_DEV_ECC_AGGR1"},
126          [87] = {88, "AM6_DEV_ECC_AGGR2"},
127          [88] = {89, "AM6_DEV_MCU_CBASS0"},
128          [89] = {90, "AM6_DEV_MCU_CBASS_DEBUG0"},
129          [90] = {91, "AM6_DEV_MCU_CBASS_FW0"},
130          [91] = {92, "AM6_DEV_MCU_ECC_AGGR0"},
131          [92] = {93, "AM6_DEV_MCU_ECC_AGGR1"},
132          [93] = {94, "AM6_DEV_WKUP_CBASS0"},
133          [94] = {95, "AM6_DEV_WKUP_ECC_AGGR0"},
134          [95] = {96, "AM6_DEV_WKUP_CBASS_FW0"},
135          [96] = {97, "AM6_DEV_MAIN2MCU_LVL_INTRTR0"},
136          [97] = {98, "AM6_DEV_MAIN2MCU_PLS_INTRTR0"},
137          [98] = {99, "AM6_DEV_CTRL_MMR0"},
138          [99] = {100, "AM6_DEV_GPIOMUX_INTRTR0"},
139          [100] = {101, "AM6_DEV_PLL_MMR0"},
140          [101] = {102, "AM6_DEV_MCU_MCAN0"},
141          [102] = {103, "AM6_DEV_MCU_MCAN1"},
142          [103] = {104, "AM6_DEV_MCASP0"},
143          [104] = {105, "AM6_DEV_MCASP1"},
144          [105] = {106, "AM6_DEV_MCASP2"},
145          [106] = {107, "AM6_DEV_MCU_CTRL_MMR0"},
146          [107] = {108, "AM6_DEV_MCU_PLL_MMR0"},
147          [108] = {109, "AM6_DEV_MCU_SEC_MMR0"},
148          [109] = {110, "AM6_DEV_I2C0"},
149          [110] = {111, "AM6_DEV_I2C1"},
150          [111] = {112, "AM6_DEV_I2C2"},
151          [112] = {113, "AM6_DEV_I2C3"},
152          [113] = {114, "AM6_DEV_MCU_I2C0"},
153          [114] = {115, "AM6_DEV_WKUP_I2C0"},
154          [115] = {116, "AM6_DEV_MCU_MSRAM0"},
155          [116] = {117, "AM6_DEV_DFTSS0"},
156          [117] = {118, "AM6_DEV_NAVSS0"},
157          [118] = {119, "AM6_DEV_MCU_NAVSS0"},
158          [119] = {120, "AM6_DEV_PCIE0"},
159          [120] = {121, "AM6_DEV_PCIE1"},
160          [121] = {122, "AM6_DEV_PDMA_DEBUG0"},
161          [122] = {123, "AM6_DEV_PDMA0"},
162          [123] = {124, "AM6_DEV_PDMA1"},
163          [124] = {125, "AM6_DEV_MCU_PDMA0"},
164          [125] = {126, "AM6_DEV_MCU_PDMA1"},
165          [126] = {127, "AM6_DEV_MCU_PSRAM0"},
166          [127] = {128, "AM6_DEV_PSRAMECC0"},
167          [128] = {129, "AM6_DEV_MCU_ARMSS0"},
168          [129] = {130, "AM6_DEV_RTI0"},
169          [130] = {131, "AM6_DEV_RTI1"},
170          [131] = {132, "AM6_DEV_RTI2"},
171          [132] = {133, "AM6_DEV_RTI3"},
172          [133] = {134, "AM6_DEV_MCU_RTI0"},
173          [134] = {135, "AM6_DEV_MCU_RTI1"},
174          [135] = {136, "AM6_DEV_SA2_UL0"},
175          [136] = {137, "AM6_DEV_MCSPI0"},
176          [137] = {138, "AM6_DEV_MCSPI1"},
177          [138] = {139, "AM6_DEV_MCSPI2"},
178          [139] = {140, "AM6_DEV_MCSPI3"},
179          [140] = {141, "AM6_DEV_MCSPI4"},
180          [141] = {142, "AM6_DEV_MCU_MCSPI0"},
181          [142] = {143, "AM6_DEV_MCU_MCSPI1"},
182          [143] = {144, "AM6_DEV_MCU_MCSPI2"},
183          [144] = {145, "AM6_DEV_TIMESYNC_INTRTR0"},
184          [145] = {146, "AM6_DEV_UART0"},
185          [146] = {147, "AM6_DEV_UART1"},
186          [147] = {148, "AM6_DEV_UART2"},
187          [148] = {149, "AM6_DEV_MCU_UART0"},
188          [149] = {150, "AM6_DEV_WKUP_UART0"},
189          [150] = {151, "AM6_DEV_USB3SS0"},
190          [151] = {152, "AM6_DEV_USB3SS1"},
191          [152] = {153, "AM6_DEV_SERDES0"},
192          [153] = {154, "AM6_DEV_SERDES1"},
193          [154] = {155, "AM6_DEV_WKUP_CTRL_MMR0"},
194          [155] = {156, "AM6_DEV_WKUP_GPIOMUX_INTRTR0"},
195          [156] = {157, "AM6_DEV_BOARD0"},
196          [157] = {159, "AM6_DEV_MCU_ARMSS0_CPU0"},
197          [158] = {161, "AM6_DEV_WKUP_DMSC0_CORTEX_M3_0"},
198          [159] = {162, "AM6_DEV_WKUP_DMSC0_INTR_AGGR_0"},
199          [160] = {163, "AM6_DEV_NAVSS0_CPTS0"},
200          [161] = {164, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0"},
201          [162] = {165, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1"},
202          [163] = {166, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2"},
203          [164] = {167, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3"},
204          [165] = {168, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4"},
205          [166] = {169, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5"},
206          [167] = {170, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6"},
207          [168] = {171, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7"},
208          [169] = {172, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8"},
209          [170] = {173, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9"},
210          [171] = {174, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10"},
211          [172] = {175, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11"},
212          [173] = {176, "AM6_DEV_NAVSS0_MCRC0"},
213          [174] = {177, "AM6_DEV_NAVSS0_PVU0"},
214          [175] = {178, "AM6_DEV_NAVSS0_PVU1"},
215          [176] = {179, "AM6_DEV_NAVSS0_UDMASS_INTA0"},
216          [177] = {180, "AM6_DEV_NAVSS0_MODSS_INTA0"},
217          [178] = {181, "AM6_DEV_NAVSS0_MODSS_INTA1"},
218          [179] = {182, "AM6_DEV_NAVSS0_INTR_ROUTER_0"},
219          [180] = {183, "AM6_DEV_NAVSS0_TIMER_MGR0"},
220          [181] = {184, "AM6_DEV_NAVSS0_TIMER_MGR1"},
221          [182] = {185, "AM6_DEV_NAVSS0_PROXY0"},
222          [183] = {186, "AM6_DEV_NAVSS0_SEC_PROXY0"},
223          [184] = {187, "AM6_DEV_NAVSS0_RINGACC0"},
224          [185] = {188, "AM6_DEV_NAVSS0_UDMAP0"},
225          [186] = {189, "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0"},
226          [187] = {190, "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0"},
227          [188] = {191, "AM6_DEV_MCU_NAVSS0_PROXY0"},
228          [189] = {192, "AM6_DEV_MCU_NAVSS0_SEC_PROXY0"},
229          [190] = {193, "AM6_DEV_MCU_NAVSS0_MCRC0"},
230          [191] = {194, "AM6_DEV_MCU_NAVSS0_UDMAP0"},
231          [192] = {195, "AM6_DEV_MCU_NAVSS0_RINGACC0"},
232          [193] = {196, "AM6_DEV_COMPUTE_CLUSTER_MSMC0"},
233          [194] = {197, "AM6_DEV_COMPUTE_CLUSTER_PBIST0"},
234          [195] = {198, "AM6_DEV_COMPUTE_CLUSTER_CPAC0"},
235          [196] = {199, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0"},
236          [197] = {200, "AM6_DEV_COMPUTE_CLUSTER_CPAC1"},
237          [198] = {201, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1"},
238          [199] = {202, "AM6_DEV_COMPUTE_CLUSTER_A53_0"},
239          [200] = {203, "AM6_DEV_COMPUTE_CLUSTER_A53_1"},
240          [201] = {204, "AM6_DEV_COMPUTE_CLUSTER_A53_2"},
241          [202] = {205, "AM6_DEV_COMPUTE_CLUSTER_A53_3"},
242          [203] = {206, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4"},
243          [204] = {207, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3"},
244          [205] = {208, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0"},
245          [206] = {209, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3"},
246          [207] = {210, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1"},
247          [208] = {211, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5"},
248          [209] = {212, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6"},
249          [210] = {213, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0"},
250          [211] = {214, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2"},
251          [212] = {215, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2"},
252          [213] = {216, "AM6_DEV_OLDI_TX_CORE_MAIN_0"},
253          [214] = {217, "AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0"},
254          [215] = {218, "AM6_DEV_ICEMELTER_WKUP_0"},
255          [216] = {219, "AM6_DEV_K3_LED_MAIN_0"},
256          [217] = {220, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU"},
257          [218] = {221, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP"},
258          [219] = {222, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU"},
259          [220] = {223, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN"},
260          [221] = {224, "AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC"},
261          [222] = {225, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA"},
262          [223] = {226, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA"},
263          [224] = {227, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU"},
264          [225] = {228, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN"},
265          [226] = {229, "AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU"},
266          [227] = {230, "AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU"},
267          [228] = {231, "AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0"},
268          [229] = {232, "AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0"},
269          [230] = {233, "AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0"},
270          [231] = {234, "AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0"},
271          [232] = {235, "AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0"},
272          [233] = {236, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU"},
273          [234] = {237, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA"},
274          [235] = {238, "AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC"},
275          [236] = {239, "AM6_DEV_DUMMY_IP_LPSC_DMSC"},
276          [237] = {240, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA"},
277          [238] = {241, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN"},
278          [239] = {242, "AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP"},
279          [240] = {243, "AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU"},
280          [241] = {244, "AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA"},
281          [242] = {245, "AM6_DEV_MCU_ARMSS0_CPU1"},
282 };