Bump up version to 0.2
[k3conf/k3conf.git] / soc / am65x_sr2 / am65x_sr2_clocks_info.c
1 /*
2  * AM65X_SR2 Clocks Info
3  *
4  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5  *
6  *  Redistribution and use in source and binary forms, with or without
7  *  modification, are permitted provided that the following conditions
8  *  are met:
9  *
10  *    Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  *
13  *    Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the
16  *    distribution.
17  *
18  *    Neither the name of Texas Instruments Incorporated nor the names of
19  *    its contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_clocks_info am65x_sr2_clocks_info[] = {
39         [0] = {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"},
40         [1] = {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"},
41         [2] = {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
42         [3] = {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
43         [4] = {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
44         [5] = {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
45         [6] = {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"},
46         [7] = {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"},
47         [8] = {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
48         [9] = {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
49         [10] = {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
50         [11] = {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
51         [12] = {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
52         [13] = {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
53         [14] = {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
54         [15] = {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
55         [16] = {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
56         [17] = {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
57         [18] = {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
58         [19] = {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
59         [20] = {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
60         [21] = {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
61         [22] = {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
62         [23] = {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
63         [24] = {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"},
64         [25] = {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
65         [26] = {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
66         [27] = {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
67         [28] = {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
68         [29] = {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
69         [30] = {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
70         [31] = {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
71         [32] = {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
72         [33] = {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
73         [34] = {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
74         [35] = {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
75         [36] = {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
76         [37] = {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"},
77         [38] = {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"},
78         [39] = {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"},
79         [40] = {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
80         [41] = {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
81         [42] = {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
82         [43] = {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
83         [44] = {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"},
84         [45] = {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"},
85         [46] = {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
86         [47] = {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
87         [48] = {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"},
88         [49] = {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"},
89         [50] = {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"},
90         [51] = {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"},
91         [52] = {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"},
92         [53] = {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"},
93         [54] = {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"},
94         [55] = {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"},
95         [56] = {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"},
96         [57] = {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"},
97         [58] = {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"},
98         [59] = {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"},
99         [60] = {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"},
100         [61] = {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"},
101         [62] = {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"},
102         [63] = {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"},
103         [64] = {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"},
104         [65] = {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"},
105         [66] = {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"},
106         [67] = {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"},
107         [68] = {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"},
108         [69] = {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"},
109         [70] = {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"},
110         [71] = {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"},
111         [72] = {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"},
112         [73] = {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"},
113         [74] = {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"},
114         [75] = {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"},
115         [76] = {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"},
116         [77] = {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"},
117         [78] = {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"},
118         [79] = {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"},
119         [80] = {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"},
120         [81] = {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"},
121         [82] = {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
122         [83] = {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"},
123         [84] = {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"},
124         [85] = {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"},
125         [86] = {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"},
126         [87] = {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"},
127         [88] = {157, 119, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_OUT", "Output clock"},
128         [89] = {157, 120, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_OUT", "Output clock"},
129         [90] = {157, 121, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_OUT", "Output clock"},
130         [91] = {157, 122, "DEV_BOARD0_BUS_PRG1_RGMII2_TCLK_OUT", "Output clock"},
131         [92] = {157, 123, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_OUT", "Output clock"},
132         [93] = {157, 124, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_OUT", "Output clock"},
133         [94] = {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"},
134         [95] = {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"},
135         [96] = {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
136         [97] = {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
137         [98] = {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
138         [99] = {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
139         [100] = {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
140         [101] = {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
141         [102] = {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"},
142         [103] = {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
143         [104] = {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
144         [105] = {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
145         [106] = {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
146         [107] = {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
147         [108] = {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
148         [109] = {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
149         [110] = {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
150         [111] = {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
151         [112] = {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
152         [113] = {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"},
153         [114] = {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"},
154         [115] = {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"},
155         [116] = {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"},
156         [117] = {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"},
157         [118] = {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"},
158         [119] = {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"},
159         [120] = {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"},
160         [121] = {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"},
161         [122] = {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"},
162         [123] = {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"},
163         [124] = {197, 0, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVH_CLK4_CLK_CLK", "Input clock"},
164         [125] = {197, 1, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVP_CLK1_CLK_CLK", "Input clock"},
165         [126] = {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
166         [127] = {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"},
167         [128] = {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"},
168         [129] = {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"},
169         [130] = {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"},
170         [131] = {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"},
171         [132] = {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"},
172         [133] = {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"},
173         [134] = {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"},
174         [135] = {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"},
175         [136] = {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"},
176         [137] = {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"},
177         [138] = {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"},
178         [139] = {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"},
179         [140] = {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"},
180         [141] = {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"},
181         [142] = {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"},
182         [143] = {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"},
183         [144] = {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"},
184         [145] = {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"},
185         [146] = {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"},
186         [147] = {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
187         [148] = {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
188         [149] = {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
189         [150] = {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
190         [151] = {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"},
191         [152] = {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
192         [153] = {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
193         [154] = {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
194         [155] = {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
195         [156] = {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
196         [157] = {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
197         [158] = {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
198         [159] = {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
199         [160] = {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
200         [161] = {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
201         [162] = {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
202         [163] = {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
203         [164] = {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"},
204         [165] = {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
205         [166] = {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
206         [167] = {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
207         [168] = {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
208         [169] = {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
209         [170] = {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
210         [171] = {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
211         [172] = {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
212         [173] = {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
213         [174] = {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
214         [175] = {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
215         [176] = {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
216         [177] = {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"},
217         [178] = {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
218         [179] = {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
219         [180] = {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
220         [181] = {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
221         [182] = {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
222         [183] = {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
223         [184] = {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
224         [185] = {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
225         [186] = {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"},
226         [187] = {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"},
227         [188] = {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"},
228         [189] = {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"},
229         [190] = {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"},
230         [191] = {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"},
231         [192] = {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"},
232         [193] = {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"},
233         [194] = {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"},
234         [195] = {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"},
235         [196] = {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"},
236         [197] = {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"},
237         [198] = {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"},
238         [199] = {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"},
239         [200] = {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"},
240         [201] = {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"},
241         [202] = {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"},
242         [203] = {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"},
243         [204] = {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"},
244         [205] = {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"},
245         [206] = {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"},
246         [207] = {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"},
247         [208] = {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"},
248         [209] = {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"},
249         [210] = {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"},
250         [211] = {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"},
251         [212] = {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"},
252         [213] = {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"},
253         [214] = {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"},
254         [215] = {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"},
255         [216] = {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"},
256         [217] = {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"},
257         [218] = {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"},
258         [219] = {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"},
259         [220] = {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"},
260         [221] = {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"},
261         [222] = {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"},
262         [223] = {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"},
263         [224] = {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"},
264         [225] = {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"},
265         [226] = {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"},
266         [227] = {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"},
267         [228] = {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"},
268         [229] = {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"},
269         [230] = {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"},
270         [231] = {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"},
271         [232] = {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"},
272         [233] = {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"},
273         [234] = {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"},
274         [235] = {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"},
275         [236] = {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"},
276         [237] = {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"},
277         [238] = {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"},
278         [239] = {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"},
279         [240] = {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"},
280         [241] = {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"},
281         [242] = {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"},
282         [243] = {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"},
283         [244] = {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"},
284         [245] = {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"},
285         [246] = {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"},
286         [247] = {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"},
287         [248] = {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"},
288         [249] = {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"},
289         [250] = {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"},
290         [251] = {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
291         [252] = {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"},
292         [253] = {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
293         [254] = {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
294         [255] = {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"},
295         [256] = {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
296         [257] = {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
297         [258] = {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
298         [259] = {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
299         [260] = {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"},
300         [261] = {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
301         [262] = {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
302         [263] = {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"},
303         [264] = {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
304         [265] = {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
305         [266] = {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
306         [267] = {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
307         [268] = {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"},
308         [269] = {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"},
309         [270] = {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"},
310         [271] = {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"},
311         [272] = {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"},
312         [273] = {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"},
313         [274] = {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"},
314         [275] = {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"},
315         [276] = {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"},
316         [277] = {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
317         [278] = {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
318         [279] = {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
319         [280] = {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"},
320         [281] = {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"},
321         [282] = {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"},
322         [283] = {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
323         [284] = {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
324         [285] = {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"},
325         [286] = {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"},
326         [287] = {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"},
327         [288] = {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"},
328         [289] = {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"},
329         [290] = {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"},
330         [291] = {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"},
331         [292] = {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"},
332         [293] = {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"},
333         [294] = {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"},
334         [295] = {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"},
335         [296] = {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"},
336         [297] = {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"},
337         [298] = {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"},
338         [299] = {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"},
339         [300] = {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"},
340         [301] = {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
341         [302] = {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"},
342         [303] = {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
343         [304] = {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
344         [305] = {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
345         [306] = {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
346         [307] = {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"},
347         [308] = {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"},
348         [309] = {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"},
349         [310] = {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"},
350         [311] = {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"},
351         [312] = {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"},
352         [313] = {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"},
353         [314] = {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
354         [315] = {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"},
355         [316] = {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
356         [317] = {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"},
357         [318] = {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"},
358         [319] = {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
359         [320] = {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
360         [321] = {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
361         [322] = {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
362         [323] = {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
363         [324] = {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
364         [325] = {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
365         [326] = {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
366         [327] = {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"},
367         [328] = {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"},
368         [329] = {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"},
369         [330] = {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"},
370         [331] = {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"},
371         [332] = {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"},
372         [333] = {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"},
373         [334] = {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"},
374         [335] = {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"},
375         [336] = {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"},
376         [337] = {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"},
377         [338] = {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"},
378         [339] = {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
379         [340] = {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
380         [341] = {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
381         [342] = {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
382         [343] = {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
383         [344] = {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
384         [345] = {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
385         [346] = {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
386         [347] = {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"},
387         [348] = {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"},
388         [349] = {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
389         [350] = {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
390         [351] = {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
391         [352] = {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
392         [353] = {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
393         [354] = {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
394         [355] = {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
395         [356] = {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
396         [357] = {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"},
397         [358] = {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"},
398         [359] = {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
399         [360] = {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
400         [361] = {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
401         [362] = {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
402         [363] = {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
403         [364] = {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
404         [365] = {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
405         [366] = {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
406         [367] = {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"},
407         [368] = {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
408         [369] = {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
409         [370] = {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
410         [371] = {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
411         [372] = {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
412         [373] = {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
413         [374] = {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
414         [375] = {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
415         [376] = {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
416         [377] = {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
417         [378] = {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
418         [379] = {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
419         [380] = {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"},
420         [381] = {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"},
421         [382] = {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"},
422         [383] = {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"},
423         [384] = {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"},
424         [385] = {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"},
425         [386] = {141, 2, "DEV_MCSPI4_BUS_IO_CLKSPII_CLK", "Input clock"},
426         [387] = {141, 3, "DEV_MCSPI4_BUS_IO_CLKSPIO_CLK", "Output clock"},
427         [388] = {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"},
428         [389] = {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"},
429         [390] = {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"},
430         [391] = {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
431         [392] = {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
432         [393] = {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
433         [394] = {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
434         [395] = {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"},
435         [396] = {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"},
436         [397] = {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"},
437         [398] = {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
438         [399] = {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
439         [400] = {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
440         [401] = {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
441         [402] = {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"},
442         [403] = {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"},
443         [404] = {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"},
444         [405] = {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"},
445         [406] = {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
446         [407] = {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
447         [408] = {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"},
448         [409] = {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"},
449         [410] = {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"},
450         [411] = {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"},
451         [412] = {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
452         [413] = {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
453         [414] = {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"},
454         [415] = {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
455         [416] = {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
456         [417] = {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
457         [418] = {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
458         [419] = {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
459         [420] = {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"},
460         [421] = {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
461         [422] = {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"},
462         [423] = {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"},
463         [424] = {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
464         [425] = {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
465         [426] = {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"},
466         [427] = {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
467         [428] = {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
468         [429] = {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"},
469         [430] = {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"},
470         [431] = {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
471         [432] = {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
472         [433] = {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
473         [434] = {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"},
474         [435] = {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
475         [436] = {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
476         [437] = {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"},
477         [438] = {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
478         [439] = {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
479         [440] = {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
480         [441] = {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
481         [442] = {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
482         [443] = {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
483         [444] = {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
484         [445] = {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
485         [446] = {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
486         [447] = {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
487         [448] = {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
488         [449] = {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
489         [450] = {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"},
490         [451] = {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
491         [452] = {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
492         [453] = {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
493         [454] = {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
494         [455] = {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
495         [456] = {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
496         [457] = {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
497         [458] = {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
498         [459] = {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
499         [460] = {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
500         [461] = {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
501         [462] = {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
502         [463] = {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"},
503         [464] = {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
504         [465] = {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
505         [466] = {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
506         [467] = {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
507         [468] = {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
508         [469] = {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
509         [470] = {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
510         [471] = {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
511         [472] = {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
512         [473] = {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
513         [474] = {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
514         [475] = {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
515         [476] = {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
516         [477] = {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
517         [478] = {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
518         [479] = {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
519         [480] = {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
520         [481] = {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"},
521         [482] = {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"},
522         [483] = {247, 0, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"},
523         [484] = {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"},
524         [485] = {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"},
525         [486] = {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"},
526         [487] = {248, 0, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK", "Input muxed clock"},
527         [488] = {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"},
528         [489] = {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"},
529         [490] = {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK", "Input muxed clock"},
530         [491] = {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"},
531         [492] = {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"},
532         [493] = {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_PCLK_CLK", "Input clock"},
533         [494] = {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_DQS_CLK", "Input clock"},
534         [495] = {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_HCLK_CLK", "Input clock"},
535         [496] = {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_OCLK_CLK", "Output clock"},
536         [497] = {249, 0, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_PCLK_CLK", "Input clock"},
537         [498] = {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK", "Input muxed clock"},
538         [499] = {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"},
539         [500] = {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"},
540         [501] = {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_HCLK_CLK", "Input clock"},
541         [502] = {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_DQS_CLK", "Input clock"},
542         [503] = {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK", "Input muxed clock"},
543         [504] = {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"},
544         [505] = {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"},
545         [506] = {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_OCLK_CLK", "Output clock"},
546         [507] = {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"},
547         [508] = {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"},
548         [509] = {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
549         [510] = {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
550         [511] = {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
551         [512] = {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
552         [513] = {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
553         [514] = {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"},
554         [515] = {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
555         [516] = {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
556         [517] = {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
557         [518] = {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
558         [519] = {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
559         [520] = {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"},
560         [521] = {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
561         [522] = {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
562         [523] = {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
563         [524] = {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
564         [525] = {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
565         [526] = {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
566         [527] = {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
567         [528] = {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
568         [529] = {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
569         [530] = {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
570         [531] = {144, 2, "DEV_MCU_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
571         [532] = {144, 3, "DEV_MCU_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
572         [533] = {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"},
573         [534] = {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"},
574         [535] = {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"},
575         [536] = {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
576         [537] = {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"},
577         [538] = {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"},
578         [539] = {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"},
579         [540] = {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"},
580         [541] = {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"},
581         [542] = {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"},
582         [543] = {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
583         [544] = {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"},
584         [545] = {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"},
585         [546] = {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"},
586         [547] = {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
587         [548] = {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
588         [549] = {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
589         [550] = {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
590         [551] = {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"},
591         [552] = {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"},
592         [553] = {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
593         [554] = {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
594         [555] = {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
595         [556] = {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
596         [557] = {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"},
597         [558] = {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"},
598         [559] = {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
599         [560] = {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
600         [561] = {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
601         [562] = {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
602         [563] = {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
603         [564] = {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
604         [565] = {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
605         [566] = {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
606         [567] = {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
607         [568] = {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
608         [569] = {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
609         [570] = {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
610         [571] = {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
611         [572] = {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
612         [573] = {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
613         [574] = {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
614         [575] = {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
615         [576] = {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
616         [577] = {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
617         [578] = {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
618         [579] = {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
619         [580] = {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
620         [581] = {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
621         [582] = {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
622         [583] = {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
623         [584] = {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
624         [585] = {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
625         [586] = {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
626         [587] = {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
627         [588] = {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
628         [589] = {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
629         [590] = {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
630         [591] = {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
631         [592] = {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
632         [593] = {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
633         [594] = {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
634         [595] = {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"},
635         [596] = {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
636         [597] = {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
637         [598] = {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"},
638         [599] = {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
639         [600] = {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
640         [601] = {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
641         [602] = {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
642         [603] = {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"},
643         [604] = {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"},
644         [605] = {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
645         [606] = {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"},
646         [607] = {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
647         [608] = {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
648         [609] = {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
649         [610] = {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"},
650         [611] = {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"},
651         [612] = {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
652         [613] = {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"},
653         [614] = {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"},
654         [615] = {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
655         [616] = {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"},
656         [617] = {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"},
657         [618] = {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"},
658         [619] = {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"},
659         [620] = {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"},
660         [621] = {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"},
661         [622] = {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"},
662         [623] = {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"},
663         [624] = {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"},
664         [625] = {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
665         [626] = {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"},
666         [627] = {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
667         [628] = {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"},
668         [629] = {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
669         [630] = {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
670         [631] = {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
671         [632] = {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
672         [633] = {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"},
673         [634] = {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"},
674         [635] = {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
675         [636] = {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"},
676         [637] = {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
677         [638] = {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"},
678         [639] = {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
679         [640] = {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
680         [641] = {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
681         [642] = {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
682         [643] = {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"},
683         [644] = {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"},
684         [645] = {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"},
685         [646] = {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"},
686         [647] = {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
687         [648] = {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
688         [649] = {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"},
689         [650] = {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
690         [651] = {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
691         [652] = {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
692         [653] = {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
693         [654] = {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
694         [655] = {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
695         [656] = {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"},
696         [657] = {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"},
697         [658] = {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
698         [659] = {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
699         [660] = {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
700         [661] = {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
701         [662] = {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"},
702         [663] = {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
703         [664] = {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
704         [665] = {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
705         [666] = {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
706         [667] = {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
707         [668] = {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
708         [669] = {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
709         [670] = {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
710         [671] = {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"},
711         [672] = {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
712         [673] = {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
713         [674] = {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"},
714         [675] = {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
715         [676] = {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
716         [677] = {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"},
717         [678] = {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"},
718         [679] = {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
719         [680] = {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
720         [681] = {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"},
721         [682] = {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"},
722         [683] = {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"},
723         [684] = {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
724         [685] = {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
725         [686] = {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
726         [687] = {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
727         [688] = {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
728         [689] = {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
729         [690] = {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
730         [691] = {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
731         [692] = {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"},
732         [693] = {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
733         [694] = {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
734         [695] = {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"},
735         [696] = {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
736         [697] = {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
737         [698] = {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"},
738         [699] = {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"},
739         [700] = {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
740         [701] = {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
741         [702] = {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"},
742         [703] = {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"},
743         [704] = {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"},
744         [705] = {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
745         [706] = {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
746         [707] = {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
747         [708] = {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
748         [709] = {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
749         [710] = {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
750         [711] = {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
751         [712] = {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
752         [713] = {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"},
753         [714] = {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
754         [715] = {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
755         [716] = {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"},
756         [717] = {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"},
757         [718] = {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"},
758         [719] = {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"},
759         [720] = {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"},
760         [721] = {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"},
761         [722] = {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
762         [723] = {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
763         [724] = {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
764         [725] = {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
765         [726] = {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
766         [727] = {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
767         [728] = {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
768         [729] = {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
769         [730] = {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"},
770         [731] = {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"},
771         [732] = {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
772         [733] = {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
773         [734] = {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
774         [735] = {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
775         [736] = {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
776         [737] = {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
777         [738] = {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
778         [739] = {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
779         [740] = {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"},
780         [741] = {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"},
781         [742] = {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
782         [743] = {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
783         [744] = {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
784         [745] = {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
785         [746] = {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
786         [747] = {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
787         [748] = {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
788         [749] = {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
789         [750] = {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"},
790         [751] = {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"},
791         [752] = {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
792         [753] = {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
793         [754] = {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
794         [755] = {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
795         [756] = {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
796         [757] = {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
797         [758] = {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
798         [759] = {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
799         [760] = {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"},
800         [761] = {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"},
801         [762] = {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"},
802         [763] = {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"},
803         [764] = {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"},
804         [765] = {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"},
805         [766] = {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"},
806         [767] = {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"},
807         [768] = {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
808         [769] = {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
809         [770] = {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
810         [771] = {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
811         [772] = {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"},
812         [773] = {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"},
813         [774] = {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"},
814         [775] = {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"},
815         [776] = {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"},
816         [777] = {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"},
817         [778] = {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"},
818         [779] = {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
819         [780] = {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
820         [781] = {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
821         [782] = {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
822         [783] = {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"},
823         [784] = {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"},
824         [785] = {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"},
825         [786] = {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"},
826         [787] = {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"},
827         [788] = {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
828         [789] = {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
829         [790] = {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
830         [791] = {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
831         [792] = {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
832         [793] = {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
833         [794] = {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
834         [795] = {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
835         [796] = {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
836         [797] = {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
837         [798] = {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
838         [799] = {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
839         [800] = {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
840         [801] = {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
841         [802] = {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
842         [803] = {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
843         [804] = {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
844         [805] = {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
845         [806] = {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
846         [807] = {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
847         [808] = {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
848         [809] = {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
849         [810] = {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
850         [811] = {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
851         [812] = {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
852         [813] = {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
853         [814] = {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
854         [815] = {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
855         [816] = {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
856         [817] = {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
857         [818] = {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
858         [819] = {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
859         [820] = {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
860         [821] = {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
861         [822] = {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
862         [823] = {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
863         [824] = {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
864         [825] = {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
865         [826] = {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
866         [827] = {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
867         [828] = {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
868         [829] = {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"},
869         [830] = {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
870         [831] = {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
871         [832] = {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
872         [833] = {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
873         [834] = {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
874         [835] = {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
875         [836] = {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
876         [837] = {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
877         [838] = {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
878         [839] = {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
879         [840] = {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
880         [841] = {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
881         [842] = {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
882         [843] = {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"},
883         [844] = {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
884         [845] = {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
885         [846] = {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
886         [847] = {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
887         [848] = {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
888         [849] = {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
889         [850] = {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
890         [851] = {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
891         [852] = {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
892         [853] = {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
893         [854] = {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
894         [855] = {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
895         [856] = {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
896         [857] = {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
897         [858] = {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
898         [859] = {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
899         [860] = {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
900         [861] = {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
901         [862] = {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
902         [863] = {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
903         [864] = {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
904         [865] = {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
905         [866] = {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
906         [867] = {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
907         [868] = {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
908         [869] = {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
909         [870] = {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
910         [871] = {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
911         [872] = {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
912         [873] = {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
913         [874] = {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
914         [875] = {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
915         [876] = {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
916         [877] = {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
917         [878] = {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
918         [879] = {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
919         [880] = {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
920         [881] = {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
921         [882] = {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
922         [883] = {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
923         [884] = {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
924         [885] = {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"},
925         [886] = {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
926         [887] = {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
927         [888] = {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
928         [889] = {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
929         [890] = {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
930         [891] = {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
931         [892] = {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
932         [893] = {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
933         [894] = {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
934         [895] = {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
935         [896] = {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
936         [897] = {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
937         [898] = {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
938         [899] = {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"},
939         [900] = {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
940         [901] = {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
941         [902] = {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
942         [903] = {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
943         [904] = {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
944         [905] = {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
945         [906] = {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
946         [907] = {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
947         [908] = {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
948         [909] = {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
949         [910] = {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
950         [911] = {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
951         [912] = {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
952         [913] = {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"},
953         [914] = {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
954         [915] = {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
955         [916] = {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
956         [917] = {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
957         [918] = {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
958         [919] = {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
959         [920] = {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
960         [921] = {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
961         [922] = {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
962         [923] = {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
963         [924] = {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
964         [925] = {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
965         [926] = {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
966         [927] = {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"},
967         [928] = {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
968         [929] = {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
969         [930] = {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
970         [931] = {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
971         [932] = {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
972         [933] = {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
973         [934] = {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
974         [935] = {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
975         [936] = {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
976         [937] = {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
977         [938] = {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
978         [939] = {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
979         [940] = {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
980         [941] = {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"},
981         [942] = {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
982         [943] = {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
983         [944] = {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
984         [945] = {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
985         [946] = {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
986         [947] = {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
987         [948] = {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
988         [949] = {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
989         [950] = {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
990         [951] = {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
991         [952] = {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
992         [953] = {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
993         [954] = {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
994         [955] = {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"},
995         [956] = {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"},
996         [957] = {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"},
997         [958] = {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"},
998         [959] = {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"},
999         [960] = {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"},
1000         [961] = {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"},
1001         [962] = {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"},
1002         [963] = {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"},
1003         [964] = {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
1004         [965] = {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"},
1005         [966] = {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
1006         [967] = {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
1007         [968] = {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"},
1008         [969] = {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"},
1009         [970] = {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"},
1010         [971] = {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
1011         [972] = {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
1012         [973] = {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"},
1013         [974] = {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"},
1014         [975] = {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
1015         [976] = {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"},
1016         [977] = {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
1017         [978] = {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
1018         [979] = {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"},
1019         [980] = {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"},
1020         [981] = {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"},
1021         [982] = {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"},
1022         [983] = {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
1023         [984] = {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"},
1024         [985] = {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
1025         [986] = {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
1026         [987] = {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
1027         [988] = {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"},
1028         [989] = {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"},
1029         [990] = {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
1030         [991] = {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
1031         [992] = {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
1032         [993] = {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
1033         [994] = {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
1034         [995] = {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"},
1035         [996] = {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"},
1036         [997] = {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
1037         [998] = {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
1038         [999] = {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
1039         [1000] = {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
1040         [1001] = {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"},
1041         [1002] = {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"},
1042         [1003] = {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"},
1043         [1004] = {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"},
1044         [1005] = {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
1045         [1006] = {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
1046         [1007] = {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"},
1047         [1008] = {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"},
1048         [1009] = {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"},
1049 };