soc: j7200: Update sysfw data corresponding to v2020.08b
[k3conf/k3conf.git] / soc / j7200 / j7200_devices_info.c
1 /*
2  * J7200 Devices Info
3  *
4  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5  *
6  *  Redistribution and use in source and binary forms, with or without
7  *  modification, are permitted provided that the following conditions
8  *  are met:
9  *
10  *    Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  *
13  *    Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the
16  *    distribution.
17  *
18  *    Neither the name of Texas Instruments Incorporated nor the names of
19  *    its contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_devices_info j7200_devices_info[] = {
39         [0] = {0, "J7200_DEV_MCU_ADC0"},
40         [1] = {1, "J7200_DEV_MCU_ADC1"},
41         [2] = {2, "J7200_DEV_ATL0"},
42         [3] = {3, "J7200_DEV_COMPUTE_CLUSTER0"},
43         [4] = {4, "J7200_DEV_A72SS0_CORE0"},
44         [5] = {5, "J7200_DEV_COMPUTE_CLUSTER0_CFG_WRAP"},
45         [6] = {6, "J7200_DEV_COMPUTE_CLUSTER0_CLEC"},
46         [7] = {7, "J7200_DEV_COMPUTE_CLUSTER0_CORE_CORE"},
47         [8] = {8, "J7200_DEV_DDR0"},
48         [9] = {9, "J7200_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP"},
49         [10] = {10, "J7200_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0"},
50         [11] = {11, "J7200_DEV_COMPUTE_CLUSTER0_DIVP_TFT0"},
51         [12] = {12, "J7200_DEV_COMPUTE_CLUSTER0_DMSC_WRAP"},
52         [13] = {13, "J7200_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN"},
53         [14] = {14, "J7200_DEV_COMPUTE_CLUSTER0_GIC500SS"},
54         [15] = {17, "J7200_DEV_COMPUTE_CLUSTER0_PBIST_WRAP"},
55         [16] = {18, "J7200_DEV_MCU_CPSW0"},
56         [17] = {19, "J7200_DEV_CPSW0"},
57         [18] = {20, "J7200_DEV_CPT2_AGGR0"},
58         [19] = {21, "J7200_DEV_CPT2_AGGR1"},
59         [20] = {22, "J7200_DEV_WKUP_DMSC0"},
60         [21] = {23, "J7200_DEV_CPT2_AGGR2"},
61         [22] = {24, "J7200_DEV_MCU_CPT2_AGGR0"},
62         [23] = {25, "J7200_DEV_CPT2_AGGR3"},
63         [24] = {26, "J7200_DEV_CPSW_TX_RGMII0"},
64         [25] = {29, "J7200_DEV_STM0"},
65         [26] = {30, "J7200_DEV_DCC0"},
66         [27] = {31, "J7200_DEV_DCC1"},
67         [28] = {32, "J7200_DEV_DCC2"},
68         [29] = {33, "J7200_DEV_DCC3"},
69         [30] = {34, "J7200_DEV_DCC4"},
70         [31] = {35, "J7200_DEV_MCU_TIMER0"},
71         [32] = {36, "J7200_DEV_DCC5"},
72         [33] = {37, "J7200_DEV_DCC6"},
73         [34] = {39, "J7200_DEV_MAIN0"},
74         [35] = {40, "J7200_DEV_WKUP_WAKEUP0"},
75         [36] = {44, "J7200_DEV_MCU_DCC0"},
76         [37] = {45, "J7200_DEV_MCU_DCC1"},
77         [38] = {46, "J7200_DEV_MCU_DCC2"},
78         [39] = {49, "J7200_DEV_TIMER0"},
79         [40] = {50, "J7200_DEV_TIMER1"},
80         [41] = {51, "J7200_DEV_TIMER2"},
81         [42] = {52, "J7200_DEV_TIMER3"},
82         [43] = {53, "J7200_DEV_TIMER4"},
83         [44] = {54, "J7200_DEV_TIMER5"},
84         [45] = {55, "J7200_DEV_TIMER6"},
85         [46] = {57, "J7200_DEV_TIMER7"},
86         [47] = {58, "J7200_DEV_TIMER8"},
87         [48] = {59, "J7200_DEV_TIMER9"},
88         [49] = {60, "J7200_DEV_TIMER10"},
89         [50] = {61, "J7200_DEV_GTC0"},
90         [51] = {62, "J7200_DEV_TIMER11"},
91         [52] = {63, "J7200_DEV_TIMER12"},
92         [53] = {64, "J7200_DEV_TIMER13"},
93         [54] = {65, "J7200_DEV_TIMER14"},
94         [55] = {66, "J7200_DEV_TIMER15"},
95         [56] = {67, "J7200_DEV_TIMER16"},
96         [57] = {68, "J7200_DEV_TIMER17"},
97         [58] = {69, "J7200_DEV_TIMER18"},
98         [59] = {70, "J7200_DEV_TIMER19"},
99         [60] = {71, "J7200_DEV_MCU_TIMER1"},
100         [61] = {72, "J7200_DEV_MCU_TIMER2"},
101         [62] = {73, "J7200_DEV_MCU_TIMER3"},
102         [63] = {74, "J7200_DEV_MCU_TIMER4"},
103         [64] = {75, "J7200_DEV_MCU_TIMER5"},
104         [65] = {76, "J7200_DEV_MCU_TIMER6"},
105         [66] = {77, "J7200_DEV_MCU_TIMER7"},
106         [67] = {78, "J7200_DEV_MCU_TIMER8"},
107         [68] = {79, "J7200_DEV_MCU_TIMER9"},
108         [69] = {80, "J7200_DEV_ECAP0"},
109         [70] = {81, "J7200_DEV_ECAP1"},
110         [71] = {82, "J7200_DEV_ECAP2"},
111         [72] = {83, "J7200_DEV_EHRPWM0"},
112         [73] = {84, "J7200_DEV_EHRPWM1"},
113         [74] = {85, "J7200_DEV_EHRPWM2"},
114         [75] = {86, "J7200_DEV_EHRPWM3"},
115         [76] = {87, "J7200_DEV_EHRPWM4"},
116         [77] = {88, "J7200_DEV_EHRPWM5"},
117         [78] = {89, "J7200_DEV_ELM0"},
118         [79] = {90, "J7200_DEV_EMIF_DATA_0_VD"},
119         [80] = {91, "J7200_DEV_MMCSD0"},
120         [81] = {92, "J7200_DEV_MMCSD1"},
121         [82] = {94, "J7200_DEV_EQEP0"},
122         [83] = {95, "J7200_DEV_EQEP1"},
123         [84] = {96, "J7200_DEV_EQEP2"},
124         [85] = {97, "J7200_DEV_ESM0"},
125         [86] = {98, "J7200_DEV_MCU_ESM0"},
126         [87] = {99, "J7200_DEV_WKUP_ESM0"},
127         [88] = {100, "J7200_DEV_MCU_FSS0"},
128         [89] = {101, "J7200_DEV_MCU_FSS0_FSAS_0"},
129         [90] = {102, "J7200_DEV_MCU_FSS0_HYPERBUS1P0_0"},
130         [91] = {103, "J7200_DEV_MCU_FSS0_OSPI_0"},
131         [92] = {104, "J7200_DEV_MCU_FSS0_OSPI_1"},
132         [93] = {105, "J7200_DEV_GPIO0"},
133         [94] = {107, "J7200_DEV_GPIO2"},
134         [95] = {109, "J7200_DEV_GPIO4"},
135         [96] = {111, "J7200_DEV_GPIO6"},
136         [97] = {113, "J7200_DEV_WKUP_GPIO0"},
137         [98] = {114, "J7200_DEV_WKUP_GPIO1"},
138         [99] = {115, "J7200_DEV_GPMC0"},
139         [100] = {116, "J7200_DEV_I3C0"},
140         [101] = {117, "J7200_DEV_MCU_I3C0"},
141         [102] = {118, "J7200_DEV_MCU_I3C1"},
142         [103] = {123, "J7200_DEV_CMPEVENT_INTRTR0"},
143         [104] = {127, "J7200_DEV_LED0"},
144         [105] = {128, "J7200_DEV_MAIN2MCU_LVL_INTRTR0"},
145         [106] = {130, "J7200_DEV_MAIN2MCU_PLS_INTRTR0"},
146         [107] = {131, "J7200_DEV_GPIOMUX_INTRTR0"},
147         [108] = {132, "J7200_DEV_WKUP_PORZ_SYNC0"},
148         [109] = {133, "J7200_DEV_PSC0"},
149         [110] = {136, "J7200_DEV_TIMESYNC_INTRTR0"},
150         [111] = {137, "J7200_DEV_WKUP_GPIOMUX_INTRTR0"},
151         [112] = {138, "J7200_DEV_WKUP_PSC0"},
152         [113] = {139, "J7200_DEV_PBIST0"},
153         [114] = {140, "J7200_DEV_PBIST1"},
154         [115] = {141, "J7200_DEV_PBIST2"},
155         [116] = {142, "J7200_DEV_MCU_PBIST0"},
156         [117] = {143, "J7200_DEV_MCU_PBIST1"},
157         [118] = {144, "J7200_DEV_MCU_PBIST2"},
158         [119] = {145, "J7200_DEV_WKUP_DDPA0"},
159         [120] = {146, "J7200_DEV_UART0"},
160         [121] = {149, "J7200_DEV_MCU_UART0"},
161         [122] = {150, "J7200_DEV_MCAN14"},
162         [123] = {151, "J7200_DEV_MCAN15"},
163         [124] = {152, "J7200_DEV_MCAN16"},
164         [125] = {153, "J7200_DEV_MCAN17"},
165         [126] = {154, "J7200_DEV_WKUP_VTM0"},
166         [127] = {155, "J7200_DEV_MAIN2WKUPMCU_VD"},
167         [128] = {156, "J7200_DEV_MCAN0"},
168         [129] = {157, "J7200_DEV_BOARD0"},
169         [130] = {158, "J7200_DEV_MCAN1"},
170         [131] = {160, "J7200_DEV_MCAN2"},
171         [132] = {161, "J7200_DEV_MCAN3"},
172         [133] = {162, "J7200_DEV_MCAN4"},
173         [134] = {163, "J7200_DEV_MCAN5"},
174         [135] = {164, "J7200_DEV_MCAN6"},
175         [136] = {165, "J7200_DEV_MCAN7"},
176         [137] = {166, "J7200_DEV_MCAN8"},
177         [138] = {167, "J7200_DEV_MCAN9"},
178         [139] = {168, "J7200_DEV_MCAN10"},
179         [140] = {169, "J7200_DEV_MCAN11"},
180         [141] = {170, "J7200_DEV_MCAN12"},
181         [142] = {171, "J7200_DEV_MCAN13"},
182         [143] = {172, "J7200_DEV_MCU_MCAN0"},
183         [144] = {173, "J7200_DEV_MCU_MCAN1"},
184         [145] = {174, "J7200_DEV_MCASP0"},
185         [146] = {175, "J7200_DEV_MCASP1"},
186         [147] = {176, "J7200_DEV_MCASP2"},
187         [148] = {187, "J7200_DEV_I2C0"},
188         [149] = {188, "J7200_DEV_I2C1"},
189         [150] = {189, "J7200_DEV_I2C2"},
190         [151] = {190, "J7200_DEV_I2C3"},
191         [152] = {191, "J7200_DEV_I2C4"},
192         [153] = {192, "J7200_DEV_I2C5"},
193         [154] = {193, "J7200_DEV_I2C6"},
194         [155] = {194, "J7200_DEV_MCU_I2C0"},
195         [156] = {195, "J7200_DEV_MCU_I2C1"},
196         [157] = {197, "J7200_DEV_WKUP_I2C0"},
197         [158] = {199, "J7200_DEV_NAVSS0"},
198         [159] = {201, "J7200_DEV_NAVSS0_CPTS_0"},
199         [160] = {202, "J7200_DEV_A72SS0_CORE0_0"},
200         [161] = {203, "J7200_DEV_A72SS0_CORE0_1"},
201         [162] = {206, "J7200_DEV_NAVSS0_DTI_0"},
202         [163] = {207, "J7200_DEV_NAVSS0_MODSS_INTA_0"},
203         [164] = {208, "J7200_DEV_NAVSS0_MODSS_INTA_1"},
204         [165] = {209, "J7200_DEV_NAVSS0_UDMASS_INTA_0"},
205         [166] = {210, "J7200_DEV_NAVSS0_PROXY_0"},
206         [167] = {211, "J7200_DEV_NAVSS0_RINGACC_0"},
207         [168] = {212, "J7200_DEV_NAVSS0_UDMAP_0"},
208         [169] = {213, "J7200_DEV_NAVSS0_INTR_ROUTER_0"},
209         [170] = {214, "J7200_DEV_NAVSS0_MAILBOX_0"},
210         [171] = {215, "J7200_DEV_NAVSS0_MAILBOX_1"},
211         [172] = {216, "J7200_DEV_NAVSS0_MAILBOX_2"},
212         [173] = {217, "J7200_DEV_NAVSS0_MAILBOX_3"},
213         [174] = {218, "J7200_DEV_NAVSS0_MAILBOX_4"},
214         [175] = {219, "J7200_DEV_NAVSS0_MAILBOX_5"},
215         [176] = {220, "J7200_DEV_NAVSS0_MAILBOX_6"},
216         [177] = {221, "J7200_DEV_NAVSS0_MAILBOX_7"},
217         [178] = {222, "J7200_DEV_NAVSS0_MAILBOX_8"},
218         [179] = {223, "J7200_DEV_NAVSS0_MAILBOX_9"},
219         [180] = {224, "J7200_DEV_NAVSS0_MAILBOX_10"},
220         [181] = {225, "J7200_DEV_NAVSS0_MAILBOX_11"},
221         [182] = {226, "J7200_DEV_NAVSS0_SPINLOCK_0"},
222         [183] = {227, "J7200_DEV_NAVSS0_MCRC_0"},
223         [184] = {228, "J7200_DEV_NAVSS0_TBU_0"},
224         [185] = {230, "J7200_DEV_NAVSS0_TIMERMGR_0"},
225         [186] = {231, "J7200_DEV_NAVSS0_TIMERMGR_1"},
226         [187] = {232, "J7200_DEV_MCU_NAVSS0"},
227         [188] = {233, "J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0"},
228         [189] = {234, "J7200_DEV_MCU_NAVSS0_PROXY0"},
229         [190] = {235, "J7200_DEV_MCU_NAVSS0_RINGACC0"},
230         [191] = {236, "J7200_DEV_MCU_NAVSS0_UDMAP_0"},
231         [192] = {237, "J7200_DEV_MCU_NAVSS0_INTR_0"},
232         [193] = {238, "J7200_DEV_MCU_NAVSS0_MCRC_0"},
233         [194] = {240, "J7200_DEV_PCIE1"},
234         [195] = {243, "J7200_DEV_R5FSS0"},
235         [196] = {245, "J7200_DEV_R5FSS0_CORE0"},
236         [197] = {246, "J7200_DEV_R5FSS0_CORE1"},
237         [198] = {249, "J7200_DEV_MCU_R5FSS0"},
238         [199] = {250, "J7200_DEV_MCU_R5FSS0_CORE0"},
239         [200] = {251, "J7200_DEV_MCU_R5FSS0_CORE1"},
240         [201] = {252, "J7200_DEV_RTI0"},
241         [202] = {253, "J7200_DEV_RTI1"},
242         [203] = {258, "J7200_DEV_RTI28"},
243         [204] = {259, "J7200_DEV_RTI29"},
244         [205] = {262, "J7200_DEV_MCU_RTI0"},
245         [206] = {263, "J7200_DEV_MCU_RTI1"},
246         [207] = {265, "J7200_DEV_MCU_SA2_UL0"},
247         [208] = {266, "J7200_DEV_MCSPI0"},
248         [209] = {267, "J7200_DEV_MCSPI1"},
249         [210] = {268, "J7200_DEV_MCSPI2"},
250         [211] = {269, "J7200_DEV_MCSPI3"},
251         [212] = {270, "J7200_DEV_MCSPI4"},
252         [213] = {271, "J7200_DEV_MCSPI5"},
253         [214] = {272, "J7200_DEV_MCSPI6"},
254         [215] = {273, "J7200_DEV_MCSPI7"},
255         [216] = {274, "J7200_DEV_MCU_MCSPI0"},
256         [217] = {275, "J7200_DEV_MCU_MCSPI1"},
257         [218] = {276, "J7200_DEV_MCU_MCSPI2"},
258         [219] = {278, "J7200_DEV_UART1"},
259         [220] = {279, "J7200_DEV_UART2"},
260         [221] = {280, "J7200_DEV_UART3"},
261         [222] = {281, "J7200_DEV_UART4"},
262         [223] = {282, "J7200_DEV_UART5"},
263         [224] = {283, "J7200_DEV_UART6"},
264         [225] = {284, "J7200_DEV_UART7"},
265         [226] = {285, "J7200_DEV_UART8"},
266         [227] = {286, "J7200_DEV_UART9"},
267         [228] = {287, "J7200_DEV_WKUP_UART0"},
268         [229] = {288, "J7200_DEV_USB0"},
269         [230] = {292, "J7200_DEV_SERDES_10G1"},
270         [231] = {298, "J7200_DEV_WKUPMCU2MAIN_VD"},
271         [232] = {299, "J7200_DEV_NAVSS0_MODSS"},
272         [233] = {300, "J7200_DEV_NAVSS0_UDMASS"},
273         [234] = {301, "J7200_DEV_NAVSS0_VIRTSS"},
274         [235] = {302, "J7200_DEV_MCU_NAVSS0_MODSS"},
275         [236] = {303, "J7200_DEV_MCU_NAVSS0_UDMASS"},
276         [237] = {304, "J7200_DEV_DEBUGSS_WRAP0"},
277         [238] = {305, "J7200_DEV_FFI_MAIN_INFRA_CBASS_VD"},
278         [239] = {306, "J7200_DEV_FFI_MAIN_IP_CBASS_VD"},
279         [240] = {307, "J7200_DEV_FFI_MAIN_RC_CBASS_VD"},
280 };