1 /*
2 * J721E Clocks Info
3 *
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_clocks_info j721e_clocks_info[] = {
39 {4, 0, "DEV_A72SS0_PLL_CTRL_CLK", "Input clock"},
40 {4, 1, "DEV_A72SS0_MSMC_CLK", "Input clock"},
41 {4, 2, "DEV_A72SS0_ARM_CLK_CLK", "Input clock"},
42 {202, 2, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
43 {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"},
44 {139, 0, "DEV_AASRC0_SYS_CLK", "Input clock"},
45 {139, 1, "DEV_AASRC0_VBUSP_CLK", "Input clock"},
46 {139, 2, "DEV_AASRC0_RX0_SYNC", "Input muxed clock"},
47 {139, 3, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
48 {139, 4, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
49 {139, 5, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
50 {139, 6, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
51 {139, 7, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
52 {139, 8, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
53 {139, 9, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
54 {139, 10, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
55 {139, 11, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
56 {139, 12, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
57 {139, 13, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
58 {139, 14, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
59 {139, 15, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
60 {139, 16, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
61 {139, 17, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
62 {139, 18, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
63 {139, 19, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
64 {139, 20, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
65 {139, 21, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
66 {139, 22, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
67 {139, 23, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
68 {139, 24, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
69 {139, 25, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
70 {139, 26, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
71 {139, 27, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
72 {139, 28, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
73 {139, 29, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
74 {139, 30, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
75 {139, 31, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
76 {139, 32, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
77 {139, 33, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
78 {139, 34, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
79 {139, 35, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
80 {139, 36, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
81 {139, 37, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
82 {139, 38, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
83 {139, 39, "DEV_AASRC0_RX1_SYNC", "Input muxed clock"},
84 {139, 40, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
85 {139, 41, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
86 {139, 42, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
87 {139, 43, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
88 {139, 44, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
89 {139, 45, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
90 {139, 46, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
91 {139, 47, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
92 {139, 48, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
93 {139, 49, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
94 {139, 50, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
95 {139, 51, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
96 {139, 52, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
97 {139, 53, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
98 {139, 54, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
99 {139, 55, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
100 {139, 56, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
101 {139, 57, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
102 {139, 58, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
103 {139, 59, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
104 {139, 60, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
105 {139, 61, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
106 {139, 62, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
107 {139, 63, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
108 {139, 64, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
109 {139, 65, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
110 {139, 66, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
111 {139, 67, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
112 {139, 68, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
113 {139, 69, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
114 {139, 70, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
115 {139, 71, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
116 {139, 72, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
117 {139, 73, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
118 {139, 74, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
119 {139, 75, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
120 {139, 76, "DEV_AASRC0_RX2_SYNC", "Input muxed clock"},
121 {139, 77, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
122 {139, 78, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
123 {139, 79, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
124 {139, 80, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
125 {139, 81, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
126 {139, 82, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
127 {139, 83, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
128 {139, 84, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
129 {139, 85, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
130 {139, 86, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
131 {139, 87, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
132 {139, 88, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
133 {139, 89, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
134 {139, 90, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
135 {139, 91, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
136 {139, 92, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
137 {139, 93, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
138 {139, 94, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
139 {139, 95, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
140 {139, 96, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
141 {139, 97, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
142 {139, 98, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
143 {139, 99, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
144 {139, 100, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
145 {139, 101, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
146 {139, 102, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
147 {139, 103, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
148 {139, 104, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
149 {139, 105, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
150 {139, 106, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
151 {139, 107, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
152 {139, 108, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
153 {139, 109, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
154 {139, 110, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
155 {139, 111, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
156 {139, 112, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
157 {139, 113, "DEV_AASRC0_RX3_SYNC", "Input muxed clock"},
158 {139, 114, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
159 {139, 115, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
160 {139, 116, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
161 {139, 117, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
162 {139, 118, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
163 {139, 119, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
164 {139, 120, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
165 {139, 121, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
166 {139, 122, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
167 {139, 123, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
168 {139, 124, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
169 {139, 125, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
170 {139, 126, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
171 {139, 127, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
172 {139, 128, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
173 {139, 129, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
174 {139, 130, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
175 {139, 131, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
176 {139, 132, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
177 {139, 133, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
178 {139, 134, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
179 {139, 135, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
180 {139, 136, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
181 {139, 137, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
182 {139, 138, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
183 {139, 139, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
184 {139, 140, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
185 {139, 141, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
186 {139, 142, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
187 {139, 143, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
188 {139, 144, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
189 {139, 145, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
190 {139, 146, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
191 {139, 147, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
192 {139, 148, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
193 {139, 149, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
194 {139, 150, "DEV_AASRC0_TX0_SYNC", "Input muxed clock"},
195 {139, 151, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
196 {139, 152, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
197 {139, 153, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
198 {139, 154, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
199 {139, 155, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
200 {139, 156, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
201 {139, 157, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
202 {139, 158, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
203 {139, 159, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
204 {139, 160, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
205 {139, 161, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
206 {139, 162, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
207 {139, 163, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
208 {139, 164, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
209 {139, 165, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
210 {139, 166, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
211 {139, 167, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
212 {139, 168, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
213 {139, 169, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
214 {139, 170, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
215 {139, 171, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
216 {139, 172, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
217 {139, 173, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
218 {139, 174, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
219 {139, 175, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
220 {139, 176, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
221 {139, 177, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
222 {139, 178, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
223 {139, 179, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
224 {139, 180, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
225 {139, 181, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
226 {139, 182, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
227 {139, 183, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
228 {139, 184, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
229 {139, 185, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
230 {139, 186, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
231 {139, 187, "DEV_AASRC0_TX1_SYNC", "Input muxed clock"},
232 {139, 188, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
233 {139, 189, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
234 {139, 190, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
235 {139, 191, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
236 {139, 192, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
237 {139, 193, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
238 {139, 194, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
239 {139, 195, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
240 {139, 196, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
241 {139, 197, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
242 {139, 198, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
243 {139, 199, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
244 {139, 200, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
245 {139, 201, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
246 {139, 202, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
247 {139, 203, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
248 {139, 204, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
249 {139, 205, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
250 {139, 206, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
251 {139, 207, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
252 {139, 208, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
253 {139, 209, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
254 {139, 210, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
255 {139, 211, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
256 {139, 212, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
257 {139, 213, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
258 {139, 214, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
259 {139, 215, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
260 {139, 216, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
261 {139, 217, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
262 {139, 218, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
263 {139, 219, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
264 {139, 220, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
265 {139, 221, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
266 {139, 222, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
267 {139, 223, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
268 {139, 224, "DEV_AASRC0_TX2_SYNC", "Input muxed clock"},
269 {139, 225, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
270 {139, 226, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
271 {139, 227, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
272 {139, 228, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
273 {139, 229, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
274 {139, 230, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
275 {139, 231, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
276 {139, 232, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
277 {139, 233, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
278 {139, 234, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
279 {139, 235, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
280 {139, 236, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
281 {139, 237, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
282 {139, 238, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
283 {139, 239, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
284 {139, 240, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
285 {139, 241, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
286 {139, 242, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
287 {139, 243, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
288 {139, 244, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
289 {139, 245, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
290 {139, 246, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
291 {139, 247, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
292 {139, 248, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
293 {139, 249, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
294 {139, 250, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
295 {139, 251, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
296 {139, 252, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
297 {139, 253, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
298 {139, 254, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
299 {139, 255, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
300 {139, 256, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
301 {139, 257, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
302 {139, 258, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
303 {139, 259, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
304 {139, 260, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
305 {139, 261, "DEV_AASRC0_TX3_SYNC", "Input muxed clock"},
306 {139, 262, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
307 {139, 263, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
308 {139, 264, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
309 {139, 265, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
310 {139, 266, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
311 {139, 267, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
312 {139, 268, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
313 {139, 269, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
314 {139, 270, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
315 {139, 271, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
316 {139, 272, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
317 {139, 273, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
318 {139, 274, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
319 {139, 275, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
320 {139, 276, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
321 {139, 277, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
322 {139, 278, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
323 {139, 279, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
324 {139, 280, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
325 {139, 281, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
326 {139, 282, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
327 {139, 283, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
328 {139, 284, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
329 {139, 285, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
330 {139, 286, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
331 {139, 287, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
332 {139, 288, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
333 {139, 289, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
334 {139, 290, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
335 {139, 291, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
336 {139, 292, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
337 {139, 293, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
338 {139, 294, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
339 {139, 295, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
340 {139, 296, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
341 {139, 297, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
342 {337, 0, "DEV_ASCPCIE_BUFFER0_CLKIN0", "Input muxed clock"},
343 {337, 1, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"},
344 {337, 2, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"},
345 {337, 3, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"},
346 {337, 4, "DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN0"},
347 {337, 5, "DEV_ASCPCIE_BUFFER0_CLKIN1", "Input muxed clock"},
348 {337, 6, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"},
349 {337, 7, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"},
350 {337, 8, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"},
351 {337, 9, "DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER0_CLKIN1"},
352 {337, 10, "DEV_ASCPCIE_BUFFER0_CLKOUT0_N", "Output clock"},
353 {337, 11, "DEV_ASCPCIE_BUFFER0_CLKOUT0_P", "Output clock"},
354 {337, 12, "DEV_ASCPCIE_BUFFER0_CLKOUT1_N", "Output clock"},
355 {337, 13, "DEV_ASCPCIE_BUFFER0_CLKOUT1_P", "Output clock"},
356 {338, 0, "DEV_ASCPCIE_BUFFER1_CLKIN0", "Input muxed clock"},
357 {338, 1, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"},
358 {338, 2, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"},
359 {338, 3, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"},
360 {338, 4, "DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN0"},
361 {338, 5, "DEV_ASCPCIE_BUFFER1_CLKIN1", "Input muxed clock"},
362 {338, 6, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"},
363 {338, 7, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"},
364 {338, 8, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"},
365 {338, 9, "DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK", "Parent input clock option to DEV_ASCPCIE_BUFFER1_CLKIN1"},
366 {338, 10, "DEV_ASCPCIE_BUFFER1_CLKOUT0_N", "Output clock"},
367 {338, 11, "DEV_ASCPCIE_BUFFER1_CLKOUT0_P", "Output clock"},
368 {338, 12, "DEV_ASCPCIE_BUFFER1_CLKOUT1_N", "Output clock"},
369 {338, 13, "DEV_ASCPCIE_BUFFER1_CLKOUT1_P", "Output clock"},
370 {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"},
371 {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
372 {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
373 {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
374 {2, 4, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
375 {2, 5, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
376 {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
377 {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
378 {2, 8, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
379 {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"},
380 {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
381 {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
382 {157, 0, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
383 {157, 2, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
384 {157, 4, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
385 {157, 6, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
386 {157, 8, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
387 {157, 10, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
388 {157, 12, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
389 {157, 14, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
390 {157, 16, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
391 {157, 18, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
392 {157, 19, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
393 {157, 20, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
394 {157, 21, "DEV_BOARD0_MCU_OSPI1_CLK_IN", "Input clock"},
395 {157, 22, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"},
396 {157, 23, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"},
397 {157, 25, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
398 {157, 27, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
399 {157, 29, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
400 {157, 31, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
401 {157, 33, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
402 {157, 35, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
403 {157, 37, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
404 {157, 38, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
405 {157, 39, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
406 {157, 41, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
407 {157, 42, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
408 {157, 43, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
409 {157, 44, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"},
410 {157, 45, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"},
411 {157, 46, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
412 {157, 47, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
413 {157, 48, "DEV_BOARD0_MCU_I3C1_SCL_IN", "Input clock"},
414 {157, 49, "DEV_BOARD0_MCU_I3C1_SCL_OUT", "Output clock"},
415 {157, 50, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
416 {157, 51, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
417 {157, 52, "DEV_BOARD0_DSI_TXCLKP_IN", "Input clock"},
418 {157, 53, "DEV_BOARD0_DSI_TXCLKN_IN", "Input clock"},
419 {157, 54, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"},
420 {157, 55, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"},
421 {157, 56, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"},
422 {157, 57, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"},
423 {157, 58, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"},
424 {157, 59, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"},
425 {157, 60, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"},
426 {157, 61, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"},
427 {157, 62, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"},
428 {157, 63, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"},
429 {157, 64, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"},
430 {157, 65, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"},
431 {157, 66, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"},
432 {157, 67, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"},
433 {157, 68, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
434 {157, 70, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"},
435 {157, 72, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"},
436 {157, 74, "DEV_BOARD0_RGMII5_RXC_OUT", "Output clock"},
437 {157, 76, "DEV_BOARD0_RGMII6_RXC_OUT", "Output clock"},
438 {157, 78, "DEV_BOARD0_RGMII7_RXC_OUT", "Output clock"},
439 {157, 80, "DEV_BOARD0_RGMII8_RXC_OUT", "Output clock"},
440 {157, 81, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
441 {157, 82, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
442 {157, 83, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
443 {157, 84, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
444 {157, 85, "DEV_BOARD0_MCU_RGMII1_TXC_OUT", "Output clock"},
445 {157, 86, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
446 {157, 87, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
447 {157, 88, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
448 {157, 89, "DEV_BOARD0_UFS0_REF_CLK_IN", "Input clock"},
449 {157, 91, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"},
450 {157, 92, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"},
451 {157, 99, "DEV_BOARD0_MMC0_CLK_IN", "Input clock"},
452 {157, 100, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
453 {157, 101, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"},
454 {157, 102, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
455 {157, 103, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
456 {157, 104, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
457 {157, 105, "DEV_BOARD0_MLB0_MLBCLK_OUT", "Output clock"},
458 {157, 106, "DEV_BOARD0_MLB0_MLBCP_OUT", "Output clock"},
459 {157, 108, "DEV_BOARD0_VPFE0_PCLK_OUT", "Output clock"},
460 {157, 109, "DEV_BOARD0_VOUT1_PCLK_IN", "Input clock"},
461 {157, 110, "DEV_BOARD0_VOUT1_EXTPCLKIN_OUT", "Output clock"},
462 {157, 111, "DEV_BOARD0_VOUT2_PCLK_IN", "Input clock"},
463 {157, 112, "DEV_BOARD0_VOUT2_EXTPCLKIN_OUT", "Output clock"},
464 {157, 113, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
465 {157, 114, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
466 {157, 115, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
467 {157, 116, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
468 {157, 117, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
469 {157, 118, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
470 {157, 119, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
471 {157, 120, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
472 {157, 126, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
473 {157, 127, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
474 {157, 128, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
475 {157, 129, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
476 {157, 130, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
477 {157, 131, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
478 {157, 132, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
479 {157, 133, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
480 {157, 137, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
481 {157, 138, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
482 {157, 139, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
483 {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
484 {157, 141, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
485 {157, 142, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
486 {157, 143, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
487 {157, 144, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
488 {157, 145, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
489 {157, 146, "DEV_BOARD0_OBSCLK1_IN", "Input muxed clock"},
490 {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
491 {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
492 {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
493 {157, 152, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
494 {157, 153, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
495 {157, 154, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
496 {157, 169, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
497 {157, 170, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
498 {157, 171, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
499 {157, 172, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"},
500 {157, 173, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
501 {157, 174, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
502 {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
503 {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
504 {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
505 {157, 178, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
506 {157, 179, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
507 {157, 180, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
508 {157, 181, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
509 {157, 182, "DEV_BOARD0_TCK_OUT", "Output clock"},
510 {157, 183, "DEV_BOARD0_PCIE_REFCLK0P_IN", "Input clock"},
511 {157, 184, "DEV_BOARD0_PCIE_REFCLK0N_IN", "Input clock"},
512 {157, 185, "DEV_BOARD0_PCIE_REFCLK0P_OUT", "Output clock"},
513 {157, 186, "DEV_BOARD0_PCIE_REFCLK0N_OUT", "Output clock"},
514 {157, 187, "DEV_BOARD0_PCIE_REFCLK0P_OUT_IN", "Input clock"},
515 {157, 188, "DEV_BOARD0_PCIE_REFCLK0N_OUT_IN", "Input clock"},
516 {157, 189, "DEV_BOARD0_PCIE_REFCLK1P_IN", "Input clock"},
517 {157, 190, "DEV_BOARD0_PCIE_REFCLK1N_IN", "Input clock"},
518 {157, 191, "DEV_BOARD0_PCIE_REFCLK1P_OUT", "Output clock"},
519 {157, 192, "DEV_BOARD0_PCIE_REFCLK1N_OUT", "Output clock"},
520 {157, 193, "DEV_BOARD0_PCIE_REFCLK1P_OUT_IN", "Input clock"},
521 {157, 194, "DEV_BOARD0_PCIE_REFCLK1N_OUT_IN", "Input clock"},
522 {157, 195, "DEV_BOARD0_PCIE_REFCLK2P_IN", "Input clock"},
523 {157, 196, "DEV_BOARD0_PCIE_REFCLK2N_IN", "Input clock"},
524 {157, 197, "DEV_BOARD0_PCIE_REFCLK2P_OUT", "Output clock"},
525 {157, 198, "DEV_BOARD0_PCIE_REFCLK2N_OUT", "Output clock"},
526 {157, 201, "DEV_BOARD0_PCIE_REFCLK3P_OUT", "Output clock"},
527 {157, 202, "DEV_BOARD0_PCIE_REFCLK3N_OUT", "Output clock"},
528 {157, 203, "DEV_BOARD0_PCIE_REFCLK3P_IN", "Input clock"},
529 {157, 204, "DEV_BOARD0_PCIE_REFCLK3N_IN", "Input clock"},
530 {157, 217, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
531 {157, 218, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
532 {157, 219, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"},
533 {157, 220, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
534 {157, 221, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
535 {157, 222, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"},
536 {157, 223, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
537 {157, 224, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
538 {157, 225, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"},
539 {157, 226, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
540 {157, 227, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
541 {157, 228, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"},
542 {157, 229, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
543 {157, 230, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
544 {157, 231, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"},
545 {157, 232, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
546 {157, 233, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
547 {157, 234, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"},
548 {157, 235, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"},
549 {157, 236, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"},
550 {157, 237, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"},
551 {157, 238, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"},
552 {157, 239, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"},
553 {157, 240, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"},
554 {157, 241, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"},
555 {157, 242, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"},
556 {157, 243, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"},
557 {157, 244, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"},
558 {157, 245, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"},
559 {157, 246, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"},
560 {157, 247, "DEV_BOARD0_MCASP5_ACLKR_IN", "Input clock"},
561 {157, 248, "DEV_BOARD0_MCASP5_ACLKR_OUT", "Output clock"},
562 {157, 249, "DEV_BOARD0_MCASP5_AFSR_OUT", "Output clock"},
563 {157, 250, "DEV_BOARD0_MCASP5_ACLKX_IN", "Input clock"},
564 {157, 251, "DEV_BOARD0_MCASP5_ACLKX_OUT", "Output clock"},
565 {157, 252, "DEV_BOARD0_MCASP5_AFSX_OUT", "Output clock"},
566 {157, 253, "DEV_BOARD0_MCASP6_ACLKR_IN", "Input clock"},
567 {157, 254, "DEV_BOARD0_MCASP6_ACLKR_OUT", "Output clock"},
568 {157, 255, "DEV_BOARD0_MCASP6_AFSR_OUT", "Output clock"},
569 {157, 256, "DEV_BOARD0_MCASP6_ACLKX_IN", "Input clock"},
570 {157, 257, "DEV_BOARD0_MCASP6_ACLKX_OUT", "Output clock"},
571 {157, 258, "DEV_BOARD0_MCASP6_AFSX_OUT", "Output clock"},
572 {157, 259, "DEV_BOARD0_MCASP7_ACLKR_IN", "Input clock"},
573 {157, 260, "DEV_BOARD0_MCASP7_ACLKR_OUT", "Output clock"},
574 {157, 261, "DEV_BOARD0_MCASP7_AFSR_OUT", "Output clock"},
575 {157, 262, "DEV_BOARD0_MCASP7_ACLKX_IN", "Input clock"},
576 {157, 263, "DEV_BOARD0_MCASP7_ACLKX_OUT", "Output clock"},
577 {157, 264, "DEV_BOARD0_MCASP7_AFSX_OUT", "Output clock"},
578 {157, 265, "DEV_BOARD0_MCASP8_ACLKR_IN", "Input clock"},
579 {157, 267, "DEV_BOARD0_MCASP8_ACLKR_OUT", "Output clock"},
580 {157, 268, "DEV_BOARD0_MCASP8_AFSR_OUT", "Output clock"},
581 {157, 269, "DEV_BOARD0_MCASP8_ACLKX_IN", "Input clock"},
582 {157, 270, "DEV_BOARD0_MCASP8_ACLKX_OUT", "Output clock"},
583 {157, 271, "DEV_BOARD0_MCASP8_AFSX_OUT", "Output clock"},
584 {157, 272, "DEV_BOARD0_MCASP9_ACLKR_IN", "Input clock"},
585 {157, 273, "DEV_BOARD0_MCASP9_ACLKR_OUT", "Output clock"},
586 {157, 274, "DEV_BOARD0_MCASP9_AFSR_OUT", "Output clock"},
587 {157, 275, "DEV_BOARD0_MCASP9_ACLKX_IN", "Input clock"},
588 {157, 276, "DEV_BOARD0_MCASP9_ACLKX_OUT", "Output clock"},
589 {157, 278, "DEV_BOARD0_MCASP9_AFSX_OUT", "Output clock"},
590 {157, 279, "DEV_BOARD0_MCASP10_ACLKR_IN", "Input clock"},
591 {157, 280, "DEV_BOARD0_MCASP10_ACLKR_OUT", "Output clock"},
592 {157, 281, "DEV_BOARD0_MCASP10_AFSR_OUT", "Output clock"},
593 {157, 282, "DEV_BOARD0_MCASP10_ACLKX_IN", "Input clock"},
594 {157, 283, "DEV_BOARD0_MCASP10_ACLKX_OUT", "Output clock"},
595 {157, 284, "DEV_BOARD0_MCASP10_AFSX_OUT", "Output clock"},
596 {157, 285, "DEV_BOARD0_MCASP11_ACLKR_IN", "Input clock"},
597 {157, 286, "DEV_BOARD0_MCASP11_ACLKR_OUT", "Output clock"},
598 {157, 287, "DEV_BOARD0_MCASP11_AFSR_OUT", "Output clock"},
599 {157, 288, "DEV_BOARD0_MCASP11_ACLKX_IN", "Input clock"},
600 {157, 289, "DEV_BOARD0_MCASP11_ACLKX_OUT", "Output clock"},
601 {157, 290, "DEV_BOARD0_MCASP11_AFSX_OUT", "Output clock"},
602 {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
603 {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
604 {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
605 {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
606 {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
607 {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
608 {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
609 {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
610 {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
611 {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
612 {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
613 {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
614 {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
615 {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
616 {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
617 {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
618 {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
619 {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
620 {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
621 {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
622 {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
623 {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
624 {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
625 {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
626 {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
627 {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
628 {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
629 {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
630 {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
631 {157, 329, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
632 {157, 330, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
633 {157, 331, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
634 {157, 334, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
635 {157, 335, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
636 {157, 336, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
637 {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
638 {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
639 {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
640 {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
641 {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
642 {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
643 {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
644 {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
645 {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
646 {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
647 {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
648 {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
649 {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
650 {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
651 {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
652 {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
653 {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
654 {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
655 {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
656 {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
657 {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
658 {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
659 {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
660 {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
661 {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
662 {157, 362, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
663 {157, 363, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
664 {157, 364, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
665 {157, 365, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
666 {157, 366, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
667 {157, 369, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
668 {157, 370, "DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT", "Output clock"},
669 {157, 371, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN", "Input muxed clock"},
670 {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
671 {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
672 {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
673 {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
674 {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
675 {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
676 {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
677 {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
678 {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
679 {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
680 {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
681 {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
682 {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
683 {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
684 {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
685 {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
686 {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
687 {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
688 {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
689 {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
690 {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
691 {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
692 {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
693 {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
694 {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
695 {157, 397, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
696 {157, 398, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
697 {157, 399, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
698 {157, 400, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
699 {157, 401, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
700 {157, 404, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
701 {157, 405, "DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT", "Output clock"},
702 {157, 406, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN", "Input muxed clock"},
703 {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
704 {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
705 {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
706 {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
707 {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
708 {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
709 {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
710 {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
711 {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
712 {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
713 {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
714 {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
715 {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
716 {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
717 {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
718 {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
719 {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
720 {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
721 {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
722 {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
723 {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
724 {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
725 {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
726 {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
727 {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
728 {157, 432, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
729 {157, 433, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
730 {157, 434, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
731 {157, 435, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
732 {157, 436, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
733 {157, 439, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
734 {142, 0, "DEV_C66SS0_CORE0_GEM_TRC_CLK", "Input clock"},
735 {142, 1, "DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
736 {142, 4, "DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
737 {142, 6, "DEV_C66SS0_CORE0_GEM_CLKIN_CLK", "Input clock"},
738 {121, 0, "DEV_C66SS0_INTROUTER0_INTR_CLK", "Input clock"},
739 {143, 0, "DEV_C66SS1_CORE0_GEM_TRC_CLK", "Input clock"},
740 {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
741 {143, 4, "DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
742 {143, 6, "DEV_C66SS1_CORE0_GEM_CLKIN_CLK", "Input clock"},
743 {122, 0, "DEV_C66SS1_INTROUTER0_INTR_CLK", "Input clock"},
744 {15, 0, "DEV_C71SS0_C7X_CLK", "Input clock"},
745 {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"},
746 {16, 0, "DEV_C71SS0_MMA_PLL_CTRL_CLK", "Input clock"},
747 {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"},
748 {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"},
749 {5, 0, "DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK", "Input clock"},
750 {6, 0, "DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK", "Input clock"},
751 {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"},
752 {7, 0, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"},
753 {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"},
754 {8, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK", "Input clock"},
755 {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"},
756 {9, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK", "Input clock"},
757 {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"},
758 {12, 0, "DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK", "Input clock"},
759 {13, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK", "Input clock"},
760 {14, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"},
761 {17, 0, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK", "Input clock"},
762 {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"},
763 {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"},
764 {19, 0, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"},
765 {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"},
766 {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"},
767 {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
768 {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"},
769 {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"},
770 {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"},
771 {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"},
772 {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"},
773 {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"},
774 {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"},
775 {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"},
776 {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"},
777 {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"},
778 {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"},
779 {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"},
780 {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
781 {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
782 {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
783 {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
784 {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
785 {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
786 {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
787 {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
788 {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
789 {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
790 {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
791 {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
792 {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
793 {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
794 {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
795 {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
796 {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
797 {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"},
798 {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"},
799 {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"},
800 {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"},
801 {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"},
802 {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"},
803 {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"},
804 {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
805 {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"},
806 {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
807 {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"},
808 {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"},
809 {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"},
810 {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
811 {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"},
812 {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"},
813 {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
814 {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"},
815 {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"},
816 {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"},
817 {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"},
818 {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"},
819 {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"},
820 {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"},
821 {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"},
822 {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"},
823 {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"},
824 {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"},
825 {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"},
826 {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"},
827 {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
828 {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"},
829 {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
830 {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"},
831 {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"},
832 {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
833 {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"},
834 {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"},
835 {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"},
836 {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"},
837 {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"},
838 {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"},
839 {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
840 {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"},
841 {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"},
842 {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"},
843 {19, 79, "DEV_CPSW0_CPTS_GENF0", "Output clock"},
844 {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"},
845 {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"},
846 {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"},
847 {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"},
848 {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"},
849 {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"},
850 {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"},
851 {19, 87, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"},
852 {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
853 {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
854 {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
855 {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"},
856 {25, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"},
857 {26, 0, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"},
858 {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"},
859 {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"},
860 {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"},
861 {27, 0, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"},
862 {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"},
863 {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"},
864 {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"},
865 {28, 0, "DEV_CSI_TX_IF0_ESC_CLK_CLK", "Input clock"},
866 {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"},
867 {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"},
868 {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"},
869 {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
870 {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
871 {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
872 {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
873 {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
874 {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"},
875 {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
876 {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
877 {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
878 {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
879 {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
880 {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
881 {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
882 {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
883 {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
884 {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
885 {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
886 {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
887 {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"},
888 {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
889 {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
890 {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
891 {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
892 {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
893 {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
894 {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
895 {41, 0, "DEV_DCC10_DCC_INPUT10_CLK", "Input clock"},
896 {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"},
897 {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"},
898 {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"},
899 {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"},
900 {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"},
901 {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"},
902 {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"},
903 {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"},
904 {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"},
905 {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"},
906 {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"},
907 {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"},
908 {42, 0, "DEV_DCC11_DCC_INPUT10_CLK", "Input clock"},
909 {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"},
910 {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"},
911 {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"},
912 {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"},
913 {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"},
914 {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"},
915 {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"},
916 {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"},
917 {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"},
918 {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"},
919 {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"},
920 {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"},
921 {43, 0, "DEV_DCC12_DCC_INPUT10_CLK", "Input clock"},
922 {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"},
923 {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"},
924 {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"},
925 {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"},
926 {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"},
927 {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"},
928 {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"},
929 {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"},
930 {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"},
931 {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"},
932 {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"},
933 {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"},
934 {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
935 {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
936 {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
937 {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
938 {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
939 {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"},
940 {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
941 {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
942 {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
943 {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
944 {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
945 {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
946 {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
947 {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
948 {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
949 {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
950 {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
951 {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
952 {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"},
953 {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
954 {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
955 {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
956 {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
957 {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
958 {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
959 {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
960 {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
961 {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
962 {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
963 {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
964 {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
965 {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"},
966 {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
967 {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
968 {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
969 {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
970 {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
971 {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
972 {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
973 {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
974 {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
975 {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
976 {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
977 {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
978 {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"},
979 {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
980 {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
981 {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
982 {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
983 {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"},
984 {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
985 {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
986 {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
987 {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
988 {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
989 {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
990 {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
991 {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"},
992 {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
993 {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
994 {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
995 {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
996 {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
997 {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
998 {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
999 {38, 0, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"},
1000 {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"},
1001 {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"},
1002 {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"},
1003 {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"},
1004 {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"},
1005 {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"},
1006 {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"},
1007 {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"},
1008 {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"},
1009 {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"},
1010 {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"},
1011 {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"},
1012 {39, 0, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"},
1013 {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"},
1014 {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"},
1015 {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"},
1016 {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"},
1017 {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"},
1018 {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"},
1019 {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"},
1020 {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"},
1021 {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"},
1022 {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"},
1023 {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"},
1024 {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"},
1025 {40, 0, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"},
1026 {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"},
1027 {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"},
1028 {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"},
1029 {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"},
1030 {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"},
1031 {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"},
1032 {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"},
1033 {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"},
1034 {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"},
1035 {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"},
1036 {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"},
1037 {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"},
1038 {47, 0, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"},
1039 {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
1040 {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
1041 {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"},
1042 {47, 4, "DEV_DDR0_DDRSS_IO_CK_N", "Output clock"},
1043 {47, 5, "DEV_DDR0_DDRSS_IO_CK", "Output clock"},
1044 {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
1045 {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
1046 {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
1047 {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"},
1048 {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
1049 {144, 0, "DEV_DECODER0_SYS_CLK", "Input clock"},
1050 {48, 0, "DEV_DMPAC0_CLK", "Input clock"},
1051 {48, 1, "DEV_DMPAC0_PLL_DCO_CLK", "Input clock"},
1052 {305, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"},
1053 {147, 0, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"},
1054 {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"},
1055 {148, 0, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"},
1056 {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"},
1057 {296, 0, "DEV_DPHY_TX0_CLK", "Input clock"},
1058 {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"},
1059 {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"},
1060 {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"},
1061 {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1062 {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1063 {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1064 {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1065 {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
1066 {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"},
1067 {296, 10, "DEV_DPHY_TX0_CK_P", "Output clock"},
1068 {296, 11, "DEV_DPHY_TX0_CK_M", "Output clock"},
1069 {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
1070 {152, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"},
1071 {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"},
1072 {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
1073 {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
1074 {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"},
1075 {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1076 {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1077 {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1078 {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1079 {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"},
1080 {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
1081 {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
1082 {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
1083 {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"},
1084 {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1085 {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1086 {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1087 {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1088 {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1089 {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"},
1090 {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"},
1091 {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"},
1092 {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"},
1093 {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"},
1094 {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"},
1095 {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
1096 {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
1097 {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"},
1098 {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
1099 {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
1100 {150, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"},
1101 {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"},
1102 {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"},
1103 {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"},
1104 {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"},
1105 {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"},
1106 {151, 0, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"},
1107 {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"},
1108 {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"},
1109 {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"},
1110 {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"},
1111 {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"},
1112 {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"},
1113 {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"},
1114 {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"},
1115 {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"},
1116 {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"},
1117 {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"},
1118 {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"},
1119 {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"},
1120 {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"},
1121 {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"},
1122 {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"},
1123 {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"},
1124 {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"},
1125 {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"},
1126 {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"},
1127 {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"},
1128 {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"},
1129 {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"},
1130 {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"},
1131 {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"},
1132 {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"},
1133 {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"},
1134 {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"},
1135 {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"},
1136 {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"},
1137 {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"},
1138 {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
1139 {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
1140 {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
1141 {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"},
1142 {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"},
1143 {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"},
1144 {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"},
1145 {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"},
1146 {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"},
1147 {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
1148 {153, 0, "DEV_ENCODER0_SYS_CLK", "Input clock"},
1149 {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
1150 {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
1151 {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
1152 {97, 0, "DEV_ESM0_CLK", "Input clock"},
1153 {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
1154 {106, 0, "DEV_GPIO1_MMR_CLK", "Input clock"},
1155 {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"},
1156 {108, 0, "DEV_GPIO3_MMR_CLK", "Input clock"},
1157 {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"},
1158 {110, 0, "DEV_GPIO5_MMR_CLK", "Input clock"},
1159 {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"},
1160 {112, 0, "DEV_GPIO7_MMR_CLK", "Input clock"},
1161 {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
1162 {115, 0, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
1163 {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"},
1164 {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
1165 {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1166 {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1167 {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1168 {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1169 {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
1170 {125, 0, "DEV_GPU0_GPU_0_GPU_PLL_CLK", "Input clock"},
1171 {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"},
1172 {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
1173 {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1174 {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1175 {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1176 {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1177 {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1178 {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1179 {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1180 {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1181 {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1182 {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1183 {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1184 {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1185 {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1186 {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1187 {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1188 {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1189 {187, 0, "DEV_I2C0_PISYS_CLK", "Input clock"},
1190 {187, 1, "DEV_I2C0_PISCL", "Input clock"},
1191 {187, 2, "DEV_I2C0_CLK", "Input clock"},
1192 {187, 3, "DEV_I2C0_PORSCL", "Output clock"},
1193 {188, 0, "DEV_I2C1_PISYS_CLK", "Input clock"},
1194 {188, 1, "DEV_I2C1_PISCL", "Input clock"},
1195 {188, 2, "DEV_I2C1_CLK", "Input clock"},
1196 {188, 3, "DEV_I2C1_PORSCL", "Output clock"},
1197 {189, 0, "DEV_I2C2_PISYS_CLK", "Input clock"},
1198 {189, 1, "DEV_I2C2_PISCL", "Input clock"},
1199 {189, 2, "DEV_I2C2_CLK", "Input clock"},
1200 {189, 3, "DEV_I2C2_PORSCL", "Output clock"},
1201 {190, 0, "DEV_I2C3_PISYS_CLK", "Input clock"},
1202 {190, 1, "DEV_I2C3_PISCL", "Input clock"},
1203 {190, 2, "DEV_I2C3_CLK", "Input clock"},
1204 {190, 3, "DEV_I2C3_PORSCL", "Output clock"},
1205 {191, 0, "DEV_I2C4_PISYS_CLK", "Input clock"},
1206 {191, 1, "DEV_I2C4_PISCL", "Input clock"},
1207 {191, 2, "DEV_I2C4_CLK", "Input clock"},
1208 {191, 3, "DEV_I2C4_PORSCL", "Output clock"},
1209 {192, 0, "DEV_I2C5_PISYS_CLK", "Input clock"},
1210 {192, 1, "DEV_I2C5_PISCL", "Input clock"},
1211 {192, 2, "DEV_I2C5_CLK", "Input clock"},
1212 {192, 3, "DEV_I2C5_PORSCL", "Output clock"},
1213 {193, 0, "DEV_I2C6_PISYS_CLK", "Input clock"},
1214 {193, 1, "DEV_I2C6_PISCL", "Input clock"},
1215 {193, 2, "DEV_I2C6_CLK", "Input clock"},
1216 {193, 3, "DEV_I2C6_PORSCL", "Output clock"},
1217 {116, 0, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"},
1218 {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"},
1219 {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"},
1220 {116, 3, "DEV_I3C0_I3C_SCL_DO", "Output clock"},
1221 {127, 0, "DEV_LED0_LED_CLK", "Input clock"},
1222 {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
1223 {128, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"},
1224 {130, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"},
1225 {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
1226 {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
1227 {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1228 {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1229 {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1230 {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1231 {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
1232 {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
1233 {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1234 {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1235 {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1236 {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1237 {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"},
1238 {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
1239 {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1240 {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1241 {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1242 {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1243 {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"},
1244 {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
1245 {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1246 {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1247 {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1248 {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1249 {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"},
1250 {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
1251 {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1252 {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1253 {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1254 {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1255 {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"},
1256 {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
1257 {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1258 {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1259 {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1260 {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1261 {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"},
1262 {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
1263 {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1264 {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1265 {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1266 {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1267 {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"},
1268 {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
1269 {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1270 {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1271 {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1272 {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1273 {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"},
1274 {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
1275 {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1276 {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1277 {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1278 {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1279 {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"},
1280 {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
1281 {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1282 {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1283 {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1284 {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1285 {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"},
1286 {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
1287 {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1288 {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1289 {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1290 {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1291 {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"},
1292 {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
1293 {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1294 {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1295 {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1296 {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1297 {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"},
1298 {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
1299 {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1300 {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1301 {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1302 {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1303 {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"},
1304 {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
1305 {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1306 {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1307 {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1308 {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1309 {174, 0, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
1310 {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
1311 {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1312 {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1313 {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1314 {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1315 {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1316 {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1317 {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1318 {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"},
1319 {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"},
1320 {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"},
1321 {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"},
1322 {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"},
1323 {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"},
1324 {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1325 {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1326 {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1327 {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1328 {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1329 {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1330 {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1331 {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1332 {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1333 {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1334 {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1335 {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1336 {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"},
1337 {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"},
1338 {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1339 {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1340 {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1341 {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1342 {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1343 {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1344 {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1345 {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1346 {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1347 {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1348 {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1349 {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1350 {175, 0, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
1351 {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
1352 {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1353 {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1354 {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1355 {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1356 {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1357 {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1358 {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1359 {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"},
1360 {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"},
1361 {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"},
1362 {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"},
1363 {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"},
1364 {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"},
1365 {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1366 {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1367 {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1368 {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1369 {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1370 {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1371 {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1372 {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1373 {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1374 {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1375 {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1376 {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1377 {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"},
1378 {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"},
1379 {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1380 {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1381 {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1382 {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1383 {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1384 {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1385 {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1386 {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1387 {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1388 {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1389 {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1390 {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1391 {184, 0, "DEV_MCASP10_VBUSP_CLK", "Input clock"},
1392 {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"},
1393 {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1394 {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1395 {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1396 {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1397 {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1398 {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1399 {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1400 {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT", "Output clock"},
1401 {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN", "Input clock"},
1402 {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT", "Output clock"},
1403 {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN", "Input clock"},
1404 {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT", "Output clock"},
1405 {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN", "Input muxed clock"},
1406 {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1407 {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1408 {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1409 {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1410 {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1411 {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1412 {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1413 {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1414 {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1415 {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1416 {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1417 {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1418 {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT", "Output clock"},
1419 {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN", "Input muxed clock"},
1420 {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1421 {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1422 {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1423 {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1424 {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1425 {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1426 {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1427 {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1428 {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1429 {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1430 {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1431 {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1432 {185, 0, "DEV_MCASP11_VBUSP_CLK", "Input clock"},
1433 {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"},
1434 {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1435 {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1436 {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1437 {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1438 {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1439 {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1440 {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1441 {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT", "Output clock"},
1442 {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN", "Input clock"},
1443 {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT", "Output clock"},
1444 {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN", "Input clock"},
1445 {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT", "Output clock"},
1446 {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN", "Input muxed clock"},
1447 {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1448 {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1449 {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1450 {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1451 {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1452 {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1453 {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1454 {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1455 {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1456 {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1457 {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1458 {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1459 {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT", "Output clock"},
1460 {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN", "Input muxed clock"},
1461 {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1462 {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1463 {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1464 {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1465 {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1466 {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1467 {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1468 {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1469 {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1470 {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1471 {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1472 {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1473 {176, 0, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
1474 {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
1475 {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1476 {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1477 {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1478 {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1479 {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1480 {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1481 {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1482 {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"},
1483 {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"},
1484 {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"},
1485 {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"},
1486 {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"},
1487 {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"},
1488 {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1489 {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1490 {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1491 {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1492 {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1493 {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1494 {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1495 {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1496 {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1497 {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1498 {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1499 {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1500 {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"},
1501 {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"},
1502 {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1503 {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1504 {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1505 {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1506 {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1507 {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1508 {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1509 {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1510 {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1511 {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1512 {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1513 {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1514 {177, 0, "DEV_MCASP3_VBUSP_CLK", "Input clock"},
1515 {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"},
1516 {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1517 {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1518 {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1519 {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1520 {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1521 {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1522 {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1523 {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT", "Output clock"},
1524 {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN", "Input clock"},
1525 {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT", "Output clock"},
1526 {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN", "Input clock"},
1527 {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT", "Output clock"},
1528 {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN", "Input muxed clock"},
1529 {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1530 {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1531 {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1532 {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1533 {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1534 {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1535 {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1536 {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1537 {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1538 {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1539 {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1540 {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1541 {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT", "Output clock"},
1542 {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN", "Input muxed clock"},
1543 {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1544 {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1545 {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1546 {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1547 {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1548 {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1549 {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1550 {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1551 {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1552 {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1553 {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1554 {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1555 {178, 0, "DEV_MCASP4_VBUSP_CLK", "Input clock"},
1556 {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"},
1557 {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1558 {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1559 {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1560 {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1561 {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1562 {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1563 {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1564 {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT", "Output clock"},
1565 {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN", "Input clock"},
1566 {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT", "Output clock"},
1567 {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN", "Input clock"},
1568 {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT", "Output clock"},
1569 {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN", "Input muxed clock"},
1570 {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1571 {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1572 {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1573 {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1574 {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1575 {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1576 {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1577 {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1578 {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1579 {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1580 {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1581 {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1582 {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT", "Output clock"},
1583 {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN", "Input muxed clock"},
1584 {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1585 {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1586 {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1587 {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1588 {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1589 {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1590 {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1591 {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1592 {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1593 {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1594 {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1595 {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1596 {179, 0, "DEV_MCASP5_VBUSP_CLK", "Input clock"},
1597 {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"},
1598 {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1599 {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1600 {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1601 {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1602 {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1603 {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1604 {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1605 {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT", "Output clock"},
1606 {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN", "Input clock"},
1607 {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT", "Output clock"},
1608 {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN", "Input clock"},
1609 {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT", "Output clock"},
1610 {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN", "Input muxed clock"},
1611 {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1612 {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1613 {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1614 {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1615 {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1616 {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1617 {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1618 {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1619 {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1620 {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1621 {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1622 {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1623 {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT", "Output clock"},
1624 {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN", "Input muxed clock"},
1625 {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1626 {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1627 {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1628 {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1629 {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1630 {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1631 {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1632 {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1633 {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1634 {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1635 {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1636 {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1637 {180, 0, "DEV_MCASP6_VBUSP_CLK", "Input clock"},
1638 {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"},
1639 {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1640 {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1641 {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1642 {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1643 {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1644 {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1645 {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1646 {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT", "Output clock"},
1647 {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN", "Input clock"},
1648 {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT", "Output clock"},
1649 {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN", "Input clock"},
1650 {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT", "Output clock"},
1651 {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN", "Input muxed clock"},
1652 {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1653 {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1654 {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1655 {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1656 {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1657 {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1658 {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1659 {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1660 {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1661 {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1662 {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1663 {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1664 {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT", "Output clock"},
1665 {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN", "Input muxed clock"},
1666 {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1667 {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1668 {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1669 {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1670 {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1671 {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1672 {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1673 {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1674 {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1675 {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1676 {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1677 {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1678 {181, 0, "DEV_MCASP7_VBUSP_CLK", "Input clock"},
1679 {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"},
1680 {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1681 {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1682 {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1683 {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1684 {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1685 {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1686 {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1687 {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT", "Output clock"},
1688 {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN", "Input clock"},
1689 {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT", "Output clock"},
1690 {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN", "Input clock"},
1691 {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT", "Output clock"},
1692 {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN", "Input muxed clock"},
1693 {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1694 {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1695 {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1696 {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1697 {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1698 {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1699 {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1700 {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1701 {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1702 {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1703 {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1704 {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1705 {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT", "Output clock"},
1706 {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN", "Input muxed clock"},
1707 {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1708 {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1709 {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1710 {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1711 {181, 34, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1712 {181, 35, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1713 {181, 36, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1714 {181, 37, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1715 {181, 38, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1716 {181, 39, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1717 {181, 40, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1718 {181, 41, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1719 {182, 0, "DEV_MCASP8_VBUSP_CLK", "Input clock"},
1720 {182, 1, "DEV_MCASP8_AUX_CLK", "Input muxed clock"},
1721 {182, 2, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1722 {182, 3, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1723 {182, 4, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1724 {182, 6, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1725 {182, 7, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1726 {182, 8, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1727 {182, 9, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1728 {182, 10, "DEV_MCASP8_MCASP_ACLKX_POUT", "Output clock"},
1729 {182, 11, "DEV_MCASP8_MCASP_ACLKX_PIN", "Input clock"},
1730 {182, 12, "DEV_MCASP8_MCASP_ACLKR_POUT", "Output clock"},
1731 {182, 13, "DEV_MCASP8_MCASP_ACLKR_PIN", "Input clock"},
1732 {182, 14, "DEV_MCASP8_MCASP_AHCLKX_POUT", "Output clock"},
1733 {182, 15, "DEV_MCASP8_MCASP_AHCLKX_PIN", "Input muxed clock"},
1734 {182, 16, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1735 {182, 17, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1736 {182, 18, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1737 {182, 19, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1738 {182, 20, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1739 {182, 21, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1740 {182, 22, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1741 {182, 23, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1742 {182, 24, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1743 {182, 25, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1744 {182, 26, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1745 {182, 27, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1746 {182, 28, "DEV_MCASP8_MCASP_AHCLKR_POUT", "Output clock"},
1747 {182, 29, "DEV_MCASP8_MCASP_AHCLKR_PIN", "Input muxed clock"},
1748 {182, 30, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1749 {182, 31, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1750 {182, 32, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1751 {182, 33, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1752 {182, 34, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1753 {182, 35, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1754 {182, 36, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1755 {182, 37, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1756 {182, 38, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1757 {182, 39, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1758 {182, 40, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1759 {182, 41, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1760 {183, 0, "DEV_MCASP9_VBUSP_CLK", "Input clock"},
1761 {183, 1, "DEV_MCASP9_AUX_CLK", "Input muxed clock"},
1762 {183, 2, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1763 {183, 3, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1764 {183, 4, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1765 {183, 6, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1766 {183, 7, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1767 {183, 8, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1768 {183, 9, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1769 {183, 10, "DEV_MCASP9_MCASP_ACLKX_POUT", "Output clock"},
1770 {183, 11, "DEV_MCASP9_MCASP_ACLKX_PIN", "Input clock"},
1771 {183, 12, "DEV_MCASP9_MCASP_ACLKR_POUT", "Output clock"},
1772 {183, 13, "DEV_MCASP9_MCASP_ACLKR_PIN", "Input clock"},
1773 {183, 14, "DEV_MCASP9_MCASP_AHCLKX_POUT", "Output clock"},
1774 {183, 15, "DEV_MCASP9_MCASP_AHCLKX_PIN", "Input muxed clock"},
1775 {183, 16, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1776 {183, 17, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1777 {183, 18, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1778 {183, 19, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1779 {183, 20, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1780 {183, 21, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1781 {183, 22, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1782 {183, 23, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1783 {183, 24, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1784 {183, 25, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1785 {183, 26, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1786 {183, 27, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1787 {183, 28, "DEV_MCASP9_MCASP_AHCLKR_POUT", "Output clock"},
1788 {183, 29, "DEV_MCASP9_MCASP_AHCLKR_PIN", "Input muxed clock"},
1789 {183, 30, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1790 {183, 31, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1791 {183, 32, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1792 {183, 33, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1793 {183, 34, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1794 {183, 35, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1795 {183, 36, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1796 {183, 37, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1797 {183, 38, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1798 {183, 39, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1799 {183, 40, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1800 {183, 41, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1801 {266, 0, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
1802 {266, 1, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
1803 {266, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
1804 {267, 0, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
1805 {267, 1, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
1806 {267, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
1807 {268, 0, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
1808 {268, 1, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
1809 {268, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
1810 {269, 0, "DEV_MCSPI3_VBUSP_CLK", "Input clock"},
1811 {269, 1, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
1812 {269, 2, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
1813 {269, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
1814 {269, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
1815 {270, 0, "DEV_MCSPI4_VBUSP_CLK", "Input clock"},
1816 {270, 1, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
1817 {270, 2, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"},
1818 {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
1819 {271, 0, "DEV_MCSPI5_VBUSP_CLK", "Input clock"},
1820 {271, 1, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"},
1821 {271, 2, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"},
1822 {272, 0, "DEV_MCSPI6_VBUSP_CLK", "Input clock"},
1823 {272, 1, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"},
1824 {272, 2, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"},
1825 {273, 0, "DEV_MCSPI7_VBUSP_CLK", "Input clock"},
1826 {273, 1, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"},
1827 {273, 2, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"},
1828 {0, 0, "DEV_MCU_ADC12_16FFC0_SYS_CLK", "Input clock"},
1829 {0, 1, "DEV_MCU_ADC12_16FFC0_ADC_CLK", "Input muxed clock"},
1830 {0, 2, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1831 {0, 3, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1832 {0, 4, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1833 {0, 5, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1834 {0, 6, "DEV_MCU_ADC12_16FFC0_VBUS_CLK", "Input clock"},
1835 {1, 0, "DEV_MCU_ADC12_16FFC1_SYS_CLK", "Input clock"},
1836 {1, 1, "DEV_MCU_ADC12_16FFC1_ADC_CLK", "Input muxed clock"},
1837 {1, 2, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1838 {1, 3, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1839 {1, 4, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1840 {1, 5, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1841 {1, 6, "DEV_MCU_ADC12_16FFC1_VBUS_CLK", "Input clock"},
1842 {18, 0, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"},
1843 {18, 1, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
1844 {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
1845 {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1846 {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1847 {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1848 {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1849 {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1850 {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1851 {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1852 {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1853 {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1854 {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1855 {18, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1856 {18, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1857 {18, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1858 {18, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1859 {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1860 {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1861 {18, 19, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"},
1862 {18, 20, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
1863 {18, 21, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
1864 {18, 22, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"},
1865 {18, 23, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
1866 {18, 24, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"},
1867 {18, 25, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"},
1868 {18, 26, "DEV_MCU_CPSW0_RGMII1_TXC_I", "Input clock"},
1869 {18, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"},
1870 {18, 28, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"},
1871 {18, 29, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"},
1872 {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"},
1873 {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
1874 {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
1875 {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
1876 {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
1877 {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
1878 {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
1879 {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
1880 {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
1881 {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
1882 {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
1883 {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
1884 {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
1885 {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
1886 {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"},
1887 {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"},
1888 {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
1889 {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
1890 {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
1891 {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"},
1892 {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
1893 {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
1894 {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
1895 {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"},
1896 {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
1897 {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
1898 {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"},
1899 {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"},
1900 {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"},
1901 {46, 2, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
1902 {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
1903 {46, 4, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"},
1904 {46, 5, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
1905 {46, 6, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
1906 {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
1907 {46, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"},
1908 {46, 9, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
1909 {46, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"},
1910 {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"},
1911 {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"},
1912 {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"},
1913 {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"},
1914 {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"},
1915 {102, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"},
1916 {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"},
1917 {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"},
1918 {102, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"},
1919 {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
1920 {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
1921 {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
1922 {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
1923 {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
1924 {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
1925 {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
1926 {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
1927 {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
1928 {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
1929 {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"},
1930 {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
1931 {104, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
1932 {104, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"},
1933 {104, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"},
1934 {104, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
1935 {104, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
1936 {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"},
1937 {104, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"},
1938 {104, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"},
1939 {194, 0, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
1940 {194, 1, "DEV_MCU_I2C0_PISCL", "Input clock"},
1941 {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"},
1942 {194, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"},
1943 {195, 0, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"},
1944 {195, 1, "DEV_MCU_I2C1_PISCL", "Input clock"},
1945 {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"},
1946 {195, 3, "DEV_MCU_I2C1_PORSCL", "Output clock"},
1947 {117, 0, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"},
1948 {117, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"},
1949 {117, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"},
1950 {117, 3, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"},
1951 {118, 0, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"},
1952 {118, 1, "DEV_MCU_I3C1_I3C_SCL_DI", "Input clock"},
1953 {118, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"},
1954 {118, 3, "DEV_MCU_I3C1_I3C_SCL_DO", "Output clock"},
1955 {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
1956 {172, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
1957 {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1958 {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1959 {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1960 {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1961 {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
1962 {173, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
1963 {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1964 {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1965 {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1966 {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1967 {274, 0, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
1968 {274, 1, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
1969 {274, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
1970 {275, 0, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
1971 {275, 1, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
1972 {275, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
1973 {275, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
1974 {275, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
1975 {276, 0, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"},
1976 {276, 1, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"},
1977 {276, 2, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"},
1978 {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
1979 {237, 0, "DEV_MCU_NAVSS0_INTR_0_INTR_CLK", "Input clock"},
1980 {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"},
1981 {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"},
1982 {234, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"},
1983 {235, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"},
1984 {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
1985 {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"},
1986 {233, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
1987 {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"},
1988 {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
1989 {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
1990 {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
1991 {250, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
1992 {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"},
1993 {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
1994 {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
1995 {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
1996 {251, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
1997 {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
1998 {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
1999 {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
2000 {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
2001 {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
2002 {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
2003 {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"},
2004 {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"},
2005 {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
2006 {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
2007 {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
2008 {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
2009 {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"},
2010 {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"},
2011 {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"},
2012 {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
2013 {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
2014 {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2015 {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2016 {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2017 {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2018 {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2019 {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2020 {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2021 {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
2022 {35, 10, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"},
2023 {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
2024 {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
2025 {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
2026 {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
2027 {322, 0, "DEV_MCU_TIMER1_CLKSEL_VD_CLK", "Input muxed clock"},
2028 {322, 1, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2029 {322, 2, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2030 {322, 3, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2031 {322, 4, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2032 {322, 5, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2033 {322, 6, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2034 {322, 7, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2035 {322, 8, "DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK"},
2036 {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
2037 {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
2038 {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2039 {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2040 {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2041 {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2042 {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2043 {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2044 {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2045 {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
2046 {72, 10, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"},
2047 {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
2048 {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
2049 {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
2050 {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
2051 {323, 0, "DEV_MCU_TIMER3_CLKSEL_VD_CLK", "Input muxed clock"},
2052 {323, 1, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2053 {323, 2, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2054 {323, 3, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2055 {323, 4, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2056 {323, 5, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2057 {323, 6, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2058 {323, 7, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2059 {323, 8, "DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK"},
2060 {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"},
2061 {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
2062 {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2063 {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2064 {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2065 {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2066 {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2067 {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2068 {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2069 {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2070 {74, 10, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"},
2071 {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"},
2072 {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
2073 {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
2074 {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
2075 {324, 0, "DEV_MCU_TIMER5_CLKSEL_VD_CLK", "Input muxed clock"},
2076 {324, 1, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2077 {324, 2, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2078 {324, 3, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2079 {324, 4, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2080 {324, 5, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2081 {324, 6, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2082 {324, 7, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2083 {324, 8, "DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK"},
2084 {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"},
2085 {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
2086 {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2087 {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2088 {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2089 {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2090 {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2091 {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2092 {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2093 {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2094 {76, 10, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"},
2095 {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"},
2096 {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
2097 {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
2098 {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
2099 {325, 0, "DEV_MCU_TIMER7_CLKSEL_VD_CLK", "Input muxed clock"},
2100 {325, 1, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2101 {325, 2, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2102 {325, 3, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2103 {325, 4, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2104 {325, 5, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2105 {325, 6, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2106 {325, 7, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2107 {325, 8, "DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK"},
2108 {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"},
2109 {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
2110 {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2111 {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2112 {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2113 {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2114 {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2115 {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2116 {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2117 {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2118 {78, 10, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"},
2119 {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"},
2120 {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
2121 {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
2122 {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
2123 {326, 0, "DEV_MCU_TIMER9_CLKSEL_VD_CLK", "Input muxed clock"},
2124 {326, 1, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2125 {326, 2, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2126 {326, 3, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2127 {326, 4, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2128 {326, 5, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2129 {326, 6, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2130 {326, 7, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2131 {326, 8, "DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK"},
2132 {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"},
2133 {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
2134 {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
2135 {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
2136 {186, 0, "DEV_MLB0_MLBSS_MLB_CLK", "Input clock"},
2137 {186, 1, "DEV_MLB0_MLBSS_SCLK_CLK", "Input clock"},
2138 {186, 2, "DEV_MLB0_MLBSS_HCLK_CLK", "Input clock"},
2139 {186, 3, "DEV_MLB0_MLBSS_PCLK_CLK", "Input clock"},
2140 {186, 4, "DEV_MLB0_MLBSS_AMLB_CLK", "Input clock"},
2141 {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"},
2142 {91, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
2143 {91, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2144 {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2145 {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2146 {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2147 {91, 6, "DEV_MMCSD0_EMMCSS_IO_CLK", "Output clock"},
2148 {92, 0, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
2149 {92, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2150 {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2151 {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2152 {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2153 {92, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
2154 {92, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"},
2155 {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"},
2156 {93, 0, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"},
2157 {93, 1, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2158 {93, 2, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2159 {93, 3, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2160 {93, 4, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2161 {93, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"},
2162 {93, 6, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input clock"},
2163 {93, 7, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"},
2164 {199, 0, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"},
2165 {199, 1, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"},
2166 {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"},
2167 {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"},
2168 {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2169 {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2170 {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2171 {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2172 {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2173 {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2174 {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2175 {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2176 {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2177 {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2178 {201, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2179 {201, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2180 {201, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2181 {201, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2182 {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2183 {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2184 {201, 18, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"},
2185 {201, 19, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"},
2186 {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"},
2187 {206, 1, "DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK", "Input clock"},
2188 {206, 2, "DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK", "Input clock"},
2189 {206, 3, "DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK", "Input clock"},
2190 {206, 4, "DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK", "Input clock"},
2191 {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"},
2192 {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"},
2193 {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"},
2194 {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"},
2195 {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"},
2196 {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"},
2197 {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"},
2198 {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"},
2199 {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"},
2200 {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"},
2201 {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"},
2202 {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"},
2203 {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"},
2204 {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"},
2205 {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"},
2206 {207, 0, "DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK", "Input clock"},
2207 {208, 0, "DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK", "Input clock"},
2208 {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"},
2209 {339, 0, "DEV_NAVSS0_PVU_0_CLK_CLK", "Input clock"},
2210 {340, 0, "DEV_NAVSS0_PVU_1_CLK_CLK", "Input clock"},
2211 {341, 0, "DEV_NAVSS0_PVU_2_CLK_CLK", "Input clock"},
2212 {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"},
2213 {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"},
2214 {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"},
2215 {229, 0, "DEV_NAVSS0_TCU_0_CLK_CLK", "Input clock"},
2216 {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"},
2217 {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"},
2218 {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"},
2219 {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"},
2220 {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
2221 {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"},
2222 {209, 0, "DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK", "Input clock"},
2223 {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"},
2224 {239, 0, "DEV_PCIE0_PCIE_LANE1_TXMCLK", "Input clock"},
2225 {239, 1, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"},
2226 {239, 2, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"},
2227 {239, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2228 {239, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2229 {239, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2230 {239, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2231 {239, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2232 {239, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2233 {239, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2234 {239, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2235 {239, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2236 {239, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2237 {239, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2238 {239, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2239 {239, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2240 {239, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2241 {239, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2242 {239, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2243 {239, 19, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2244 {239, 20, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"},
2245 {239, 21, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"},
2246 {239, 22, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"},
2247 {239, 23, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"},
2248 {239, 24, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"},
2249 {239, 25, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"},
2250 {239, 26, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"},
2251 {239, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"},
2252 {239, 28, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"},
2253 {239, 29, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"},
2254 {239, 30, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"},
2255 {240, 0, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"},
2256 {240, 1, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"},
2257 {240, 2, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"},
2258 {240, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2259 {240, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2260 {240, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2261 {240, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2262 {240, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2263 {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2264 {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2265 {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2266 {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2267 {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2268 {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2269 {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2270 {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2271 {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2272 {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2273 {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2274 {240, 19, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2275 {240, 20, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"},
2276 {240, 21, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"},
2277 {240, 22, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"},
2278 {240, 23, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"},
2279 {240, 24, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"},
2280 {240, 25, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"},
2281 {240, 26, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"},
2282 {240, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"},
2283 {240, 28, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"},
2284 {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"},
2285 {240, 30, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"},
2286 {241, 0, "DEV_PCIE2_PCIE_LANE1_TXMCLK", "Input clock"},
2287 {241, 1, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"},
2288 {241, 2, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"},
2289 {241, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2290 {241, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2291 {241, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2292 {241, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2293 {241, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2294 {241, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2295 {241, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2296 {241, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2297 {241, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2298 {241, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2299 {241, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2300 {241, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2301 {241, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2302 {241, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2303 {241, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2304 {241, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2305 {241, 19, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2306 {241, 20, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"},
2307 {241, 21, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"},
2308 {241, 22, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"},
2309 {241, 23, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"},
2310 {241, 24, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"},
2311 {241, 25, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"},
2312 {241, 26, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"},
2313 {241, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"},
2314 {241, 28, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"},
2315 {241, 29, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"},
2316 {241, 30, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"},
2317 {242, 0, "DEV_PCIE3_PCIE_LANE1_TXMCLK", "Input clock"},
2318 {242, 1, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"},
2319 {242, 2, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"},
2320 {242, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2321 {242, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2322 {242, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2323 {242, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2324 {242, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2325 {242, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2326 {242, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2327 {242, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2328 {242, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2329 {242, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2330 {242, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2331 {242, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2332 {242, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2333 {242, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2334 {242, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2335 {242, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2336 {242, 19, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2337 {242, 20, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"},
2338 {242, 21, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"},
2339 {242, 22, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"},
2340 {242, 23, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"},
2341 {242, 24, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"},
2342 {242, 25, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"},
2343 {242, 26, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"},
2344 {242, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"},
2345 {242, 28, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"},
2346 {242, 29, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"},
2347 {242, 30, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"},
2348 {119, 0, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I", "Input clock"},
2349 {119, 1, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"},
2350 {119, 2, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I", "Input clock"},
2351 {119, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"},
2352 {119, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2353 {119, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2354 {119, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2355 {119, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2356 {119, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2357 {119, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2358 {119, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2359 {119, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2360 {119, 12, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2361 {119, 13, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2362 {119, 14, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2363 {119, 15, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2364 {119, 16, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2365 {119, 17, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2366 {119, 18, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2367 {119, 19, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2368 {119, 20, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"},
2369 {119, 21, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I", "Input clock"},
2370 {119, 22, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"},
2371 {119, 23, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I", "Input clock"},
2372 {119, 24, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"},
2373 {119, 25, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
2374 {119, 26, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
2375 {119, 27, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"},
2376 {119, 28, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"},
2377 {119, 29, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O", "Output clock"},
2378 {119, 30, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O", "Output clock"},
2379 {119, 31, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O", "Output clock"},
2380 {120, 0, "DEV_PRU_ICSSG1_SERDES0_RXCLK", "Input muxed clock"},
2381 {120, 1, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
2382 {120, 2, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
2383 {120, 3, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I", "Input clock"},
2384 {120, 4, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"},
2385 {120, 5, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I", "Input clock"},
2386 {120, 6, "DEV_PRU_ICSSG1_SERDES0_RXFCLK", "Input muxed clock"},
2387 {120, 7, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
2388 {120, 8, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
2389 {120, 9, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"},
2390 {120, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2391 {120, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2392 {120, 12, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2393 {120, 13, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2394 {120, 14, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2395 {120, 15, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2396 {120, 16, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2397 {120, 17, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2398 {120, 18, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2399 {120, 19, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2400 {120, 20, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2401 {120, 21, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2402 {120, 22, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2403 {120, 23, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2404 {120, 24, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2405 {120, 25, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2406 {120, 26, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"},
2407 {120, 27, "DEV_PRU_ICSSG1_SERDES0_TXMCLK", "Input muxed clock"},
2408 {120, 28, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
2409 {120, 29, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
2410 {120, 30, "DEV_PRU_ICSSG1_SERDES0_REFCLK", "Input muxed clock"},
2411 {120, 31, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
2412 {120, 32, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
2413 {120, 33, "DEV_PRU_ICSSG1_SERDES1_RXFCLK", "Input muxed clock"},
2414 {120, 34, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
2415 {120, 35, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
2416 {120, 36, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I", "Input clock"},
2417 {120, 37, "DEV_PRU_ICSSG1_SERDES1_RXCLK", "Input muxed clock"},
2418 {120, 38, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
2419 {120, 39, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
2420 {120, 40, "DEV_PRU_ICSSG1_SERDES1_TXFCLK", "Input muxed clock"},
2421 {120, 41, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
2422 {120, 42, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
2423 {120, 43, "DEV_PRU_ICSSG1_SERDES1_TXMCLK", "Input muxed clock"},
2424 {120, 44, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
2425 {120, 45, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
2426 {120, 46, "DEV_PRU_ICSSG1_SERDES0_TXFCLK", "Input muxed clock"},
2427 {120, 47, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
2428 {120, 48, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
2429 {120, 49, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"},
2430 {120, 50, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I", "Input clock"},
2431 {120, 51, "DEV_PRU_ICSSG1_SERDES1_REFCLK", "Input muxed clock"},
2432 {120, 52, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
2433 {120, 53, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
2434 {120, 54, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"},
2435 {120, 55, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
2436 {120, 56, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
2437 {120, 57, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"},
2438 {120, 58, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"},
2439 {120, 59, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O", "Output clock"},
2440 {120, 60, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O", "Output clock"},
2441 {120, 61, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O", "Output clock"},
2442 {120, 62, "DEV_PRU_ICSSG1_SERDES0_TXCLK", "Output clock"},
2443 {120, 63, "DEV_PRU_ICSSG1_SERDES1_TXCLK", "Output clock"},
2444 {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"},
2445 {133, 1, "DEV_PSC0_CLK", "Input clock"},
2446 {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"},
2447 {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
2448 {245, 2, "DEV_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
2449 {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"},
2450 {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
2451 {246, 2, "DEV_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
2452 {134, 0, "DEV_R5FSS0_INTROUTER0_INTR_CLK", "Input clock"},
2453 {247, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"},
2454 {247, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"},
2455 {247, 2, "DEV_R5FSS1_CORE0_INTERFACE_PHASE", "Input clock"},
2456 {248, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"},
2457 {248, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"},
2458 {248, 2, "DEV_R5FSS1_CORE1_INTERFACE_PHASE", "Input clock"},
2459 {135, 0, "DEV_R5FSS1_INTROUTER0_INTR_CLK", "Input clock"},
2460 {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"},
2461 {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
2462 {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2463 {252, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2464 {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2465 {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2466 {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2467 {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2468 {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2469 {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2470 {253, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"},
2471 {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
2472 {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2473 {253, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2474 {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2475 {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2476 {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2477 {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2478 {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2479 {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2480 {257, 0, "DEV_RTI15_VBUSP_CLK", "Input clock"},
2481 {257, 1, "DEV_RTI15_RTI_CLK", "Input muxed clock"},
2482 {257, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2483 {257, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2484 {257, 4, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2485 {257, 5, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2486 {257, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2487 {257, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2488 {257, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2489 {257, 9, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2490 {256, 0, "DEV_RTI16_VBUSP_CLK", "Input clock"},
2491 {256, 1, "DEV_RTI16_RTI_CLK", "Input muxed clock"},
2492 {256, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2493 {256, 3, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2494 {256, 4, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2495 {256, 5, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2496 {256, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2497 {256, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2498 {256, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2499 {256, 9, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2500 {254, 0, "DEV_RTI24_VBUSP_CLK", "Input clock"},
2501 {254, 1, "DEV_RTI24_RTI_CLK", "Input muxed clock"},
2502 {254, 2, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2503 {254, 3, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2504 {254, 4, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2505 {254, 5, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2506 {254, 6, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2507 {254, 7, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2508 {254, 8, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2509 {254, 9, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2510 {255, 0, "DEV_RTI25_VBUSP_CLK", "Input clock"},
2511 {255, 1, "DEV_RTI25_RTI_CLK", "Input muxed clock"},
2512 {255, 2, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2513 {255, 3, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2514 {255, 4, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2515 {255, 5, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2516 {255, 6, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2517 {255, 7, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2518 {255, 8, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2519 {255, 9, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2520 {258, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"},
2521 {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"},
2522 {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2523 {258, 3, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2524 {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2525 {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2526 {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2527 {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2528 {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2529 {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2530 {259, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"},
2531 {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"},
2532 {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2533 {259, 3, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2534 {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2535 {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2536 {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2537 {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2538 {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2539 {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2540 {260, 0, "DEV_RTI30_VBUSP_CLK", "Input clock"},
2541 {260, 1, "DEV_RTI30_RTI_CLK", "Input muxed clock"},
2542 {260, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2543 {260, 3, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2544 {260, 4, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2545 {260, 5, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2546 {260, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2547 {260, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2548 {260, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2549 {260, 9, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2550 {261, 0, "DEV_RTI31_VBUSP_CLK", "Input clock"},
2551 {261, 1, "DEV_RTI31_RTI_CLK", "Input muxed clock"},
2552 {261, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2553 {261, 3, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2554 {261, 4, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2555 {261, 5, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2556 {261, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2557 {261, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2558 {261, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2559 {261, 9, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2560 {264, 0, "DEV_SA2_UL0_X2_CLK", "Input clock"},
2561 {264, 1, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"},
2562 {264, 2, "DEV_SA2_UL0_X1_CLK", "Input clock"},
2563 {297, 0, "DEV_SERDES_10G0_IP1_LN3_TXCLK", "Input clock"},
2564 {297, 1, "DEV_SERDES_10G0_CLK", "Input clock"},
2565 {297, 2, "DEV_SERDES_10G0_IP3_LN2_TXCLK", "Input clock"},
2566 {297, 3, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input clock"},
2567 {297, 4, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"},
2568 {297, 5, "DEV_SERDES_10G0_IP3_LN1_TXCLK", "Input clock"},
2569 {297, 6, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"},
2570 {297, 7, "DEV_SERDES_10G0_IP3_LN0_TXCLK", "Input clock"},
2571 {297, 8, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"},
2572 {297, 9, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"},
2573 {297, 10, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2574 {297, 11, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2575 {297, 12, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2576 {297, 13, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2577 {297, 14, "DEV_SERDES_10G0_IP1_LN1_REFCLK", "Output clock"},
2578 {297, 15, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"},
2579 {297, 16, "DEV_SERDES_10G0_IP3_LN1_TXFCLK", "Output clock"},
2580 {297, 17, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"},
2581 {297, 18, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"},
2582 {297, 19, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"},
2583 {297, 20, "DEV_SERDES_10G0_IP3_LN1_TXMCLK", "Output clock"},
2584 {297, 21, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"},
2585 {297, 22, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"},
2586 {297, 23, "DEV_SERDES_10G0_IP3_LN2_RXCLK", "Output clock"},
2587 {297, 24, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"},
2588 {297, 25, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"},
2589 {297, 26, "DEV_SERDES_10G0_IP3_LN1_RXFCLK", "Output clock"},
2590 {297, 27, "DEV_SERDES_10G0_IP3_LN0_RXFCLK", "Output clock"},
2591 {297, 28, "DEV_SERDES_10G0_IP1_LN1_TXMCLK", "Output clock"},
2592 {297, 29, "DEV_SERDES_10G0_IP1_LN1_RXFCLK", "Output clock"},
2593 {297, 30, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"},
2594 {297, 31, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"},
2595 {297, 32, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"},
2596 {297, 33, "DEV_SERDES_10G0_IP3_LN1_REFCLK", "Output clock"},
2597 {297, 34, "DEV_SERDES_10G0_IP3_LN0_REFCLK", "Output clock"},
2598 {297, 35, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"},
2599 {297, 36, "DEV_SERDES_10G0_IP3_LN0_RXCLK", "Output clock"},
2600 {297, 37, "DEV_SERDES_10G0_IP3_LN2_REFCLK", "Output clock"},
2601 {297, 38, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"},
2602 {297, 39, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"},
2603 {297, 40, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"},
2604 {297, 41, "DEV_SERDES_10G0_IP1_LN1_TXFCLK", "Output clock"},
2605 {297, 42, "DEV_SERDES_10G0_IP3_LN0_TXFCLK", "Output clock"},
2606 {297, 43, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"},
2607 {297, 44, "DEV_SERDES_10G0_IP3_LN1_RXCLK", "Output clock"},
2608 {297, 45, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"},
2609 {297, 46, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"},
2610 {297, 47, "DEV_SERDES_10G0_IP3_LN2_RXFCLK", "Output clock"},
2611 {297, 48, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"},
2612 {297, 49, "DEV_SERDES_10G0_IP3_LN2_TXMCLK", "Output clock"},
2613 {297, 50, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"},
2614 {297, 51, "DEV_SERDES_10G0_IP3_LN2_TXFCLK", "Output clock"},
2615 {297, 52, "DEV_SERDES_10G0_IP3_LN0_TXMCLK", "Output clock"},
2616 {297, 53, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"},
2617 {297, 54, "DEV_SERDES_10G0_IP1_LN1_RXCLK", "Output clock"},
2618 {292, 0, "DEV_SERDES_16G0_CORE_REF1_CLK", "Input muxed clock"},
2619 {292, 1, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2620 {292, 2, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2621 {292, 3, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2622 {292, 4, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2623 {292, 5, "DEV_SERDES_16G0_CLK", "Input clock"},
2624 {292, 6, "DEV_SERDES_16G0_IP1_LN0_TXCLK", "Input clock"},
2625 {292, 7, "DEV_SERDES_16G0_IP2_LN1_TXCLK", "Input clock"},
2626 {292, 8, "DEV_SERDES_16G0_IP3_LN1_TXCLK", "Input clock"},
2627 {292, 9, "DEV_SERDES_16G0_IP2_LN0_TXCLK", "Input clock"},
2628 {292, 10, "DEV_SERDES_16G0_IP1_LN1_TXCLK", "Input clock"},
2629 {292, 11, "DEV_SERDES_16G0_CORE_REF_CLK", "Input muxed clock"},
2630 {292, 12, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2631 {292, 13, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2632 {292, 14, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2633 {292, 15, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2634 {292, 16, "DEV_SERDES_16G0_IP2_LN0_TXFCLK", "Output clock"},
2635 {292, 17, "DEV_SERDES_16G0_IP1_LN1_REFCLK", "Output clock"},
2636 {292, 18, "DEV_SERDES_16G0_IP3_LN1_TXMCLK", "Output clock"},
2637 {292, 19, "DEV_SERDES_16G0_IP3_LN1_TXFCLK", "Output clock"},
2638 {292, 20, "DEV_SERDES_16G0_IP1_LN0_RXFCLK", "Output clock"},
2639 {292, 21, "DEV_SERDES_16G0_IP2_LN1_REFCLK", "Output clock"},
2640 {292, 22, "DEV_SERDES_16G0_IP2_LN1_TXFCLK", "Output clock"},
2641 {292, 23, "DEV_SERDES_16G0_REF_DER_OUT_CLK", "Output clock"},
2642 {292, 24, "DEV_SERDES_16G0_IP1_LN0_TXFCLK", "Output clock"},
2643 {292, 25, "DEV_SERDES_16G0_IP3_LN1_RXFCLK", "Output clock"},
2644 {292, 26, "DEV_SERDES_16G0_IP1_LN1_TXMCLK", "Output clock"},
2645 {292, 27, "DEV_SERDES_16G0_IP1_LN1_RXFCLK", "Output clock"},
2646 {292, 28, "DEV_SERDES_16G0_IP3_LN1_RXCLK", "Output clock"},
2647 {292, 29, "DEV_SERDES_16G0_IP3_LN1_REFCLK", "Output clock"},
2648 {292, 30, "DEV_SERDES_16G0_IP2_LN1_RXCLK", "Output clock"},
2649 {292, 31, "DEV_SERDES_16G0_IP2_LN0_RXFCLK", "Output clock"},
2650 {292, 32, "DEV_SERDES_16G0_IP1_LN0_RXCLK", "Output clock"},
2651 {292, 33, "DEV_SERDES_16G0_REF_OUT_CLK", "Output clock"},
2652 {292, 34, "DEV_SERDES_16G0_REF1_OUT_CLK", "Output clock"},
2653 {292, 35, "DEV_SERDES_16G0_IP1_LN0_REFCLK", "Output clock"},
2654 {292, 36, "DEV_SERDES_16G0_IP1_LN0_TXMCLK", "Output clock"},
2655 {292, 37, "DEV_SERDES_16G0_IP2_LN1_RXFCLK", "Output clock"},
2656 {292, 38, "DEV_SERDES_16G0_IP2_LN1_TXMCLK", "Output clock"},
2657 {292, 39, "DEV_SERDES_16G0_IP2_LN0_REFCLK", "Output clock"},
2658 {292, 40, "DEV_SERDES_16G0_IP2_LN0_TXMCLK", "Output clock"},
2659 {292, 41, "DEV_SERDES_16G0_IP1_LN1_TXFCLK", "Output clock"},
2660 {292, 42, "DEV_SERDES_16G0_IP2_LN0_RXCLK", "Output clock"},
2661 {292, 43, "DEV_SERDES_16G0_IP1_LN1_RXCLK", "Output clock"},
2662 {292, 49, "DEV_SERDES_16G0_CMN_REFCLK1_M", "Input clock"},
2663 {292, 57, "DEV_SERDES_16G0_CMN_REFCLK1_P", "Input clock"},
2664 {293, 0, "DEV_SERDES_16G1_CORE_REF1_CLK", "Input muxed clock"},
2665 {293, 1, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2666 {293, 2, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2667 {293, 3, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2668 {293, 4, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2669 {293, 5, "DEV_SERDES_16G1_CLK", "Input clock"},
2670 {293, 6, "DEV_SERDES_16G1_IP1_LN0_TXCLK", "Input clock"},
2671 {293, 7, "DEV_SERDES_16G1_IP2_LN1_TXCLK", "Input clock"},
2672 {293, 8, "DEV_SERDES_16G1_IP4_LN1_TXCLK", "Input clock"},
2673 {293, 9, "DEV_SERDES_16G1_IP4_LN0_TXCLK", "Input clock"},
2674 {293, 10, "DEV_SERDES_16G1_IP3_LN1_TXCLK", "Input clock"},
2675 {293, 11, "DEV_SERDES_16G1_IP2_LN0_TXCLK", "Input clock"},
2676 {293, 12, "DEV_SERDES_16G1_IP1_LN1_TXCLK", "Input clock"},
2677 {293, 13, "DEV_SERDES_16G1_CORE_REF_CLK", "Input muxed clock"},
2678 {293, 14, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2679 {293, 15, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2680 {293, 16, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2681 {293, 17, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2682 {293, 18, "DEV_SERDES_16G1_IP2_LN0_TXFCLK", "Output clock"},
2683 {293, 19, "DEV_SERDES_16G1_IP1_LN1_REFCLK", "Output clock"},
2684 {293, 20, "DEV_SERDES_16G1_IP4_LN1_RXFCLK", "Output clock"},
2685 {293, 21, "DEV_SERDES_16G1_IP3_LN1_TXMCLK", "Output clock"},
2686 {293, 22, "DEV_SERDES_16G1_IP3_LN1_TXFCLK", "Output clock"},
2687 {293, 23, "DEV_SERDES_16G1_IP1_LN0_RXFCLK", "Output clock"},
2688 {293, 24, "DEV_SERDES_16G1_IP2_LN1_REFCLK", "Output clock"},
2689 {293, 25, "DEV_SERDES_16G1_IP2_LN1_TXFCLK", "Output clock"},
2690 {293, 26, "DEV_SERDES_16G1_REF_DER_OUT_CLK", "Output clock"},
2691 {293, 27, "DEV_SERDES_16G1_IP1_LN0_TXFCLK", "Output clock"},
2692 {293, 28, "DEV_SERDES_16G1_IP3_LN1_RXFCLK", "Output clock"},
2693 {293, 29, "DEV_SERDES_16G1_IP1_LN1_TXMCLK", "Output clock"},
2694 {293, 30, "DEV_SERDES_16G1_IP1_LN1_RXFCLK", "Output clock"},
2695 {293, 31, "DEV_SERDES_16G1_IP4_LN1_REFCLK", "Output clock"},
2696 {293, 32, "DEV_SERDES_16G1_IP3_LN1_RXCLK", "Output clock"},
2697 {293, 33, "DEV_SERDES_16G1_IP4_LN1_TXMCLK", "Output clock"},
2698 {293, 34, "DEV_SERDES_16G1_IP3_LN1_REFCLK", "Output clock"},
2699 {293, 35, "DEV_SERDES_16G1_IP4_LN0_REFCLK", "Output clock"},
2700 {293, 36, "DEV_SERDES_16G1_IP2_LN1_RXCLK", "Output clock"},
2701 {293, 37, "DEV_SERDES_16G1_IP2_LN0_RXFCLK", "Output clock"},
2702 {293, 38, "DEV_SERDES_16G1_IP1_LN0_RXCLK", "Output clock"},
2703 {293, 39, "DEV_SERDES_16G1_REF_OUT_CLK", "Output clock"},
2704 {293, 40, "DEV_SERDES_16G1_REF1_OUT_CLK", "Output clock"},
2705 {293, 41, "DEV_SERDES_16G1_IP4_LN1_RXCLK", "Output clock"},
2706 {293, 42, "DEV_SERDES_16G1_IP1_LN0_REFCLK", "Output clock"},
2707 {293, 43, "DEV_SERDES_16G1_IP1_LN0_TXMCLK", "Output clock"},
2708 {293, 44, "DEV_SERDES_16G1_IP4_LN0_TXFCLK", "Output clock"},
2709 {293, 45, "DEV_SERDES_16G1_IP4_LN0_RXCLK", "Output clock"},
2710 {293, 46, "DEV_SERDES_16G1_IP2_LN1_RXFCLK", "Output clock"},
2711 {293, 47, "DEV_SERDES_16G1_IP2_LN1_TXMCLK", "Output clock"},
2712 {293, 48, "DEV_SERDES_16G1_IP4_LN0_RXFCLK", "Output clock"},
2713 {293, 49, "DEV_SERDES_16G1_IP2_LN0_REFCLK", "Output clock"},
2714 {293, 50, "DEV_SERDES_16G1_IP2_LN0_TXMCLK", "Output clock"},
2715 {293, 51, "DEV_SERDES_16G1_IP1_LN1_TXFCLK", "Output clock"},
2716 {293, 52, "DEV_SERDES_16G1_IP2_LN0_RXCLK", "Output clock"},
2717 {293, 53, "DEV_SERDES_16G1_IP4_LN0_TXMCLK", "Output clock"},
2718 {293, 54, "DEV_SERDES_16G1_IP1_LN1_RXCLK", "Output clock"},
2719 {293, 55, "DEV_SERDES_16G1_IP4_LN1_TXFCLK", "Output clock"},
2720 {293, 60, "DEV_SERDES_16G1_CMN_REFCLK1_M", "Input clock"},
2721 {293, 67, "DEV_SERDES_16G1_CMN_REFCLK1_P", "Input clock"},
2722 {294, 0, "DEV_SERDES_16G2_CORE_REF1_CLK", "Input muxed clock"},
2723 {294, 1, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
2724 {294, 2, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
2725 {294, 3, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
2726 {294, 4, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
2727 {294, 5, "DEV_SERDES_16G2_CLK", "Input clock"},
2728 {294, 6, "DEV_SERDES_16G2_IP2_LN1_TXCLK", "Input clock"},
2729 {294, 7, "DEV_SERDES_16G2_IP4_LN1_TXCLK", "Input clock"},
2730 {294, 8, "DEV_SERDES_16G2_IP4_LN0_TXCLK", "Input clock"},
2731 {294, 9, "DEV_SERDES_16G2_IP3_LN1_TXCLK", "Input clock"},
2732 {294, 10, "DEV_SERDES_16G2_IP2_LN0_TXCLK", "Input clock"},
2733 {294, 11, "DEV_SERDES_16G2_CORE_REF_CLK", "Input muxed clock"},
2734 {294, 12, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
2735 {294, 13, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
2736 {294, 14, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
2737 {294, 15, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
2738 {294, 16, "DEV_SERDES_16G2_IP2_LN0_TXFCLK", "Output clock"},
2739 {294, 17, "DEV_SERDES_16G2_IP4_LN1_RXFCLK", "Output clock"},
2740 {294, 18, "DEV_SERDES_16G2_IP3_LN1_TXMCLK", "Output clock"},
2741 {294, 19, "DEV_SERDES_16G2_IP3_LN1_TXFCLK", "Output clock"},
2742 {294, 20, "DEV_SERDES_16G2_IP2_LN1_REFCLK", "Output clock"},
2743 {294, 21, "DEV_SERDES_16G2_IP2_LN1_TXFCLK", "Output clock"},
2744 {294, 22, "DEV_SERDES_16G2_REF_DER_OUT_CLK", "Output clock"},
2745 {294, 23, "DEV_SERDES_16G2_IP3_LN1_RXFCLK", "Output clock"},
2746 {294, 24, "DEV_SERDES_16G2_IP4_LN1_REFCLK", "Output clock"},
2747 {294, 25, "DEV_SERDES_16G2_IP3_LN1_RXCLK", "Output clock"},
2748 {294, 26, "DEV_SERDES_16G2_IP4_LN1_TXMCLK", "Output clock"},
2749 {294, 27, "DEV_SERDES_16G2_IP3_LN1_REFCLK", "Output clock"},
2750 {294, 28, "DEV_SERDES_16G2_IP4_LN0_REFCLK", "Output clock"},
2751 {294, 29, "DEV_SERDES_16G2_IP2_LN1_RXCLK", "Output clock"},
2752 {294, 30, "DEV_SERDES_16G2_IP2_LN0_RXFCLK", "Output clock"},
2753 {294, 31, "DEV_SERDES_16G2_REF_OUT_CLK", "Output clock"},
2754 {294, 32, "DEV_SERDES_16G2_REF1_OUT_CLK", "Output clock"},
2755 {294, 33, "DEV_SERDES_16G2_IP4_LN1_RXCLK", "Output clock"},
2756 {294, 34, "DEV_SERDES_16G2_IP4_LN0_TXFCLK", "Output clock"},
2757 {294, 35, "DEV_SERDES_16G2_IP4_LN0_RXCLK", "Output clock"},
2758 {294, 36, "DEV_SERDES_16G2_IP2_LN1_RXFCLK", "Output clock"},
2759 {294, 37, "DEV_SERDES_16G2_IP2_LN1_TXMCLK", "Output clock"},
2760 {294, 38, "DEV_SERDES_16G2_IP4_LN0_RXFCLK", "Output clock"},
2761 {294, 39, "DEV_SERDES_16G2_IP2_LN0_REFCLK", "Output clock"},
2762 {294, 40, "DEV_SERDES_16G2_IP2_LN0_TXMCLK", "Output clock"},
2763 {294, 41, "DEV_SERDES_16G2_IP2_LN0_RXCLK", "Output clock"},
2764 {294, 42, "DEV_SERDES_16G2_IP4_LN0_TXMCLK", "Output clock"},
2765 {294, 43, "DEV_SERDES_16G2_IP4_LN1_TXFCLK", "Output clock"},
2766 {294, 51, "DEV_SERDES_16G2_CMN_REFCLK1_M", "Input clock"},
2767 {294, 61, "DEV_SERDES_16G2_CMN_REFCLK1_P", "Input clock"},
2768 {295, 0, "DEV_SERDES_16G3_CORE_REF1_CLK", "Input muxed clock"},
2769 {295, 1, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
2770 {295, 2, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
2771 {295, 3, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
2772 {295, 4, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
2773 {295, 5, "DEV_SERDES_16G3_CLK", "Input clock"},
2774 {295, 6, "DEV_SERDES_16G3_IP2_LN1_TXCLK", "Input clock"},
2775 {295, 7, "DEV_SERDES_16G3_IP3_LN1_TXCLK", "Input clock"},
2776 {295, 8, "DEV_SERDES_16G3_IP2_LN0_TXCLK", "Input clock"},
2777 {295, 9, "DEV_SERDES_16G3_CORE_REF_CLK", "Input muxed clock"},
2778 {295, 10, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
2779 {295, 11, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
2780 {295, 12, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
2781 {295, 13, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
2782 {295, 14, "DEV_SERDES_16G3_IP2_LN0_TXFCLK", "Output clock"},
2783 {295, 15, "DEV_SERDES_16G3_IP3_LN1_TXMCLK", "Output clock"},
2784 {295, 16, "DEV_SERDES_16G3_IP3_LN1_TXFCLK", "Output clock"},
2785 {295, 17, "DEV_SERDES_16G3_IP2_LN1_REFCLK", "Output clock"},
2786 {295, 18, "DEV_SERDES_16G3_IP2_LN1_TXFCLK", "Output clock"},
2787 {295, 19, "DEV_SERDES_16G3_REF_DER_OUT_CLK", "Output clock"},
2788 {295, 20, "DEV_SERDES_16G3_IP3_LN1_RXFCLK", "Output clock"},
2789 {295, 21, "DEV_SERDES_16G3_IP3_LN1_RXCLK", "Output clock"},
2790 {295, 22, "DEV_SERDES_16G3_IP3_LN1_REFCLK", "Output clock"},
2791 {295, 23, "DEV_SERDES_16G3_IP2_LN1_RXCLK", "Output clock"},
2792 {295, 24, "DEV_SERDES_16G3_IP2_LN0_RXFCLK", "Output clock"},
2793 {295, 25, "DEV_SERDES_16G3_REF_OUT_CLK", "Output clock"},
2794 {295, 26, "DEV_SERDES_16G3_REF1_OUT_CLK", "Output clock"},
2795 {295, 27, "DEV_SERDES_16G3_IP2_LN1_RXFCLK", "Output clock"},
2796 {295, 28, "DEV_SERDES_16G3_IP2_LN1_TXMCLK", "Output clock"},
2797 {295, 29, "DEV_SERDES_16G3_IP2_LN0_REFCLK", "Output clock"},
2798 {295, 30, "DEV_SERDES_16G3_IP2_LN0_TXMCLK", "Output clock"},
2799 {295, 31, "DEV_SERDES_16G3_IP2_LN0_RXCLK", "Output clock"},
2800 {295, 40, "DEV_SERDES_16G3_CMN_REFCLK1_M", "Input clock"},
2801 {295, 51, "DEV_SERDES_16G3_CMN_REFCLK1_P", "Input clock"},
2802 {29, 0, "DEV_STM0_VBUSP_CLK", "Input clock"},
2803 {29, 1, "DEV_STM0_CORE_CLK", "Input clock"},
2804 {29, 2, "DEV_STM0_ATB_CLK", "Input clock"},
2805 {49, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"},
2806 {49, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
2807 {49, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2808 {49, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2809 {49, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2810 {49, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2811 {49, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2812 {49, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2813 {49, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2814 {49, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2815 {49, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2816 {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2817 {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2818 {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2819 {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2820 {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2821 {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2822 {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
2823 {49, 18, "DEV_TIMER0_TIMER_PWM", "Output clock"},
2824 {50, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"},
2825 {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
2826 {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
2827 {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
2828 {60, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"},
2829 {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"},
2830 {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2831 {60, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2832 {60, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2833 {60, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2834 {60, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2835 {60, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2836 {60, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2837 {60, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2838 {60, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2839 {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2840 {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2841 {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2842 {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2843 {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2844 {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2845 {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
2846 {60, 18, "DEV_TIMER10_TIMER_PWM", "Output clock"},
2847 {62, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"},
2848 {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"},
2849 {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
2850 {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
2851 {332, 0, "DEV_TIMER11_CLKSEL_VD_CLK", "Input muxed clock"},
2852 {332, 1, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2853 {332, 2, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2854 {332, 3, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2855 {332, 4, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2856 {332, 5, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2857 {332, 6, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2858 {332, 7, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2859 {332, 8, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2860 {332, 9, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2861 {332, 10, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2862 {332, 11, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2863 {332, 12, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2864 {332, 13, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2865 {332, 14, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2866 {332, 15, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2867 {332, 16, "DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK"},
2868 {63, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"},
2869 {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"},
2870 {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2871 {63, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2872 {63, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2873 {63, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2874 {63, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2875 {63, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2876 {63, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2877 {63, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2878 {63, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2879 {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2880 {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2881 {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2882 {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2883 {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2884 {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2885 {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
2886 {63, 18, "DEV_TIMER12_TIMER_PWM", "Output clock"},
2887 {64, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"},
2888 {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"},
2889 {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
2890 {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
2891 {333, 0, "DEV_TIMER13_CLKSEL_VD_CLK", "Input muxed clock"},
2892 {333, 1, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2893 {333, 2, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2894 {333, 3, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2895 {333, 4, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2896 {333, 5, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2897 {333, 6, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2898 {333, 7, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2899 {333, 8, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2900 {333, 9, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2901 {333, 10, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2902 {333, 11, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2903 {333, 12, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2904 {333, 13, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2905 {333, 14, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2906 {333, 15, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2907 {333, 16, "DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK"},
2908 {65, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"},
2909 {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"},
2910 {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2911 {65, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2912 {65, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2913 {65, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2914 {65, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2915 {65, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2916 {65, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2917 {65, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2918 {65, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2919 {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2920 {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2921 {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2922 {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2923 {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2924 {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2925 {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
2926 {65, 18, "DEV_TIMER14_TIMER_PWM", "Output clock"},
2927 {66, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"},
2928 {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"},
2929 {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
2930 {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
2931 {334, 0, "DEV_TIMER15_CLKSEL_VD_CLK", "Input muxed clock"},
2932 {334, 1, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2933 {334, 2, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2934 {334, 3, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2935 {334, 4, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2936 {334, 5, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2937 {334, 6, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2938 {334, 7, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2939 {334, 8, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2940 {334, 9, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2941 {334, 10, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2942 {334, 11, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2943 {334, 12, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2944 {334, 13, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2945 {334, 14, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2946 {334, 15, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2947 {334, 16, "DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK"},
2948 {67, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"},
2949 {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"},
2950 {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2951 {67, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2952 {67, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2953 {67, 5, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2954 {67, 6, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2955 {67, 7, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2956 {67, 8, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2957 {67, 9, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2958 {67, 10, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2959 {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2960 {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2961 {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2962 {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2963 {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2964 {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2965 {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
2966 {67, 18, "DEV_TIMER16_TIMER_PWM", "Output clock"},
2967 {68, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"},
2968 {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"},
2969 {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
2970 {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
2971 {335, 0, "DEV_TIMER17_CLKSEL_VD_CLK", "Input muxed clock"},
2972 {335, 1, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2973 {335, 2, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2974 {335, 3, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2975 {335, 4, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2976 {335, 5, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2977 {335, 6, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2978 {335, 7, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2979 {335, 8, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2980 {335, 9, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2981 {335, 10, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2982 {335, 11, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2983 {335, 12, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2984 {335, 13, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2985 {335, 14, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2986 {335, 15, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2987 {335, 16, "DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK"},
2988 {69, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"},
2989 {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"},
2990 {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2991 {69, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2992 {69, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2993 {69, 5, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2994 {69, 6, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2995 {69, 7, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2996 {69, 8, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2997 {69, 9, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2998 {69, 10, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
2999 {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
3000 {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
3001 {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
3002 {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
3003 {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
3004 {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
3005 {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
3006 {69, 18, "DEV_TIMER18_TIMER_PWM", "Output clock"},
3007 {70, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"},
3008 {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"},
3009 {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
3010 {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
3011 {336, 0, "DEV_TIMER19_CLKSEL_VD_CLK", "Input muxed clock"},
3012 {336, 1, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3013 {336, 2, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3014 {336, 3, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3015 {336, 4, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3016 {336, 5, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3017 {336, 6, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3018 {336, 7, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3019 {336, 8, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3020 {336, 9, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3021 {336, 10, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3022 {336, 11, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3023 {336, 12, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3024 {336, 13, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3025 {336, 14, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3026 {336, 15, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3027 {336, 16, "DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK"},
3028 {327, 0, "DEV_TIMER1_CLKSEL_VD_CLK", "Input muxed clock"},
3029 {327, 1, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3030 {327, 2, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3031 {327, 3, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3032 {327, 4, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3033 {327, 5, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3034 {327, 6, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3035 {327, 7, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3036 {327, 8, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3037 {327, 9, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3038 {327, 10, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3039 {327, 11, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3040 {327, 12, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3041 {327, 13, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3042 {327, 14, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3043 {327, 15, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3044 {327, 16, "DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK"},
3045 {51, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"},
3046 {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
3047 {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3048 {51, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3049 {51, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3050 {51, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3051 {51, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3052 {51, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3053 {51, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3054 {51, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3055 {51, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3056 {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3057 {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3058 {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3059 {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3060 {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3061 {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3062 {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
3063 {51, 18, "DEV_TIMER2_TIMER_PWM", "Output clock"},
3064 {52, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"},
3065 {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
3066 {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
3067 {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
3068 {328, 0, "DEV_TIMER3_CLKSEL_VD_CLK", "Input muxed clock"},
3069 {328, 1, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3070 {328, 2, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3071 {328, 3, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3072 {328, 4, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3073 {328, 5, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3074 {328, 6, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3075 {328, 7, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3076 {328, 8, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3077 {328, 9, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3078 {328, 10, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3079 {328, 11, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3080 {328, 12, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3081 {328, 13, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3082 {328, 14, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3083 {328, 15, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3084 {328, 16, "DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK"},
3085 {53, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"},
3086 {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
3087 {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3088 {53, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3089 {53, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3090 {53, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3091 {53, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3092 {53, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3093 {53, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3094 {53, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3095 {53, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3096 {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3097 {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3098 {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3099 {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3100 {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3101 {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3102 {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
3103 {53, 18, "DEV_TIMER4_TIMER_PWM", "Output clock"},
3104 {54, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"},
3105 {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
3106 {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
3107 {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
3108 {329, 0, "DEV_TIMER5_CLKSEL_VD_CLK", "Input muxed clock"},
3109 {329, 1, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3110 {329, 2, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3111 {329, 3, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3112 {329, 4, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3113 {329, 5, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3114 {329, 6, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3115 {329, 7, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3116 {329, 8, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3117 {329, 9, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3118 {329, 10, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3119 {329, 11, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3120 {329, 12, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3121 {329, 13, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3122 {329, 14, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3123 {329, 15, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3124 {329, 16, "DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK"},
3125 {55, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"},
3126 {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
3127 {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3128 {55, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3129 {55, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3130 {55, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3131 {55, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3132 {55, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3133 {55, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3134 {55, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3135 {55, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3136 {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3137 {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3138 {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3139 {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3140 {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3141 {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3142 {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
3143 {55, 18, "DEV_TIMER6_TIMER_PWM", "Output clock"},
3144 {57, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"},
3145 {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
3146 {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
3147 {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
3148 {330, 0, "DEV_TIMER7_CLKSEL_VD_CLK", "Input muxed clock"},
3149 {330, 1, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3150 {330, 2, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3151 {330, 3, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3152 {330, 4, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3153 {330, 5, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3154 {330, 6, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3155 {330, 7, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3156 {330, 8, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3157 {330, 9, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3158 {330, 10, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3159 {330, 11, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3160 {330, 12, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3161 {330, 13, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3162 {330, 14, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3163 {330, 15, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3164 {330, 16, "DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK"},
3165 {58, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"},
3166 {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
3167 {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3168 {58, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3169 {58, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3170 {58, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3171 {58, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3172 {58, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3173 {58, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3174 {58, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3175 {58, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3176 {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3177 {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3178 {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3179 {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3180 {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3181 {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3182 {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
3183 {58, 18, "DEV_TIMER8_TIMER_PWM", "Output clock"},
3184 {59, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"},
3185 {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
3186 {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
3187 {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
3188 {331, 0, "DEV_TIMER9_CLKSEL_VD_CLK", "Input muxed clock"},
3189 {331, 1, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3190 {331, 2, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3191 {331, 3, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3192 {331, 4, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3193 {331, 5, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3194 {331, 6, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3195 {331, 7, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3196 {331, 8, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3197 {331, 9, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3198 {331, 10, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3199 {331, 11, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3200 {331, 12, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3201 {331, 13, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3202 {331, 14, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3203 {331, 15, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3204 {331, 16, "DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK"},
3205 {136, 0, "DEV_TIMESYNC_INTRTR0_INTR_CLK", "Input clock"},
3206 {146, 0, "DEV_UART0_FCLK_CLK", "Input clock"},
3207 {146, 1, "DEV_UART0_VBUSP_CLK", "Input clock"},
3208 {278, 0, "DEV_UART1_FCLK_CLK", "Input clock"},
3209 {278, 1, "DEV_UART1_VBUSP_CLK", "Input clock"},
3210 {279, 0, "DEV_UART2_FCLK_CLK", "Input clock"},
3211 {279, 1, "DEV_UART2_VBUSP_CLK", "Input clock"},
3212 {280, 0, "DEV_UART3_FCLK_CLK", "Input clock"},
3213 {280, 1, "DEV_UART3_VBUSP_CLK", "Input clock"},
3214 {281, 0, "DEV_UART4_FCLK_CLK", "Input clock"},
3215 {281, 1, "DEV_UART4_VBUSP_CLK", "Input clock"},
3216 {282, 0, "DEV_UART5_FCLK_CLK", "Input clock"},
3217 {282, 1, "DEV_UART5_VBUSP_CLK", "Input clock"},
3218 {283, 0, "DEV_UART6_FCLK_CLK", "Input clock"},
3219 {283, 1, "DEV_UART6_VBUSP_CLK", "Input clock"},
3220 {284, 0, "DEV_UART7_FCLK_CLK", "Input clock"},
3221 {284, 1, "DEV_UART7_VBUSP_CLK", "Input clock"},
3222 {285, 0, "DEV_UART8_FCLK_CLK", "Input clock"},
3223 {285, 1, "DEV_UART8_VBUSP_CLK", "Input clock"},
3224 {286, 0, "DEV_UART9_FCLK_CLK", "Input clock"},
3225 {286, 1, "DEV_UART9_VBUSP_CLK", "Input clock"},
3226 {277, 0, "DEV_UFS0_UFSHCI_HCLK_CLK", "Input clock"},
3227 {277, 1, "DEV_UFS0_UFSHCI_MCLK_CLK", "Input muxed clock"},
3228 {277, 2, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
3229 {277, 3, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
3230 {277, 4, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
3231 {277, 5, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
3232 {277, 6, "DEV_UFS0_UFSHCI_MPHY_REFCLK", "Output clock"},
3233 {288, 0, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"},
3234 {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
3235 {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
3236 {288, 3, "DEV_USB0_CLK_LPM_CLK", "Input clock"},
3237 {288, 4, "DEV_USB0_BUF_CLK", "Input clock"},
3238 {288, 5, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
3239 {288, 6, "DEV_USB0_PIPE_RXCLK", "Input muxed clock"},
3240 {288, 7, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
3241 {288, 8, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
3242 {288, 9, "DEV_USB0_PIPE_TXMCLK", "Input muxed clock"},
3243 {288, 10, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
3244 {288, 11, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
3245 {288, 12, "DEV_USB0_PIPE_RXFCLK", "Input muxed clock"},
3246 {288, 13, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
3247 {288, 14, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
3248 {288, 15, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
3249 {288, 16, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
3250 {288, 17, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
3251 {288, 18, "DEV_USB0_PCLK_CLK", "Input clock"},
3252 {288, 19, "DEV_USB0_ACLK_CLK", "Input clock"},
3253 {288, 20, "DEV_USB0_PIPE_TXFCLK", "Input muxed clock"},
3254 {288, 21, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
3255 {288, 22, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
3256 {288, 23, "DEV_USB0_PIPE_TXCLK", "Output clock"},
3257 {289, 0, "DEV_USB1_PIPE_REFCLK", "Input muxed clock"},
3258 {289, 1, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"},
3259 {289, 2, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"},
3260 {289, 3, "DEV_USB1_CLK_LPM_CLK", "Input clock"},
3261 {289, 4, "DEV_USB1_BUF_CLK", "Input clock"},
3262 {289, 5, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"},
3263 {289, 6, "DEV_USB1_PIPE_RXCLK", "Input muxed clock"},
3264 {289, 7, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"},
3265 {289, 8, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"},
3266 {289, 9, "DEV_USB1_PIPE_TXMCLK", "Input muxed clock"},
3267 {289, 10, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"},
3268 {289, 11, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"},
3269 {289, 12, "DEV_USB1_PIPE_RXFCLK", "Input muxed clock"},
3270 {289, 13, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"},
3271 {289, 14, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"},
3272 {289, 15, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"},
3273 {289, 16, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
3274 {289, 17, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
3275 {289, 18, "DEV_USB1_PCLK_CLK", "Input clock"},
3276 {289, 19, "DEV_USB1_ACLK_CLK", "Input clock"},
3277 {289, 20, "DEV_USB1_PIPE_TXFCLK", "Input muxed clock"},
3278 {289, 21, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"},
3279 {289, 22, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"},
3280 {289, 23, "DEV_USB1_PIPE_TXCLK", "Output clock"},
3281 {290, 0, "DEV_VPAC0_CLK", "Input clock"},
3282 {290, 1, "DEV_VPAC0_PLL_DCO_CLK", "Input clock"},
3283 {291, 0, "DEV_VPFE0_CCD_PCLK_CLK", "Input clock"},
3284 {291, 1, "DEV_VPFE0_VPFE_CLK", "Input clock"},
3285 {145, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"},
3286 {99, 0, "DEV_WKUP_ESM0_CLK", "Input clock"},
3287 {113, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input clock"},
3288 {114, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input clock"},
3289 {137, 0, "DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
3290 {197, 0, "DEV_WKUP_I2C0_PISYS_CLK", "Input muxed clock"},
3291 {197, 1, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
3292 {197, 2, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
3293 {197, 3, "DEV_WKUP_I2C0_PISCL", "Input clock"},
3294 {197, 4, "DEV_WKUP_I2C0_CLK", "Input clock"},
3295 {197, 5, "DEV_WKUP_I2C0_PORSCL", "Output clock"},
3296 {132, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"},
3297 {138, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"},
3298 {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"},
3299 {287, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"},
3300 {287, 1, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
3301 {287, 2, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
3302 {287, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"},
3303 {154, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"},
3304 {154, 1, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"},
3305 {154, 2, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"},
3306 };