Bump up version to 0.2
[k3conf/k3conf.git] / soc / j721e / j721e_clocks_info.c
1 /*
2  * J721E Clocks Info
3  *
4  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5  *
6  *  Redistribution and use in source and binary forms, with or without
7  *  modification, are permitted provided that the following conditions
8  *  are met:
9  *
10  *    Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  *
13  *    Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the
16  *    distribution.
17  *
18  *    Neither the name of Texas Instruments Incorporated nor the names of
19  *    its contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_clocks_info j721e_clocks_info[] = {
39         [0] = {4, 0, "DEV_A72SS0_PLL_CTRL_CLK", "Input clock"},
40         [1] = {4, 1, "DEV_A72SS0_MSMC_CLK", "Input clock"},
41         [2] = {4, 2, "DEV_A72SS0_ARM_CLK_CLK", "Input clock"},
42         [3] = {202, 2, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
43         [4] = {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"},
44         [5] = {139, 0, "DEV_AASRC0_SYS_CLK", "Input clock"},
45         [6] = {139, 1, "DEV_AASRC0_VBUSP_CLK", "Input clock"},
46         [7] = {139, 2, "DEV_AASRC0_RX0_SYNC", "Input muxed clock"},
47         [8] = {139, 3, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
48         [9] = {139, 4, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
49         [10] = {139, 5, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
50         [11] = {139, 6, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
51         [12] = {139, 7, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
52         [13] = {139, 8, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
53         [14] = {139, 9, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
54         [15] = {139, 10, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
55         [16] = {139, 11, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
56         [17] = {139, 12, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
57         [18] = {139, 13, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
58         [19] = {139, 14, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
59         [20] = {139, 15, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
60         [21] = {139, 16, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
61         [22] = {139, 17, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
62         [23] = {139, 18, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
63         [24] = {139, 19, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
64         [25] = {139, 20, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
65         [26] = {139, 21, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
66         [27] = {139, 22, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
67         [28] = {139, 23, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
68         [29] = {139, 24, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
69         [30] = {139, 25, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
70         [31] = {139, 26, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
71         [32] = {139, 27, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
72         [33] = {139, 28, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
73         [34] = {139, 29, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
74         [35] = {139, 30, "DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
75         [36] = {139, 31, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
76         [37] = {139, 32, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
77         [38] = {139, 33, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
78         [39] = {139, 34, "DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
79         [40] = {139, 35, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
80         [41] = {139, 36, "DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
81         [42] = {139, 37, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
82         [43] = {139, 38, "DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC"},
83         [44] = {139, 39, "DEV_AASRC0_RX1_SYNC", "Input muxed clock"},
84         [45] = {139, 40, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
85         [46] = {139, 41, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
86         [47] = {139, 42, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
87         [48] = {139, 43, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
88         [49] = {139, 44, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
89         [50] = {139, 45, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
90         [51] = {139, 46, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
91         [52] = {139, 47, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
92         [53] = {139, 48, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
93         [54] = {139, 49, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
94         [55] = {139, 50, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
95         [56] = {139, 51, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
96         [57] = {139, 52, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
97         [58] = {139, 53, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
98         [59] = {139, 54, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
99         [60] = {139, 55, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
100         [61] = {139, 56, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
101         [62] = {139, 57, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
102         [63] = {139, 58, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
103         [64] = {139, 59, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
104         [65] = {139, 60, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
105         [66] = {139, 61, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
106         [67] = {139, 62, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
107         [68] = {139, 63, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
108         [69] = {139, 64, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
109         [70] = {139, 65, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
110         [71] = {139, 66, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
111         [72] = {139, 67, "DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
112         [73] = {139, 68, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
113         [74] = {139, 69, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
114         [75] = {139, 70, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
115         [76] = {139, 71, "DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
116         [77] = {139, 72, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
117         [78] = {139, 73, "DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
118         [79] = {139, 74, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
119         [80] = {139, 75, "DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC"},
120         [81] = {139, 76, "DEV_AASRC0_RX2_SYNC", "Input muxed clock"},
121         [82] = {139, 77, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
122         [83] = {139, 78, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
123         [84] = {139, 79, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
124         [85] = {139, 80, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
125         [86] = {139, 81, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
126         [87] = {139, 82, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
127         [88] = {139, 83, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
128         [89] = {139, 84, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
129         [90] = {139, 85, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
130         [91] = {139, 86, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
131         [92] = {139, 87, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
132         [93] = {139, 88, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
133         [94] = {139, 89, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
134         [95] = {139, 90, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
135         [96] = {139, 91, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
136         [97] = {139, 92, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
137         [98] = {139, 93, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
138         [99] = {139, 94, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
139         [100] = {139, 95, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
140         [101] = {139, 96, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
141         [102] = {139, 97, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
142         [103] = {139, 98, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
143         [104] = {139, 99, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
144         [105] = {139, 100, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
145         [106] = {139, 101, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
146         [107] = {139, 102, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
147         [108] = {139, 103, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
148         [109] = {139, 104, "DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
149         [110] = {139, 105, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
150         [111] = {139, 106, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
151         [112] = {139, 107, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
152         [113] = {139, 108, "DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
153         [114] = {139, 109, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
154         [115] = {139, 110, "DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
155         [116] = {139, 111, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
156         [117] = {139, 112, "DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC"},
157         [118] = {139, 113, "DEV_AASRC0_RX3_SYNC", "Input muxed clock"},
158         [119] = {139, 114, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
159         [120] = {139, 115, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
160         [121] = {139, 116, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
161         [122] = {139, 117, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
162         [123] = {139, 118, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
163         [124] = {139, 119, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
164         [125] = {139, 120, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
165         [126] = {139, 121, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
166         [127] = {139, 122, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
167         [128] = {139, 123, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
168         [129] = {139, 124, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
169         [130] = {139, 125, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
170         [131] = {139, 126, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
171         [132] = {139, 127, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
172         [133] = {139, 128, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
173         [134] = {139, 129, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
174         [135] = {139, 130, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
175         [136] = {139, 131, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
176         [137] = {139, 132, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
177         [138] = {139, 133, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
178         [139] = {139, 134, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
179         [140] = {139, 135, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
180         [141] = {139, 136, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
181         [142] = {139, 137, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
182         [143] = {139, 138, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
183         [144] = {139, 139, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
184         [145] = {139, 140, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
185         [146] = {139, 141, "DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
186         [147] = {139, 142, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
187         [148] = {139, 143, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
188         [149] = {139, 144, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
189         [150] = {139, 145, "DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
190         [151] = {139, 146, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
191         [152] = {139, 147, "DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
192         [153] = {139, 148, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
193         [154] = {139, 149, "DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC"},
194         [155] = {139, 150, "DEV_AASRC0_TX0_SYNC", "Input muxed clock"},
195         [156] = {139, 151, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
196         [157] = {139, 152, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
197         [158] = {139, 153, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
198         [159] = {139, 154, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
199         [160] = {139, 155, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
200         [161] = {139, 156, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
201         [162] = {139, 157, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
202         [163] = {139, 158, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
203         [164] = {139, 159, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
204         [165] = {139, 160, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
205         [166] = {139, 161, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
206         [167] = {139, 162, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
207         [168] = {139, 163, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
208         [169] = {139, 164, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
209         [170] = {139, 165, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
210         [171] = {139, 166, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
211         [172] = {139, 167, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
212         [173] = {139, 168, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
213         [174] = {139, 169, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
214         [175] = {139, 170, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
215         [176] = {139, 171, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
216         [177] = {139, 172, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
217         [178] = {139, 173, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
218         [179] = {139, 174, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
219         [180] = {139, 175, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
220         [181] = {139, 176, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
221         [182] = {139, 177, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
222         [183] = {139, 178, "DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
223         [184] = {139, 179, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
224         [185] = {139, 180, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
225         [186] = {139, 181, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
226         [187] = {139, 182, "DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
227         [188] = {139, 183, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
228         [189] = {139, 184, "DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
229         [190] = {139, 185, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
230         [191] = {139, 186, "DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC"},
231         [192] = {139, 187, "DEV_AASRC0_TX1_SYNC", "Input muxed clock"},
232         [193] = {139, 188, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
233         [194] = {139, 189, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
234         [195] = {139, 190, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
235         [196] = {139, 191, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
236         [197] = {139, 192, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
237         [198] = {139, 193, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
238         [199] = {139, 194, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
239         [200] = {139, 195, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
240         [201] = {139, 196, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
241         [202] = {139, 197, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
242         [203] = {139, 198, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
243         [204] = {139, 199, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
244         [205] = {139, 200, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
245         [206] = {139, 201, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
246         [207] = {139, 202, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
247         [208] = {139, 203, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
248         [209] = {139, 204, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
249         [210] = {139, 205, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
250         [211] = {139, 206, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
251         [212] = {139, 207, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
252         [213] = {139, 208, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
253         [214] = {139, 209, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
254         [215] = {139, 210, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
255         [216] = {139, 211, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
256         [217] = {139, 212, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
257         [218] = {139, 213, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
258         [219] = {139, 214, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
259         [220] = {139, 215, "DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
260         [221] = {139, 216, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
261         [222] = {139, 217, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
262         [223] = {139, 218, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
263         [224] = {139, 219, "DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
264         [225] = {139, 220, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
265         [226] = {139, 221, "DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
266         [227] = {139, 222, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
267         [228] = {139, 223, "DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC"},
268         [229] = {139, 224, "DEV_AASRC0_TX2_SYNC", "Input muxed clock"},
269         [230] = {139, 225, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
270         [231] = {139, 226, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
271         [232] = {139, 227, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
272         [233] = {139, 228, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
273         [234] = {139, 229, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
274         [235] = {139, 230, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
275         [236] = {139, 231, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
276         [237] = {139, 232, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
277         [238] = {139, 233, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
278         [239] = {139, 234, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
279         [240] = {139, 235, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
280         [241] = {139, 236, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
281         [242] = {139, 237, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
282         [243] = {139, 238, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
283         [244] = {139, 239, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
284         [245] = {139, 240, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
285         [246] = {139, 241, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
286         [247] = {139, 242, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
287         [248] = {139, 243, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
288         [249] = {139, 244, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
289         [250] = {139, 245, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
290         [251] = {139, 246, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
291         [252] = {139, 247, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
292         [253] = {139, 248, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
293         [254] = {139, 249, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
294         [255] = {139, 250, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
295         [256] = {139, 251, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
296         [257] = {139, 252, "DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
297         [258] = {139, 253, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
298         [259] = {139, 254, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
299         [260] = {139, 255, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
300         [261] = {139, 256, "DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
301         [262] = {139, 257, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
302         [263] = {139, 258, "DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
303         [264] = {139, 259, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
304         [265] = {139, 260, "DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC"},
305         [266] = {139, 261, "DEV_AASRC0_TX3_SYNC", "Input muxed clock"},
306         [267] = {139, 262, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
307         [268] = {139, 263, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
308         [269] = {139, 264, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
309         [270] = {139, 265, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
310         [271] = {139, 266, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
311         [272] = {139, 267, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
312         [273] = {139, 268, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
313         [274] = {139, 269, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
314         [275] = {139, 270, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
315         [276] = {139, 271, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
316         [277] = {139, 272, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
317         [278] = {139, 273, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
318         [279] = {139, 274, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
319         [280] = {139, 275, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
320         [281] = {139, 276, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
321         [282] = {139, 277, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
322         [283] = {139, 278, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
323         [284] = {139, 279, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
324         [285] = {139, 280, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
325         [286] = {139, 281, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
326         [287] = {139, 282, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
327         [288] = {139, 283, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
328         [289] = {139, 284, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
329         [290] = {139, 285, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
330         [291] = {139, 286, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
331         [292] = {139, 287, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
332         [293] = {139, 288, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
333         [294] = {139, 289, "DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
334         [295] = {139, 290, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
335         [296] = {139, 291, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
336         [297] = {139, 292, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
337         [298] = {139, 293, "DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
338         [299] = {139, 294, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
339         [300] = {139, 295, "DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
340         [301] = {139, 296, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
341         [302] = {139, 297, "DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC"},
342         [303] = {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"},
343         [304] = {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
344         [305] = {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
345         [306] = {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
346         [307] = {2, 4, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
347         [308] = {2, 5, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
348         [309] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
349         [310] = {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
350         [311] = {2, 8, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
351         [312] = {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT", "Output clock"},
352         [313] = {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
353         [314] = {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
354         [315] = {157, 0, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
355         [316] = {157, 2, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
356         [317] = {157, 4, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
357         [318] = {157, 6, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
358         [319] = {157, 8, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
359         [320] = {157, 10, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
360         [321] = {157, 12, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
361         [322] = {157, 14, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
362         [323] = {157, 16, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
363         [324] = {157, 18, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
364         [325] = {157, 19, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
365         [326] = {157, 20, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
366         [327] = {157, 21, "DEV_BOARD0_MCU_OSPI1_CLK_IN", "Input clock"},
367         [328] = {157, 22, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"},
368         [329] = {157, 23, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"},
369         [330] = {157, 25, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
370         [331] = {157, 27, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
371         [332] = {157, 29, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
372         [333] = {157, 31, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
373         [334] = {157, 33, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
374         [335] = {157, 35, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
375         [336] = {157, 37, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
376         [337] = {157, 38, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
377         [338] = {157, 39, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
378         [339] = {157, 41, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
379         [340] = {157, 42, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
380         [341] = {157, 43, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
381         [342] = {157, 44, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"},
382         [343] = {157, 45, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"},
383         [344] = {157, 46, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
384         [345] = {157, 47, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
385         [346] = {157, 48, "DEV_BOARD0_MCU_I3C1_SCL_IN", "Input clock"},
386         [347] = {157, 49, "DEV_BOARD0_MCU_I3C1_SCL_OUT", "Output clock"},
387         [348] = {157, 50, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
388         [349] = {157, 51, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
389         [350] = {157, 52, "DEV_BOARD0_DSI_TXCLKP_IN", "Input clock"},
390         [351] = {157, 53, "DEV_BOARD0_DSI_TXCLKN_IN", "Input clock"},
391         [352] = {157, 54, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"},
392         [353] = {157, 55, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"},
393         [354] = {157, 56, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"},
394         [355] = {157, 57, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"},
395         [356] = {157, 58, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"},
396         [357] = {157, 59, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"},
397         [358] = {157, 60, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"},
398         [359] = {157, 61, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"},
399         [360] = {157, 62, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"},
400         [361] = {157, 63, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"},
401         [362] = {157, 64, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"},
402         [363] = {157, 65, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"},
403         [364] = {157, 66, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"},
404         [365] = {157, 67, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"},
405         [366] = {157, 68, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
406         [367] = {157, 70, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"},
407         [368] = {157, 72, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"},
408         [369] = {157, 74, "DEV_BOARD0_RGMII5_RXC_OUT", "Output clock"},
409         [370] = {157, 76, "DEV_BOARD0_RGMII6_RXC_OUT", "Output clock"},
410         [371] = {157, 78, "DEV_BOARD0_RGMII7_RXC_OUT", "Output clock"},
411         [372] = {157, 80, "DEV_BOARD0_RGMII8_RXC_OUT", "Output clock"},
412         [373] = {157, 81, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
413         [374] = {157, 82, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
414         [375] = {157, 83, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
415         [376] = {157, 84, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
416         [377] = {157, 85, "DEV_BOARD0_MCU_RGMII1_TXC_OUT", "Output clock"},
417         [378] = {157, 86, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
418         [379] = {157, 87, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
419         [380] = {157, 88, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
420         [381] = {157, 89, "DEV_BOARD0_UFS0_REF_CLK_IN", "Input clock"},
421         [382] = {157, 91, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"},
422         [383] = {157, 92, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"},
423         [384] = {157, 99, "DEV_BOARD0_MMC0_CLK_IN", "Input clock"},
424         [385] = {157, 100, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
425         [386] = {157, 101, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"},
426         [387] = {157, 102, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
427         [388] = {157, 103, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
428         [389] = {157, 104, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
429         [390] = {157, 105, "DEV_BOARD0_MLB0_MLBCLK_OUT", "Output clock"},
430         [391] = {157, 106, "DEV_BOARD0_MLB0_MLBCP_OUT", "Output clock"},
431         [392] = {157, 108, "DEV_BOARD0_VPFE0_PCLK_OUT", "Output clock"},
432         [393] = {157, 109, "DEV_BOARD0_VOUT1_PCLK_IN", "Input clock"},
433         [394] = {157, 110, "DEV_BOARD0_VOUT1_EXTPCLKIN_OUT", "Output clock"},
434         [395] = {157, 111, "DEV_BOARD0_VOUT2_PCLK_IN", "Input clock"},
435         [396] = {157, 112, "DEV_BOARD0_VOUT2_EXTPCLKIN_OUT", "Output clock"},
436         [397] = {157, 113, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
437         [398] = {157, 114, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
438         [399] = {157, 115, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
439         [400] = {157, 116, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
440         [401] = {157, 117, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
441         [402] = {157, 118, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
442         [403] = {157, 119, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
443         [404] = {157, 120, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
444         [405] = {157, 126, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
445         [406] = {157, 127, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
446         [407] = {157, 128, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
447         [408] = {157, 129, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
448         [409] = {157, 130, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
449         [410] = {157, 131, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
450         [411] = {157, 132, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
451         [412] = {157, 133, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
452         [413] = {157, 137, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
453         [414] = {157, 138, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
454         [415] = {157, 139, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
455         [416] = {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
456         [417] = {157, 141, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
457         [418] = {157, 142, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
458         [419] = {157, 143, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
459         [420] = {157, 144, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
460         [421] = {157, 145, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
461         [422] = {157, 146, "DEV_BOARD0_OBSCLK1_IN", "Input muxed clock"},
462         [423] = {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
463         [424] = {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
464         [425] = {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
465         [426] = {157, 152, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
466         [427] = {157, 153, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
467         [428] = {157, 154, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
468         [429] = {157, 169, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
469         [430] = {157, 170, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
470         [431] = {157, 171, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
471         [432] = {157, 172, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"},
472         [433] = {157, 173, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
473         [434] = {157, 174, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
474         [435] = {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
475         [436] = {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
476         [437] = {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
477         [438] = {157, 178, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
478         [439] = {157, 179, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
479         [440] = {157, 180, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
480         [441] = {157, 181, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
481         [442] = {157, 182, "DEV_BOARD0_TCK_OUT", "Output clock"},
482         [443] = {157, 185, "DEV_BOARD0_PCIE_REFCLK0P_OUT", "Output clock"},
483         [444] = {157, 186, "DEV_BOARD0_PCIE_REFCLK0N_OUT", "Output clock"},
484         [445] = {157, 191, "DEV_BOARD0_PCIE_REFCLK1P_OUT", "Output clock"},
485         [446] = {157, 192, "DEV_BOARD0_PCIE_REFCLK1N_OUT", "Output clock"},
486         [447] = {157, 197, "DEV_BOARD0_PCIE_REFCLK2P_OUT", "Output clock"},
487         [448] = {157, 198, "DEV_BOARD0_PCIE_REFCLK2N_OUT", "Output clock"},
488         [449] = {157, 201, "DEV_BOARD0_PCIE_REFCLK3P_OUT", "Output clock"},
489         [450] = {157, 202, "DEV_BOARD0_PCIE_REFCLK3N_OUT", "Output clock"},
490         [451] = {157, 217, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
491         [452] = {157, 218, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
492         [453] = {157, 219, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"},
493         [454] = {157, 220, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
494         [455] = {157, 221, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
495         [456] = {157, 222, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"},
496         [457] = {157, 223, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
497         [458] = {157, 224, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
498         [459] = {157, 225, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"},
499         [460] = {157, 226, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
500         [461] = {157, 227, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
501         [462] = {157, 228, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"},
502         [463] = {157, 229, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
503         [464] = {157, 230, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
504         [465] = {157, 231, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"},
505         [466] = {157, 232, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
506         [467] = {157, 233, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
507         [468] = {157, 234, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"},
508         [469] = {157, 235, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"},
509         [470] = {157, 236, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"},
510         [471] = {157, 237, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"},
511         [472] = {157, 238, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"},
512         [473] = {157, 239, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"},
513         [474] = {157, 240, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"},
514         [475] = {157, 241, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"},
515         [476] = {157, 242, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"},
516         [477] = {157, 243, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"},
517         [478] = {157, 244, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"},
518         [479] = {157, 245, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"},
519         [480] = {157, 246, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"},
520         [481] = {157, 247, "DEV_BOARD0_MCASP5_ACLKR_IN", "Input clock"},
521         [482] = {157, 248, "DEV_BOARD0_MCASP5_ACLKR_OUT", "Output clock"},
522         [483] = {157, 249, "DEV_BOARD0_MCASP5_AFSR_OUT", "Output clock"},
523         [484] = {157, 250, "DEV_BOARD0_MCASP5_ACLKX_IN", "Input clock"},
524         [485] = {157, 251, "DEV_BOARD0_MCASP5_ACLKX_OUT", "Output clock"},
525         [486] = {157, 252, "DEV_BOARD0_MCASP5_AFSX_OUT", "Output clock"},
526         [487] = {157, 253, "DEV_BOARD0_MCASP6_ACLKR_IN", "Input clock"},
527         [488] = {157, 254, "DEV_BOARD0_MCASP6_ACLKR_OUT", "Output clock"},
528         [489] = {157, 255, "DEV_BOARD0_MCASP6_AFSR_OUT", "Output clock"},
529         [490] = {157, 256, "DEV_BOARD0_MCASP6_ACLKX_IN", "Input clock"},
530         [491] = {157, 257, "DEV_BOARD0_MCASP6_ACLKX_OUT", "Output clock"},
531         [492] = {157, 258, "DEV_BOARD0_MCASP6_AFSX_OUT", "Output clock"},
532         [493] = {157, 259, "DEV_BOARD0_MCASP7_ACLKR_IN", "Input clock"},
533         [494] = {157, 260, "DEV_BOARD0_MCASP7_ACLKR_OUT", "Output clock"},
534         [495] = {157, 261, "DEV_BOARD0_MCASP7_AFSR_OUT", "Output clock"},
535         [496] = {157, 262, "DEV_BOARD0_MCASP7_ACLKX_IN", "Input clock"},
536         [497] = {157, 263, "DEV_BOARD0_MCASP7_ACLKX_OUT", "Output clock"},
537         [498] = {157, 264, "DEV_BOARD0_MCASP7_AFSX_OUT", "Output clock"},
538         [499] = {157, 265, "DEV_BOARD0_MCASP8_ACLKR_IN", "Input clock"},
539         [500] = {157, 267, "DEV_BOARD0_MCASP8_ACLKR_OUT", "Output clock"},
540         [501] = {157, 268, "DEV_BOARD0_MCASP8_AFSR_OUT", "Output clock"},
541         [502] = {157, 269, "DEV_BOARD0_MCASP8_ACLKX_IN", "Input clock"},
542         [503] = {157, 270, "DEV_BOARD0_MCASP8_ACLKX_OUT", "Output clock"},
543         [504] = {157, 271, "DEV_BOARD0_MCASP8_AFSX_OUT", "Output clock"},
544         [505] = {157, 272, "DEV_BOARD0_MCASP9_ACLKR_IN", "Input clock"},
545         [506] = {157, 273, "DEV_BOARD0_MCASP9_ACLKR_OUT", "Output clock"},
546         [507] = {157, 274, "DEV_BOARD0_MCASP9_AFSR_OUT", "Output clock"},
547         [508] = {157, 275, "DEV_BOARD0_MCASP9_ACLKX_IN", "Input clock"},
548         [509] = {157, 276, "DEV_BOARD0_MCASP9_ACLKX_OUT", "Output clock"},
549         [510] = {157, 278, "DEV_BOARD0_MCASP9_AFSX_OUT", "Output clock"},
550         [511] = {157, 279, "DEV_BOARD0_MCASP10_ACLKR_IN", "Input clock"},
551         [512] = {157, 280, "DEV_BOARD0_MCASP10_ACLKR_OUT", "Output clock"},
552         [513] = {157, 281, "DEV_BOARD0_MCASP10_AFSR_OUT", "Output clock"},
553         [514] = {157, 282, "DEV_BOARD0_MCASP10_ACLKX_IN", "Input clock"},
554         [515] = {157, 283, "DEV_BOARD0_MCASP10_ACLKX_OUT", "Output clock"},
555         [516] = {157, 284, "DEV_BOARD0_MCASP10_AFSX_OUT", "Output clock"},
556         [517] = {157, 285, "DEV_BOARD0_MCASP11_ACLKR_IN", "Input clock"},
557         [518] = {157, 286, "DEV_BOARD0_MCASP11_ACLKR_OUT", "Output clock"},
558         [519] = {157, 287, "DEV_BOARD0_MCASP11_AFSR_OUT", "Output clock"},
559         [520] = {157, 288, "DEV_BOARD0_MCASP11_ACLKX_IN", "Input clock"},
560         [521] = {157, 289, "DEV_BOARD0_MCASP11_ACLKX_OUT", "Output clock"},
561         [522] = {157, 290, "DEV_BOARD0_MCASP11_AFSX_OUT", "Output clock"},
562         [523] = {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
563         [524] = {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
564         [525] = {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
565         [526] = {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
566         [527] = {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
567         [528] = {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
568         [529] = {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
569         [530] = {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
570         [531] = {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
571         [532] = {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
572         [533] = {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
573         [534] = {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
574         [535] = {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
575         [536] = {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
576         [537] = {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
577         [538] = {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
578         [539] = {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
579         [540] = {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
580         [541] = {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
581         [542] = {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
582         [543] = {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
583         [544] = {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
584         [545] = {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
585         [546] = {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
586         [547] = {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
587         [548] = {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
588         [549] = {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
589         [550] = {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
590         [551] = {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
591         [552] = {157, 329, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
592         [553] = {157, 330, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
593         [554] = {157, 331, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
594         [555] = {157, 334, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
595         [556] = {157, 335, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
596         [557] = {157, 336, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
597         [558] = {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
598         [559] = {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
599         [560] = {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
600         [561] = {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
601         [562] = {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
602         [563] = {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
603         [564] = {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
604         [565] = {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
605         [566] = {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
606         [567] = {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
607         [568] = {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
608         [569] = {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
609         [570] = {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
610         [571] = {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
611         [572] = {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
612         [573] = {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
613         [574] = {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
614         [575] = {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
615         [576] = {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
616         [577] = {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
617         [578] = {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
618         [579] = {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
619         [580] = {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
620         [581] = {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
621         [582] = {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
622         [583] = {157, 362, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
623         [584] = {157, 363, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
624         [585] = {157, 364, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
625         [586] = {157, 365, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
626         [587] = {157, 366, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
627         [588] = {157, 369, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
628         [589] = {157, 370, "DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT", "Output clock"},
629         [590] = {157, 371, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN", "Input muxed clock"},
630         [591] = {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
631         [592] = {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
632         [593] = {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
633         [594] = {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
634         [595] = {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
635         [596] = {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
636         [597] = {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
637         [598] = {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
638         [599] = {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
639         [600] = {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
640         [601] = {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
641         [602] = {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
642         [603] = {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
643         [604] = {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
644         [605] = {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
645         [606] = {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
646         [607] = {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
647         [608] = {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
648         [609] = {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
649         [610] = {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
650         [611] = {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
651         [612] = {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
652         [613] = {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
653         [614] = {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
654         [615] = {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
655         [616] = {157, 397, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
656         [617] = {157, 398, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
657         [618] = {157, 399, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
658         [619] = {157, 400, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
659         [620] = {157, 401, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
660         [621] = {157, 404, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
661         [622] = {157, 405, "DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT", "Output clock"},
662         [623] = {157, 406, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN", "Input muxed clock"},
663         [624] = {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
664         [625] = {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
665         [626] = {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
666         [627] = {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
667         [628] = {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
668         [629] = {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
669         [630] = {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
670         [631] = {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
671         [632] = {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
672         [633] = {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
673         [634] = {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
674         [635] = {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
675         [636] = {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
676         [637] = {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
677         [638] = {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
678         [639] = {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
679         [640] = {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
680         [641] = {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
681         [642] = {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
682         [643] = {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
683         [644] = {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
684         [645] = {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
685         [646] = {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
686         [647] = {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
687         [648] = {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
688         [649] = {157, 432, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
689         [650] = {157, 433, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
690         [651] = {157, 434, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
691         [652] = {157, 435, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
692         [653] = {157, 436, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
693         [654] = {157, 439, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
694         [655] = {142, 0, "DEV_C66SS0_CORE0_GEM_TRC_CLK", "Input clock"},
695         [656] = {142, 1, "DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
696         [657] = {142, 4, "DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
697         [658] = {142, 6, "DEV_C66SS0_CORE0_GEM_CLKIN_CLK", "Input clock"},
698         [659] = {121, 0, "DEV_C66SS0_INTROUTER0_INTR_CLK", "Input clock"},
699         [660] = {143, 0, "DEV_C66SS1_CORE0_GEM_TRC_CLK", "Input clock"},
700         [661] = {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
701         [662] = {143, 4, "DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK", "Output clock"},
702         [663] = {143, 6, "DEV_C66SS1_CORE0_GEM_CLKIN_CLK", "Input clock"},
703         [664] = {122, 0, "DEV_C66SS1_INTROUTER0_INTR_CLK", "Input clock"},
704         [665] = {15, 0, "DEV_C71SS0_C7X_CLK", "Input clock"},
705         [666] = {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"},
706         [667] = {16, 0, "DEV_C71SS0_MMA_PLL_CTRL_CLK", "Input clock"},
707         [668] = {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"},
708         [669] = {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"},
709         [670] = {5, 0, "DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK", "Input clock"},
710         [671] = {6, 0, "DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK", "Input clock"},
711         [672] = {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"},
712         [673] = {7, 0, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"},
713         [674] = {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"},
714         [675] = {8, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK", "Input clock"},
715         [676] = {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"},
716         [677] = {9, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK", "Input clock"},
717         [678] = {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"},
718         [679] = {12, 0, "DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK", "Input clock"},
719         [680] = {13, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK", "Input clock"},
720         [681] = {14, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"},
721         [682] = {17, 0, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK", "Input clock"},
722         [683] = {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"},
723         [684] = {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"},
724         [685] = {19, 0, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"},
725         [686] = {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"},
726         [687] = {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"},
727         [688] = {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
728         [689] = {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"},
729         [690] = {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"},
730         [691] = {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"},
731         [692] = {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"},
732         [693] = {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"},
733         [694] = {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"},
734         [695] = {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"},
735         [696] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"},
736         [697] = {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"},
737         [698] = {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"},
738         [699] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"},
739         [700] = {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"},
740         [701] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
741         [702] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
742         [703] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
743         [704] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
744         [705] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
745         [706] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
746         [707] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
747         [708] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
748         [709] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
749         [710] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
750         [711] = {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
751         [712] = {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
752         [713] = {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
753         [714] = {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
754         [715] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
755         [716] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
756         [717] = {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
757         [718] = {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"},
758         [719] = {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"},
759         [720] = {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"},
760         [721] = {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"},
761         [722] = {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"},
762         [723] = {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"},
763         [724] = {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"},
764         [725] = {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
765         [726] = {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"},
766         [727] = {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
767         [728] = {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"},
768         [729] = {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"},
769         [730] = {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"},
770         [731] = {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
771         [732] = {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"},
772         [733] = {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"},
773         [734] = {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
774         [735] = {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"},
775         [736] = {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"},
776         [737] = {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"},
777         [738] = {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"},
778         [739] = {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"},
779         [740] = {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"},
780         [741] = {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"},
781         [742] = {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"},
782         [743] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"},
783         [744] = {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"},
784         [745] = {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"},
785         [746] = {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"},
786         [747] = {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"},
787         [748] = {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
788         [749] = {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"},
789         [750] = {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
790         [751] = {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"},
791         [752] = {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"},
792         [753] = {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
793         [754] = {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"},
794         [755] = {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"},
795         [756] = {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"},
796         [757] = {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"},
797         [758] = {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"},
798         [759] = {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"},
799         [760] = {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
800         [761] = {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"},
801         [762] = {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"},
802         [763] = {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"},
803         [764] = {19, 79, "DEV_CPSW0_CPTS_GENF0", "Output clock"},
804         [765] = {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"},
805         [766] = {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"},
806         [767] = {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"},
807         [768] = {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"},
808         [769] = {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"},
809         [770] = {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"},
810         [771] = {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"},
811         [772] = {19, 87, "DEV_CPSW0_MDIO_MDCLK_O", "Output clock"},
812         [773] = {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
813         [774] = {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
814         [775] = {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
815         [776] = {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"},
816         [777] = {25, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"},
817         [778] = {26, 0, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"},
818         [779] = {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"},
819         [780] = {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"},
820         [781] = {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"},
821         [782] = {27, 0, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"},
822         [783] = {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"},
823         [784] = {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"},
824         [785] = {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"},
825         [786] = {28, 0, "DEV_CSI_TX_IF0_ESC_CLK_CLK", "Input clock"},
826         [787] = {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"},
827         [788] = {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"},
828         [789] = {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"},
829         [790] = {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
830         [791] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
831         [792] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
832         [793] = {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
833         [794] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
834         [795] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"},
835         [796] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
836         [797] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
837         [798] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
838         [799] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
839         [800] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
840         [801] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
841         [802] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
842         [803] = {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
843         [804] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
844         [805] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
845         [806] = {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
846         [807] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
847         [808] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"},
848         [809] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
849         [810] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
850         [811] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
851         [812] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
852         [813] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
853         [814] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
854         [815] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
855         [816] = {41, 0, "DEV_DCC10_DCC_INPUT10_CLK", "Input clock"},
856         [817] = {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"},
857         [818] = {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"},
858         [819] = {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"},
859         [820] = {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"},
860         [821] = {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"},
861         [822] = {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"},
862         [823] = {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"},
863         [824] = {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"},
864         [825] = {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"},
865         [826] = {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"},
866         [827] = {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"},
867         [828] = {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"},
868         [829] = {42, 0, "DEV_DCC11_DCC_INPUT10_CLK", "Input clock"},
869         [830] = {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"},
870         [831] = {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"},
871         [832] = {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"},
872         [833] = {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"},
873         [834] = {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"},
874         [835] = {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"},
875         [836] = {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"},
876         [837] = {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"},
877         [838] = {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"},
878         [839] = {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"},
879         [840] = {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"},
880         [841] = {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"},
881         [842] = {43, 0, "DEV_DCC12_DCC_INPUT10_CLK", "Input clock"},
882         [843] = {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"},
883         [844] = {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"},
884         [845] = {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"},
885         [846] = {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"},
886         [847] = {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"},
887         [848] = {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"},
888         [849] = {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"},
889         [850] = {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"},
890         [851] = {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"},
891         [852] = {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"},
892         [853] = {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"},
893         [854] = {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"},
894         [855] = {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
895         [856] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
896         [857] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
897         [858] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
898         [859] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
899         [860] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"},
900         [861] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
901         [862] = {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
902         [863] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
903         [864] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
904         [865] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
905         [866] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
906         [867] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
907         [868] = {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
908         [869] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
909         [870] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
910         [871] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
911         [872] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
912         [873] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"},
913         [874] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
914         [875] = {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
915         [876] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
916         [877] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
917         [878] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
918         [879] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
919         [880] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
920         [881] = {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
921         [882] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
922         [883] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
923         [884] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
924         [885] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
925         [886] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"},
926         [887] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
927         [888] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
928         [889] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
929         [890] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
930         [891] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
931         [892] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
932         [893] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
933         [894] = {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
934         [895] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
935         [896] = {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
936         [897] = {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
937         [898] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
938         [899] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"},
939         [900] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
940         [901] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
941         [902] = {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
942         [903] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
943         [904] = {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"},
944         [905] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
945         [906] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
946         [907] = {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
947         [908] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
948         [909] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
949         [910] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
950         [911] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
951         [912] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"},
952         [913] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
953         [914] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
954         [915] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
955         [916] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
956         [917] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
957         [918] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
958         [919] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
959         [920] = {38, 0, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"},
960         [921] = {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"},
961         [922] = {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"},
962         [923] = {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"},
963         [924] = {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"},
964         [925] = {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"},
965         [926] = {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"},
966         [927] = {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"},
967         [928] = {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"},
968         [929] = {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"},
969         [930] = {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"},
970         [931] = {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"},
971         [932] = {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"},
972         [933] = {39, 0, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"},
973         [934] = {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"},
974         [935] = {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"},
975         [936] = {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"},
976         [937] = {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"},
977         [938] = {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"},
978         [939] = {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"},
979         [940] = {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"},
980         [941] = {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"},
981         [942] = {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"},
982         [943] = {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"},
983         [944] = {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"},
984         [945] = {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"},
985         [946] = {40, 0, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"},
986         [947] = {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"},
987         [948] = {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"},
988         [949] = {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"},
989         [950] = {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"},
990         [951] = {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"},
991         [952] = {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"},
992         [953] = {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"},
993         [954] = {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"},
994         [955] = {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"},
995         [956] = {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"},
996         [957] = {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"},
997         [958] = {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"},
998         [959] = {47, 0, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"},
999         [960] = {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
1000         [961] = {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
1001         [962] = {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"},
1002         [963] = {47, 4, "DEV_DDR0_DDRSS_IO_CK_N", "Output clock"},
1003         [964] = {47, 5, "DEV_DDR0_DDRSS_IO_CK", "Output clock"},
1004         [965] = {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
1005         [966] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
1006         [967] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
1007         [968] = {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK", "Output clock"},
1008         [969] = {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
1009         [970] = {144, 0, "DEV_DECODER0_SYS_CLK", "Input clock"},
1010         [971] = {48, 0, "DEV_DMPAC0_CLK", "Input clock"},
1011         [972] = {48, 1, "DEV_DMPAC0_PLL_DCO_CLK", "Input clock"},
1012         [973] = {305, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"},
1013         [974] = {147, 0, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"},
1014         [975] = {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"},
1015         [976] = {148, 0, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"},
1016         [977] = {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"},
1017         [978] = {296, 0, "DEV_DPHY_TX0_CLK", "Input clock"},
1018         [979] = {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"},
1019         [980] = {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"},
1020         [981] = {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"},
1021         [982] = {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1022         [983] = {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1023         [984] = {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1024         [985] = {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
1025         [986] = {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
1026         [987] = {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"},
1027         [988] = {296, 10, "DEV_DPHY_TX0_CK_P", "Output clock"},
1028         [989] = {296, 11, "DEV_DPHY_TX0_CK_M", "Output clock"},
1029         [990] = {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
1030         [991] = {152, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"},
1031         [992] = {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"},
1032         [993] = {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
1033         [994] = {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
1034         [995] = {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"},
1035         [996] = {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1036         [997] = {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1037         [998] = {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1038         [999] = {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
1039         [1000] = {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"},
1040         [1001] = {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
1041         [1002] = {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
1042         [1003] = {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
1043         [1004] = {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"},
1044         [1005] = {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1045         [1006] = {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1046         [1007] = {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1047         [1008] = {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1048         [1009] = {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
1049         [1010] = {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"},
1050         [1011] = {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"},
1051         [1012] = {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"},
1052         [1013] = {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"},
1053         [1014] = {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"},
1054         [1015] = {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"},
1055         [1016] = {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
1056         [1017] = {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
1057         [1018] = {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"},
1058         [1019] = {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
1059         [1020] = {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
1060         [1021] = {150, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"},
1061         [1022] = {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"},
1062         [1023] = {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"},
1063         [1024] = {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"},
1064         [1025] = {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"},
1065         [1026] = {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"},
1066         [1027] = {151, 0, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"},
1067         [1028] = {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"},
1068         [1029] = {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"},
1069         [1030] = {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"},
1070         [1031] = {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"},
1071         [1032] = {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"},
1072         [1033] = {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"},
1073         [1034] = {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"},
1074         [1035] = {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"},
1075         [1036] = {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"},
1076         [1037] = {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"},
1077         [1038] = {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"},
1078         [1039] = {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"},
1079         [1040] = {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"},
1080         [1041] = {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"},
1081         [1042] = {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"},
1082         [1043] = {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"},
1083         [1044] = {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"},
1084         [1045] = {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"},
1085         [1046] = {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"},
1086         [1047] = {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"},
1087         [1048] = {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"},
1088         [1049] = {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"},
1089         [1050] = {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"},
1090         [1051] = {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"},
1091         [1052] = {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"},
1092         [1053] = {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"},
1093         [1054] = {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"},
1094         [1055] = {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"},
1095         [1056] = {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"},
1096         [1057] = {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"},
1097         [1058] = {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"},
1098         [1059] = {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
1099         [1060] = {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
1100         [1061] = {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
1101         [1062] = {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"},
1102         [1063] = {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"},
1103         [1064] = {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"},
1104         [1065] = {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"},
1105         [1066] = {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"},
1106         [1067] = {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"},
1107         [1068] = {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
1108         [1069] = {153, 0, "DEV_ENCODER0_SYS_CLK", "Input clock"},
1109         [1070] = {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
1110         [1071] = {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
1111         [1072] = {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
1112         [1073] = {97, 0, "DEV_ESM0_CLK", "Input clock"},
1113         [1074] = {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
1114         [1075] = {106, 0, "DEV_GPIO1_MMR_CLK", "Input clock"},
1115         [1076] = {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"},
1116         [1077] = {108, 0, "DEV_GPIO3_MMR_CLK", "Input clock"},
1117         [1078] = {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"},
1118         [1079] = {110, 0, "DEV_GPIO5_MMR_CLK", "Input clock"},
1119         [1080] = {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"},
1120         [1081] = {112, 0, "DEV_GPIO7_MMR_CLK", "Input clock"},
1121         [1082] = {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
1122         [1083] = {115, 0, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
1123         [1084] = {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"},
1124         [1085] = {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
1125         [1086] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1126         [1087] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1127         [1088] = {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1128         [1089] = {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
1129         [1090] = {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
1130         [1091] = {125, 0, "DEV_GPU0_GPU_0_GPU_PLL_CLK", "Input clock"},
1131         [1092] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"},
1132         [1093] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
1133         [1094] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1134         [1095] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1135         [1096] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1136         [1097] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1137         [1098] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1138         [1099] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1139         [1100] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1140         [1101] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1141         [1102] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1142         [1103] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1143         [1104] = {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1144         [1105] = {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1145         [1106] = {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1146         [1107] = {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1147         [1108] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1148         [1109] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
1149         [1110] = {187, 0, "DEV_I2C0_PISYS_CLK", "Input clock"},
1150         [1111] = {187, 1, "DEV_I2C0_PISCL", "Input clock"},
1151         [1112] = {187, 2, "DEV_I2C0_CLK", "Input clock"},
1152         [1113] = {188, 0, "DEV_I2C1_PISYS_CLK", "Input clock"},
1153         [1114] = {188, 1, "DEV_I2C1_PISCL", "Input clock"},
1154         [1115] = {188, 2, "DEV_I2C1_CLK", "Input clock"},
1155         [1116] = {189, 0, "DEV_I2C2_PISYS_CLK", "Input clock"},
1156         [1117] = {189, 1, "DEV_I2C2_PISCL", "Input clock"},
1157         [1118] = {189, 2, "DEV_I2C2_CLK", "Input clock"},
1158         [1119] = {190, 0, "DEV_I2C3_PISYS_CLK", "Input clock"},
1159         [1120] = {190, 1, "DEV_I2C3_PISCL", "Input clock"},
1160         [1121] = {190, 2, "DEV_I2C3_CLK", "Input clock"},
1161         [1122] = {191, 0, "DEV_I2C4_PISYS_CLK", "Input clock"},
1162         [1123] = {191, 1, "DEV_I2C4_PISCL", "Input clock"},
1163         [1124] = {191, 2, "DEV_I2C4_CLK", "Input clock"},
1164         [1125] = {192, 0, "DEV_I2C5_PISYS_CLK", "Input clock"},
1165         [1126] = {192, 1, "DEV_I2C5_PISCL", "Input clock"},
1166         [1127] = {192, 2, "DEV_I2C5_CLK", "Input clock"},
1167         [1128] = {193, 0, "DEV_I2C6_PISYS_CLK", "Input clock"},
1168         [1129] = {193, 1, "DEV_I2C6_PISCL", "Input clock"},
1169         [1130] = {193, 2, "DEV_I2C6_CLK", "Input clock"},
1170         [1131] = {116, 0, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"},
1171         [1132] = {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"},
1172         [1133] = {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"},
1173         [1134] = {116, 3, "DEV_I3C0_I3C_SCL_DO", "Output clock"},
1174         [1135] = {127, 0, "DEV_LED0_LED_CLK", "Input clock"},
1175         [1136] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
1176         [1137] = {128, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"},
1177         [1138] = {130, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"},
1178         [1139] = {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
1179         [1140] = {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
1180         [1141] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1181         [1142] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1182         [1143] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1183         [1144] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
1184         [1145] = {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
1185         [1146] = {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
1186         [1147] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1187         [1148] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1188         [1149] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1189         [1150] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
1190         [1151] = {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"},
1191         [1152] = {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
1192         [1153] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1193         [1154] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1194         [1155] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1195         [1156] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
1196         [1157] = {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"},
1197         [1158] = {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
1198         [1159] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1199         [1160] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1200         [1161] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1201         [1162] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
1202         [1163] = {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"},
1203         [1164] = {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
1204         [1165] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1205         [1166] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1206         [1167] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1207         [1168] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
1208         [1169] = {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"},
1209         [1170] = {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
1210         [1171] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1211         [1172] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1212         [1173] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1213         [1174] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
1214         [1175] = {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"},
1215         [1176] = {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
1216         [1177] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1217         [1178] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1218         [1179] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1219         [1180] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
1220         [1181] = {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"},
1221         [1182] = {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
1222         [1183] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1223         [1184] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1224         [1185] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1225         [1186] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
1226         [1187] = {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"},
1227         [1188] = {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
1228         [1189] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1229         [1190] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1230         [1191] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1231         [1192] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
1232         [1193] = {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"},
1233         [1194] = {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
1234         [1195] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1235         [1196] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1236         [1197] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1237         [1198] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
1238         [1199] = {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"},
1239         [1200] = {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
1240         [1201] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1241         [1202] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1242         [1203] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1243         [1204] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
1244         [1205] = {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"},
1245         [1206] = {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
1246         [1207] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1247         [1208] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1248         [1209] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1249         [1210] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
1250         [1211] = {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"},
1251         [1212] = {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
1252         [1213] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1253         [1214] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1254         [1215] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1255         [1216] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
1256         [1217] = {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"},
1257         [1218] = {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
1258         [1219] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1259         [1220] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1260         [1221] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1261         [1222] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
1262         [1223] = {174, 0, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
1263         [1224] = {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
1264         [1225] = {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1265         [1226] = {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1266         [1227] = {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1267         [1228] = {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1268         [1229] = {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1269         [1230] = {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1270         [1231] = {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
1271         [1232] = {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT", "Output clock"},
1272         [1233] = {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN", "Input clock"},
1273         [1234] = {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT", "Output clock"},
1274         [1235] = {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN", "Input clock"},
1275         [1236] = {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT", "Output clock"},
1276         [1237] = {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN", "Input muxed clock"},
1277         [1238] = {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1278         [1239] = {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1279         [1240] = {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1280         [1241] = {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1281         [1242] = {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1282         [1243] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1283         [1244] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1284         [1245] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1285         [1246] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1286         [1247] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1287         [1248] = {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1288         [1249] = {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN"},
1289         [1250] = {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT", "Output clock"},
1290         [1251] = {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN", "Input muxed clock"},
1291         [1252] = {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1292         [1253] = {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1293         [1254] = {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1294         [1255] = {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1295         [1256] = {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1296         [1257] = {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1297         [1258] = {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1298         [1259] = {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1299         [1260] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1300         [1261] = {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1301         [1262] = {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1302         [1263] = {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN"},
1303         [1264] = {175, 0, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
1304         [1265] = {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
1305         [1266] = {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1306         [1267] = {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1307         [1268] = {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1308         [1269] = {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1309         [1270] = {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1310         [1271] = {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1311         [1272] = {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
1312         [1273] = {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT", "Output clock"},
1313         [1274] = {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN", "Input clock"},
1314         [1275] = {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT", "Output clock"},
1315         [1276] = {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN", "Input clock"},
1316         [1277] = {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT", "Output clock"},
1317         [1278] = {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN", "Input muxed clock"},
1318         [1279] = {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1319         [1280] = {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1320         [1281] = {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1321         [1282] = {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1322         [1283] = {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1323         [1284] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1324         [1285] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1325         [1286] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1326         [1287] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1327         [1288] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1328         [1289] = {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1329         [1290] = {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN"},
1330         [1291] = {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT", "Output clock"},
1331         [1292] = {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN", "Input muxed clock"},
1332         [1293] = {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1333         [1294] = {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1334         [1295] = {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1335         [1296] = {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1336         [1297] = {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1337         [1298] = {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1338         [1299] = {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1339         [1300] = {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1340         [1301] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1341         [1302] = {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1342         [1303] = {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1343         [1304] = {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN"},
1344         [1305] = {184, 0, "DEV_MCASP10_VBUSP_CLK", "Input clock"},
1345         [1306] = {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"},
1346         [1307] = {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1347         [1308] = {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1348         [1309] = {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1349         [1310] = {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1350         [1311] = {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1351         [1312] = {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1352         [1313] = {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
1353         [1314] = {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT", "Output clock"},
1354         [1315] = {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN", "Input clock"},
1355         [1316] = {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT", "Output clock"},
1356         [1317] = {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN", "Input clock"},
1357         [1318] = {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT", "Output clock"},
1358         [1319] = {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN", "Input muxed clock"},
1359         [1320] = {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1360         [1321] = {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1361         [1322] = {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1362         [1323] = {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1363         [1324] = {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1364         [1325] = {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1365         [1326] = {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1366         [1327] = {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1367         [1328] = {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1368         [1329] = {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1369         [1330] = {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1370         [1331] = {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN"},
1371         [1332] = {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT", "Output clock"},
1372         [1333] = {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN", "Input muxed clock"},
1373         [1334] = {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1374         [1335] = {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1375         [1336] = {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1376         [1337] = {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1377         [1338] = {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1378         [1339] = {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1379         [1340] = {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1380         [1341] = {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1381         [1342] = {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1382         [1343] = {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1383         [1344] = {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1384         [1345] = {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN"},
1385         [1346] = {185, 0, "DEV_MCASP11_VBUSP_CLK", "Input clock"},
1386         [1347] = {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"},
1387         [1348] = {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1388         [1349] = {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1389         [1350] = {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1390         [1351] = {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1391         [1352] = {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1392         [1353] = {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1393         [1354] = {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
1394         [1355] = {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT", "Output clock"},
1395         [1356] = {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN", "Input clock"},
1396         [1357] = {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT", "Output clock"},
1397         [1358] = {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN", "Input clock"},
1398         [1359] = {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT", "Output clock"},
1399         [1360] = {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN", "Input muxed clock"},
1400         [1361] = {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1401         [1362] = {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1402         [1363] = {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1403         [1364] = {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1404         [1365] = {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1405         [1366] = {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1406         [1367] = {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1407         [1368] = {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1408         [1369] = {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1409         [1370] = {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1410         [1371] = {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1411         [1372] = {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN"},
1412         [1373] = {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT", "Output clock"},
1413         [1374] = {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN", "Input muxed clock"},
1414         [1375] = {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1415         [1376] = {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1416         [1377] = {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1417         [1378] = {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1418         [1379] = {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1419         [1380] = {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1420         [1381] = {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1421         [1382] = {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1422         [1383] = {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1423         [1384] = {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1424         [1385] = {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1425         [1386] = {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN"},
1426         [1387] = {176, 0, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
1427         [1388] = {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
1428         [1389] = {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1429         [1390] = {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1430         [1391] = {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1431         [1392] = {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1432         [1393] = {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1433         [1394] = {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1434         [1395] = {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
1435         [1396] = {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT", "Output clock"},
1436         [1397] = {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN", "Input clock"},
1437         [1398] = {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT", "Output clock"},
1438         [1399] = {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN", "Input clock"},
1439         [1400] = {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT", "Output clock"},
1440         [1401] = {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN", "Input muxed clock"},
1441         [1402] = {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1442         [1403] = {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1443         [1404] = {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1444         [1405] = {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1445         [1406] = {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1446         [1407] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1447         [1408] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1448         [1409] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1449         [1410] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1450         [1411] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1451         [1412] = {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1452         [1413] = {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN"},
1453         [1414] = {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT", "Output clock"},
1454         [1415] = {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN", "Input muxed clock"},
1455         [1416] = {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1456         [1417] = {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1457         [1418] = {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1458         [1419] = {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1459         [1420] = {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1460         [1421] = {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1461         [1422] = {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1462         [1423] = {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1463         [1424] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1464         [1425] = {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1465         [1426] = {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1466         [1427] = {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN"},
1467         [1428] = {177, 0, "DEV_MCASP3_VBUSP_CLK", "Input clock"},
1468         [1429] = {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"},
1469         [1430] = {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1470         [1431] = {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1471         [1432] = {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1472         [1433] = {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1473         [1434] = {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1474         [1435] = {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1475         [1436] = {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
1476         [1437] = {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT", "Output clock"},
1477         [1438] = {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN", "Input clock"},
1478         [1439] = {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT", "Output clock"},
1479         [1440] = {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN", "Input clock"},
1480         [1441] = {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT", "Output clock"},
1481         [1442] = {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN", "Input muxed clock"},
1482         [1443] = {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1483         [1444] = {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1484         [1445] = {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1485         [1446] = {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1486         [1447] = {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1487         [1448] = {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1488         [1449] = {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1489         [1450] = {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1490         [1451] = {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1491         [1452] = {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1492         [1453] = {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1493         [1454] = {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN"},
1494         [1455] = {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT", "Output clock"},
1495         [1456] = {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN", "Input muxed clock"},
1496         [1457] = {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1497         [1458] = {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1498         [1459] = {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1499         [1460] = {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1500         [1461] = {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1501         [1462] = {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1502         [1463] = {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1503         [1464] = {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1504         [1465] = {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1505         [1466] = {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1506         [1467] = {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1507         [1468] = {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN"},
1508         [1469] = {178, 0, "DEV_MCASP4_VBUSP_CLK", "Input clock"},
1509         [1470] = {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"},
1510         [1471] = {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1511         [1472] = {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1512         [1473] = {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1513         [1474] = {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1514         [1475] = {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1515         [1476] = {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1516         [1477] = {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
1517         [1478] = {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT", "Output clock"},
1518         [1479] = {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN", "Input clock"},
1519         [1480] = {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT", "Output clock"},
1520         [1481] = {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN", "Input clock"},
1521         [1482] = {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT", "Output clock"},
1522         [1483] = {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN", "Input muxed clock"},
1523         [1484] = {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1524         [1485] = {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1525         [1486] = {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1526         [1487] = {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1527         [1488] = {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1528         [1489] = {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1529         [1490] = {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1530         [1491] = {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1531         [1492] = {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1532         [1493] = {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1533         [1494] = {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1534         [1495] = {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN"},
1535         [1496] = {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT", "Output clock"},
1536         [1497] = {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN", "Input muxed clock"},
1537         [1498] = {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1538         [1499] = {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1539         [1500] = {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1540         [1501] = {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1541         [1502] = {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1542         [1503] = {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1543         [1504] = {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1544         [1505] = {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1545         [1506] = {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1546         [1507] = {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1547         [1508] = {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1548         [1509] = {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN"},
1549         [1510] = {179, 0, "DEV_MCASP5_VBUSP_CLK", "Input clock"},
1550         [1511] = {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"},
1551         [1512] = {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1552         [1513] = {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1553         [1514] = {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1554         [1515] = {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1555         [1516] = {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1556         [1517] = {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1557         [1518] = {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
1558         [1519] = {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT", "Output clock"},
1559         [1520] = {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN", "Input clock"},
1560         [1521] = {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT", "Output clock"},
1561         [1522] = {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN", "Input clock"},
1562         [1523] = {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT", "Output clock"},
1563         [1524] = {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN", "Input muxed clock"},
1564         [1525] = {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1565         [1526] = {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1566         [1527] = {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1567         [1528] = {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1568         [1529] = {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1569         [1530] = {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1570         [1531] = {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1571         [1532] = {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1572         [1533] = {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1573         [1534] = {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1574         [1535] = {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1575         [1536] = {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN"},
1576         [1537] = {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT", "Output clock"},
1577         [1538] = {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN", "Input muxed clock"},
1578         [1539] = {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1579         [1540] = {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1580         [1541] = {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1581         [1542] = {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1582         [1543] = {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1583         [1544] = {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1584         [1545] = {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1585         [1546] = {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1586         [1547] = {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1587         [1548] = {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1588         [1549] = {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1589         [1550] = {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN"},
1590         [1551] = {180, 0, "DEV_MCASP6_VBUSP_CLK", "Input clock"},
1591         [1552] = {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"},
1592         [1553] = {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1593         [1554] = {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1594         [1555] = {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1595         [1556] = {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1596         [1557] = {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1597         [1558] = {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1598         [1559] = {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
1599         [1560] = {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT", "Output clock"},
1600         [1561] = {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN", "Input clock"},
1601         [1562] = {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT", "Output clock"},
1602         [1563] = {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN", "Input clock"},
1603         [1564] = {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT", "Output clock"},
1604         [1565] = {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN", "Input muxed clock"},
1605         [1566] = {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1606         [1567] = {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1607         [1568] = {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1608         [1569] = {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1609         [1570] = {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1610         [1571] = {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1611         [1572] = {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1612         [1573] = {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1613         [1574] = {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1614         [1575] = {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1615         [1576] = {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1616         [1577] = {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN"},
1617         [1578] = {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT", "Output clock"},
1618         [1579] = {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN", "Input muxed clock"},
1619         [1580] = {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1620         [1581] = {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1621         [1582] = {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1622         [1583] = {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1623         [1584] = {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1624         [1585] = {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1625         [1586] = {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1626         [1587] = {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1627         [1588] = {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1628         [1589] = {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1629         [1590] = {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1630         [1591] = {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN"},
1631         [1592] = {181, 0, "DEV_MCASP7_VBUSP_CLK", "Input clock"},
1632         [1593] = {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"},
1633         [1594] = {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1634         [1595] = {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1635         [1596] = {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1636         [1597] = {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1637         [1598] = {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1638         [1599] = {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1639         [1600] = {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
1640         [1601] = {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT", "Output clock"},
1641         [1602] = {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN", "Input clock"},
1642         [1603] = {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT", "Output clock"},
1643         [1604] = {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN", "Input clock"},
1644         [1605] = {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT", "Output clock"},
1645         [1606] = {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN", "Input muxed clock"},
1646         [1607] = {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1647         [1608] = {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1648         [1609] = {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1649         [1610] = {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1650         [1611] = {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1651         [1612] = {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1652         [1613] = {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1653         [1614] = {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1654         [1615] = {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1655         [1616] = {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1656         [1617] = {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1657         [1618] = {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN"},
1658         [1619] = {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT", "Output clock"},
1659         [1620] = {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN", "Input muxed clock"},
1660         [1621] = {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1661         [1622] = {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1662         [1623] = {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1663         [1624] = {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1664         [1625] = {181, 34, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1665         [1626] = {181, 35, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1666         [1627] = {181, 36, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1667         [1628] = {181, 37, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1668         [1629] = {181, 38, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1669         [1630] = {181, 39, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1670         [1631] = {181, 40, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1671         [1632] = {181, 41, "DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN"},
1672         [1633] = {182, 0, "DEV_MCASP8_VBUSP_CLK", "Input clock"},
1673         [1634] = {182, 1, "DEV_MCASP8_AUX_CLK", "Input muxed clock"},
1674         [1635] = {182, 2, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1675         [1636] = {182, 3, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1676         [1637] = {182, 4, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1677         [1638] = {182, 6, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1678         [1639] = {182, 7, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1679         [1640] = {182, 8, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1680         [1641] = {182, 9, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
1681         [1642] = {182, 10, "DEV_MCASP8_MCASP_ACLKX_POUT", "Output clock"},
1682         [1643] = {182, 11, "DEV_MCASP8_MCASP_ACLKX_PIN", "Input clock"},
1683         [1644] = {182, 12, "DEV_MCASP8_MCASP_ACLKR_POUT", "Output clock"},
1684         [1645] = {182, 13, "DEV_MCASP8_MCASP_ACLKR_PIN", "Input clock"},
1685         [1646] = {182, 14, "DEV_MCASP8_MCASP_AHCLKX_POUT", "Output clock"},
1686         [1647] = {182, 15, "DEV_MCASP8_MCASP_AHCLKX_PIN", "Input muxed clock"},
1687         [1648] = {182, 16, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1688         [1649] = {182, 17, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1689         [1650] = {182, 18, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1690         [1651] = {182, 19, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1691         [1652] = {182, 20, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1692         [1653] = {182, 21, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1693         [1654] = {182, 22, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1694         [1655] = {182, 23, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1695         [1656] = {182, 24, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1696         [1657] = {182, 25, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1697         [1658] = {182, 26, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1698         [1659] = {182, 27, "DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN"},
1699         [1660] = {182, 28, "DEV_MCASP8_MCASP_AHCLKR_POUT", "Output clock"},
1700         [1661] = {182, 29, "DEV_MCASP8_MCASP_AHCLKR_PIN", "Input muxed clock"},
1701         [1662] = {182, 30, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1702         [1663] = {182, 31, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1703         [1664] = {182, 32, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1704         [1665] = {182, 33, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1705         [1666] = {182, 34, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1706         [1667] = {182, 35, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1707         [1668] = {182, 36, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1708         [1669] = {182, 37, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1709         [1670] = {182, 38, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1710         [1671] = {182, 39, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1711         [1672] = {182, 40, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1712         [1673] = {182, 41, "DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN"},
1713         [1674] = {183, 0, "DEV_MCASP9_VBUSP_CLK", "Input clock"},
1714         [1675] = {183, 1, "DEV_MCASP9_AUX_CLK", "Input muxed clock"},
1715         [1676] = {183, 2, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1716         [1677] = {183, 3, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1717         [1678] = {183, 4, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1718         [1679] = {183, 6, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1719         [1680] = {183, 7, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1720         [1681] = {183, 8, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1721         [1682] = {183, 9, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
1722         [1683] = {183, 10, "DEV_MCASP9_MCASP_ACLKX_POUT", "Output clock"},
1723         [1684] = {183, 11, "DEV_MCASP9_MCASP_ACLKX_PIN", "Input clock"},
1724         [1685] = {183, 12, "DEV_MCASP9_MCASP_ACLKR_POUT", "Output clock"},
1725         [1686] = {183, 13, "DEV_MCASP9_MCASP_ACLKR_PIN", "Input clock"},
1726         [1687] = {183, 14, "DEV_MCASP9_MCASP_AHCLKX_POUT", "Output clock"},
1727         [1688] = {183, 15, "DEV_MCASP9_MCASP_AHCLKX_PIN", "Input muxed clock"},
1728         [1689] = {183, 16, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1729         [1690] = {183, 17, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1730         [1691] = {183, 18, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1731         [1692] = {183, 19, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1732         [1693] = {183, 20, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1733         [1694] = {183, 21, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1734         [1695] = {183, 22, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1735         [1696] = {183, 23, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1736         [1697] = {183, 24, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1737         [1698] = {183, 25, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1738         [1699] = {183, 26, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1739         [1700] = {183, 27, "DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN"},
1740         [1701] = {183, 28, "DEV_MCASP9_MCASP_AHCLKR_POUT", "Output clock"},
1741         [1702] = {183, 29, "DEV_MCASP9_MCASP_AHCLKR_PIN", "Input muxed clock"},
1742         [1703] = {183, 30, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1743         [1704] = {183, 31, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1744         [1705] = {183, 32, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1745         [1706] = {183, 33, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1746         [1707] = {183, 34, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1747         [1708] = {183, 35, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1748         [1709] = {183, 36, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1749         [1710] = {183, 37, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1750         [1711] = {183, 38, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1751         [1712] = {183, 39, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1752         [1713] = {183, 40, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1753         [1714] = {183, 41, "DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN"},
1754         [1715] = {266, 0, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
1755         [1716] = {266, 1, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
1756         [1717] = {266, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
1757         [1718] = {267, 0, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
1758         [1719] = {267, 1, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
1759         [1720] = {267, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
1760         [1721] = {268, 0, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
1761         [1722] = {268, 1, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
1762         [1723] = {268, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
1763         [1724] = {269, 0, "DEV_MCSPI3_VBUSP_CLK", "Input clock"},
1764         [1725] = {269, 1, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
1765         [1726] = {269, 2, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
1766         [1727] = {269, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
1767         [1728] = {269, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
1768         [1729] = {270, 0, "DEV_MCSPI4_VBUSP_CLK", "Input clock"},
1769         [1730] = {270, 1, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
1770         [1731] = {270, 2, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"},
1771         [1732] = {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
1772         [1733] = {271, 0, "DEV_MCSPI5_VBUSP_CLK", "Input clock"},
1773         [1734] = {271, 1, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"},
1774         [1735] = {271, 2, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"},
1775         [1736] = {272, 0, "DEV_MCSPI6_VBUSP_CLK", "Input clock"},
1776         [1737] = {272, 1, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"},
1777         [1738] = {272, 2, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"},
1778         [1739] = {273, 0, "DEV_MCSPI7_VBUSP_CLK", "Input clock"},
1779         [1740] = {273, 1, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"},
1780         [1741] = {273, 2, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"},
1781         [1742] = {0, 0, "DEV_MCU_ADC12_16FFC0_SYS_CLK", "Input clock"},
1782         [1743] = {0, 1, "DEV_MCU_ADC12_16FFC0_ADC_CLK", "Input muxed clock"},
1783         [1744] = {0, 2, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1784         [1745] = {0, 3, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1785         [1746] = {0, 4, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1786         [1747] = {0, 5, "DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK"},
1787         [1748] = {0, 6, "DEV_MCU_ADC12_16FFC0_VBUS_CLK", "Input clock"},
1788         [1749] = {1, 0, "DEV_MCU_ADC12_16FFC1_SYS_CLK", "Input clock"},
1789         [1750] = {1, 1, "DEV_MCU_ADC12_16FFC1_ADC_CLK", "Input muxed clock"},
1790         [1751] = {1, 2, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1791         [1752] = {1, 3, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1792         [1753] = {1, 4, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1793         [1754] = {1, 5, "DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK"},
1794         [1755] = {1, 6, "DEV_MCU_ADC12_16FFC1_VBUS_CLK", "Input clock"},
1795         [1756] = {18, 0, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"},
1796         [1757] = {18, 1, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
1797         [1758] = {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
1798         [1759] = {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1799         [1760] = {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1800         [1761] = {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1801         [1762] = {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1802         [1763] = {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1803         [1764] = {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1804         [1765] = {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1805         [1766] = {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1806         [1767] = {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1807         [1768] = {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1808         [1769] = {18, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1809         [1770] = {18, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1810         [1771] = {18, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1811         [1772] = {18, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1812         [1773] = {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1813         [1774] = {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
1814         [1775] = {18, 19, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"},
1815         [1776] = {18, 20, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
1816         [1777] = {18, 21, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
1817         [1778] = {18, 22, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"},
1818         [1779] = {18, 23, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
1819         [1780] = {18, 24, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"},
1820         [1781] = {18, 25, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"},
1821         [1782] = {18, 26, "DEV_MCU_CPSW0_RGMII1_TXC_I", "Input clock"},
1822         [1783] = {18, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"},
1823         [1784] = {18, 28, "DEV_MCU_CPSW0_CPTS_GENF0", "Output clock"},
1824         [1785] = {18, 29, "DEV_MCU_CPSW0_MDIO_MDCLK_O", "Output clock"},
1825         [1786] = {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"},
1826         [1787] = {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
1827         [1788] = {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
1828         [1789] = {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
1829         [1790] = {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
1830         [1791] = {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
1831         [1792] = {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
1832         [1793] = {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
1833         [1794] = {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
1834         [1795] = {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
1835         [1796] = {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
1836         [1797] = {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
1837         [1798] = {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
1838         [1799] = {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
1839         [1800] = {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"},
1840         [1801] = {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"},
1841         [1802] = {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
1842         [1803] = {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
1843         [1804] = {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
1844         [1805] = {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"},
1845         [1806] = {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
1846         [1807] = {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
1847         [1808] = {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
1848         [1809] = {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"},
1849         [1810] = {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
1850         [1811] = {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
1851         [1812] = {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"},
1852         [1813] = {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"},
1853         [1814] = {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"},
1854         [1815] = {46, 2, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
1855         [1816] = {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
1856         [1817] = {46, 4, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"},
1857         [1818] = {46, 5, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
1858         [1819] = {46, 6, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
1859         [1820] = {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
1860         [1821] = {46, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"},
1861         [1822] = {46, 9, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
1862         [1823] = {46, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"},
1863         [1824] = {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"},
1864         [1825] = {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"},
1865         [1826] = {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"},
1866         [1827] = {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"},
1867         [1828] = {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"},
1868         [1829] = {102, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"},
1869         [1830] = {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"},
1870         [1831] = {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"},
1871         [1832] = {102, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"},
1872         [1833] = {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
1873         [1834] = {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
1874         [1835] = {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
1875         [1836] = {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
1876         [1837] = {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
1877         [1838] = {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
1878         [1839] = {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
1879         [1840] = {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
1880         [1841] = {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
1881         [1842] = {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
1882         [1843] = {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"},
1883         [1844] = {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
1884         [1845] = {104, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
1885         [1846] = {104, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"},
1886         [1847] = {104, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"},
1887         [1848] = {104, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
1888         [1849] = {104, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
1889         [1850] = {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"},
1890         [1851] = {104, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"},
1891         [1852] = {104, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"},
1892         [1853] = {194, 0, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
1893         [1854] = {194, 1, "DEV_MCU_I2C0_PISCL", "Input clock"},
1894         [1855] = {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"},
1895         [1856] = {194, 3, "DEV_MCU_I2C0_PORSCL", "Output clock"},
1896         [1857] = {195, 0, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"},
1897         [1858] = {195, 1, "DEV_MCU_I2C1_PISCL", "Input clock"},
1898         [1859] = {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"},
1899         [1860] = {117, 0, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"},
1900         [1861] = {117, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"},
1901         [1862] = {117, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"},
1902         [1863] = {117, 3, "DEV_MCU_I3C0_I3C_SCL_DO", "Output clock"},
1903         [1864] = {118, 0, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"},
1904         [1865] = {118, 1, "DEV_MCU_I3C1_I3C_SCL_DI", "Input clock"},
1905         [1866] = {118, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"},
1906         [1867] = {118, 3, "DEV_MCU_I3C1_I3C_SCL_DO", "Output clock"},
1907         [1868] = {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
1908         [1869] = {172, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
1909         [1870] = {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1910         [1871] = {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1911         [1872] = {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1912         [1873] = {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
1913         [1874] = {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
1914         [1875] = {173, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
1915         [1876] = {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1916         [1877] = {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1917         [1878] = {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1918         [1879] = {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
1919         [1880] = {274, 0, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
1920         [1881] = {274, 1, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
1921         [1882] = {274, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
1922         [1883] = {275, 0, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
1923         [1884] = {275, 1, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
1924         [1885] = {275, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
1925         [1886] = {275, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
1926         [1887] = {275, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
1927         [1888] = {276, 0, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"},
1928         [1889] = {276, 1, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"},
1929         [1890] = {276, 2, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"},
1930         [1891] = {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
1931         [1892] = {237, 0, "DEV_MCU_NAVSS0_INTR_0_INTR_CLK", "Input clock"},
1932         [1893] = {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"},
1933         [1894] = {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"},
1934         [1895] = {234, 0, "DEV_MCU_NAVSS0_PROXY0_CLK_CLK", "Input clock"},
1935         [1896] = {235, 0, "DEV_MCU_NAVSS0_RINGACC0_SYS_CLK", "Input clock"},
1936         [1897] = {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
1937         [1898] = {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"},
1938         [1899] = {233, 0, "DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK", "Input clock"},
1939         [1900] = {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"},
1940         [1901] = {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
1941         [1902] = {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
1942         [1903] = {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
1943         [1904] = {250, 4, "DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
1944         [1905] = {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"},
1945         [1906] = {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
1946         [1907] = {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
1947         [1908] = {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
1948         [1909] = {251, 4, "DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
1949         [1910] = {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
1950         [1911] = {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
1951         [1912] = {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
1952         [1913] = {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
1953         [1914] = {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
1954         [1915] = {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
1955         [1916] = {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"},
1956         [1917] = {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"},
1957         [1918] = {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
1958         [1919] = {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
1959         [1920] = {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
1960         [1921] = {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
1961         [1922] = {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"},
1962         [1923] = {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"},
1963         [1924] = {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"},
1964         [1925] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
1965         [1926] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
1966         [1927] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1967         [1928] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1968         [1929] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1969         [1930] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1970         [1931] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1971         [1932] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1972         [1933] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1973         [1934] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
1974         [1935] = {35, 10, "DEV_MCU_TIMER0_TIMER_PWM", "Output clock"},
1975         [1936] = {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
1976         [1937] = {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
1977         [1938] = {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
1978         [1939] = {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
1979         [1940] = {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
1980         [1941] = {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
1981         [1942] = {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1982         [1943] = {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1983         [1944] = {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1984         [1945] = {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1985         [1946] = {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1986         [1947] = {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1987         [1948] = {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1988         [1949] = {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
1989         [1950] = {72, 10, "DEV_MCU_TIMER2_TIMER_PWM", "Output clock"},
1990         [1951] = {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
1991         [1952] = {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
1992         [1953] = {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
1993         [1954] = {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
1994         [1955] = {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"},
1995         [1956] = {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
1996         [1957] = {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
1997         [1958] = {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
1998         [1959] = {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
1999         [1960] = {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2000         [1961] = {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2001         [1962] = {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2002         [1963] = {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2003         [1964] = {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
2004         [1965] = {74, 10, "DEV_MCU_TIMER4_TIMER_PWM", "Output clock"},
2005         [1966] = {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"},
2006         [1967] = {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
2007         [1968] = {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
2008         [1969] = {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
2009         [1970] = {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"},
2010         [1971] = {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
2011         [1972] = {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2012         [1973] = {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2013         [1974] = {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2014         [1975] = {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2015         [1976] = {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2016         [1977] = {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2017         [1978] = {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2018         [1979] = {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
2019         [1980] = {76, 10, "DEV_MCU_TIMER6_TIMER_PWM", "Output clock"},
2020         [1981] = {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"},
2021         [1982] = {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
2022         [1983] = {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
2023         [1984] = {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
2024         [1985] = {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"},
2025         [1986] = {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
2026         [1987] = {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2027         [1988] = {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2028         [1989] = {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2029         [1990] = {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2030         [1991] = {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2031         [1992] = {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2032         [1993] = {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2033         [1994] = {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
2034         [1995] = {78, 10, "DEV_MCU_TIMER8_TIMER_PWM", "Output clock"},
2035         [1996] = {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"},
2036         [1997] = {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
2037         [1998] = {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
2038         [1999] = {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
2039         [2000] = {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"},
2040         [2001] = {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
2041         [2002] = {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
2042         [2003] = {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
2043         [2004] = {186, 0, "DEV_MLB0_MLBSS_MLB_CLK", "Input clock"},
2044         [2005] = {186, 1, "DEV_MLB0_MLBSS_SCLK_CLK", "Input clock"},
2045         [2006] = {186, 2, "DEV_MLB0_MLBSS_HCLK_CLK", "Input clock"},
2046         [2007] = {186, 3, "DEV_MLB0_MLBSS_PCLK_CLK", "Input clock"},
2047         [2008] = {186, 4, "DEV_MLB0_MLBSS_AMLB_CLK", "Input clock"},
2048         [2009] = {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"},
2049         [2010] = {91, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
2050         [2011] = {91, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2051         [2012] = {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2052         [2013] = {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2053         [2014] = {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
2054         [2015] = {91, 6, "DEV_MMCSD0_EMMCSS_IO_CLK", "Output clock"},
2055         [2016] = {92, 0, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
2056         [2017] = {92, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2057         [2018] = {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2058         [2019] = {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2059         [2020] = {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
2060         [2021] = {92, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
2061         [2022] = {92, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I", "Input clock"},
2062         [2023] = {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O", "Output clock"},
2063         [2024] = {93, 0, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"},
2064         [2025] = {93, 1, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2065         [2026] = {93, 2, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2066         [2027] = {93, 3, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2067         [2028] = {93, 4, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
2068         [2029] = {93, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"},
2069         [2030] = {93, 6, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I", "Input clock"},
2070         [2031] = {93, 7, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O", "Output clock"},
2071         [2032] = {199, 0, "DEV_NAVSS0_CPTS0_GENF3", "Output clock"},
2072         [2033] = {199, 1, "DEV_NAVSS0_CPTS0_GENF2", "Output clock"},
2073         [2034] = {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"},
2074         [2035] = {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"},
2075         [2036] = {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2076         [2037] = {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2077         [2038] = {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2078         [2039] = {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2079         [2040] = {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2080         [2041] = {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2081         [2042] = {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2082         [2043] = {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2083         [2044] = {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2084         [2045] = {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2085         [2046] = {201, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2086         [2047] = {201, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2087         [2048] = {201, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2088         [2049] = {201, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2089         [2050] = {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2090         [2051] = {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
2091         [2052] = {201, 18, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"},
2092         [2053] = {201, 19, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"},
2093         [2054] = {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"},
2094         [2055] = {206, 1, "DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK", "Input clock"},
2095         [2056] = {206, 2, "DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK", "Input clock"},
2096         [2057] = {206, 3, "DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK", "Input clock"},
2097         [2058] = {206, 4, "DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK", "Input clock"},
2098         [2059] = {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"},
2099         [2060] = {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"},
2100         [2061] = {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"},
2101         [2062] = {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"},
2102         [2063] = {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"},
2103         [2064] = {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"},
2104         [2065] = {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"},
2105         [2066] = {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"},
2106         [2067] = {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"},
2107         [2068] = {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"},
2108         [2069] = {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"},
2109         [2070] = {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"},
2110         [2071] = {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"},
2111         [2072] = {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"},
2112         [2073] = {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"},
2113         [2074] = {207, 0, "DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK", "Input clock"},
2114         [2075] = {208, 0, "DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK", "Input clock"},
2115         [2076] = {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"},
2116         [2077] = {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"},
2117         [2078] = {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"},
2118         [2079] = {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"},
2119         [2080] = {229, 0, "DEV_NAVSS0_TCU_0_CLK_CLK", "Input clock"},
2120         [2081] = {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"},
2121         [2082] = {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"},
2122         [2083] = {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"},
2123         [2084] = {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"},
2124         [2085] = {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
2125         [2086] = {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"},
2126         [2087] = {209, 0, "DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK", "Input clock"},
2127         [2088] = {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"},
2128         [2089] = {239, 0, "DEV_PCIE0_PCIE_LANE1_TXMCLK", "Input clock"},
2129         [2090] = {239, 1, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"},
2130         [2091] = {239, 2, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"},
2131         [2092] = {239, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2132         [2093] = {239, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2133         [2094] = {239, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2134         [2095] = {239, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2135         [2096] = {239, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2136         [2097] = {239, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2137         [2098] = {239, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2138         [2099] = {239, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2139         [2100] = {239, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2140         [2101] = {239, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2141         [2102] = {239, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2142         [2103] = {239, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2143         [2104] = {239, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2144         [2105] = {239, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2145         [2106] = {239, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2146         [2107] = {239, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2147         [2108] = {239, 19, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
2148         [2109] = {239, 20, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"},
2149         [2110] = {239, 21, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"},
2150         [2111] = {239, 22, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"},
2151         [2112] = {239, 23, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"},
2152         [2113] = {239, 24, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"},
2153         [2114] = {239, 25, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"},
2154         [2115] = {239, 26, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"},
2155         [2116] = {239, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"},
2156         [2117] = {239, 28, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"},
2157         [2118] = {239, 29, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"},
2158         [2119] = {239, 30, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"},
2159         [2120] = {240, 0, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"},
2160         [2121] = {240, 1, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"},
2161         [2122] = {240, 2, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"},
2162         [2123] = {240, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2163         [2124] = {240, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2164         [2125] = {240, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2165         [2126] = {240, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2166         [2127] = {240, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2167         [2128] = {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2168         [2129] = {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2169         [2130] = {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2170         [2131] = {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2171         [2132] = {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2172         [2133] = {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2173         [2134] = {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2174         [2135] = {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2175         [2136] = {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2176         [2137] = {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2177         [2138] = {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2178         [2139] = {240, 19, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
2179         [2140] = {240, 20, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"},
2180         [2141] = {240, 21, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"},
2181         [2142] = {240, 22, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"},
2182         [2143] = {240, 23, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"},
2183         [2144] = {240, 24, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"},
2184         [2145] = {240, 25, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"},
2185         [2146] = {240, 26, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"},
2186         [2147] = {240, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"},
2187         [2148] = {240, 28, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"},
2188         [2149] = {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"},
2189         [2150] = {240, 30, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"},
2190         [2151] = {241, 0, "DEV_PCIE2_PCIE_LANE1_TXMCLK", "Input clock"},
2191         [2152] = {241, 1, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"},
2192         [2153] = {241, 2, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"},
2193         [2154] = {241, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2194         [2155] = {241, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2195         [2156] = {241, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2196         [2157] = {241, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2197         [2158] = {241, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2198         [2159] = {241, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2199         [2160] = {241, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2200         [2161] = {241, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2201         [2162] = {241, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2202         [2163] = {241, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2203         [2164] = {241, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2204         [2165] = {241, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2205         [2166] = {241, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2206         [2167] = {241, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2207         [2168] = {241, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2208         [2169] = {241, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2209         [2170] = {241, 19, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
2210         [2171] = {241, 20, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"},
2211         [2172] = {241, 21, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"},
2212         [2173] = {241, 22, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"},
2213         [2174] = {241, 23, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"},
2214         [2175] = {241, 24, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"},
2215         [2176] = {241, 25, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"},
2216         [2177] = {241, 26, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"},
2217         [2178] = {241, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"},
2218         [2179] = {241, 28, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"},
2219         [2180] = {241, 29, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"},
2220         [2181] = {241, 30, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"},
2221         [2182] = {242, 0, "DEV_PCIE3_PCIE_LANE1_TXMCLK", "Input clock"},
2222         [2183] = {242, 1, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"},
2223         [2184] = {242, 2, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"},
2224         [2185] = {242, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
2225         [2186] = {242, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2226         [2187] = {242, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2227         [2188] = {242, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2228         [2189] = {242, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2229         [2190] = {242, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2230         [2191] = {242, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2231         [2192] = {242, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2232         [2193] = {242, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2233         [2194] = {242, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2234         [2195] = {242, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2235         [2196] = {242, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2236         [2197] = {242, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2237         [2198] = {242, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2238         [2199] = {242, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2239         [2200] = {242, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2240         [2201] = {242, 19, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
2241         [2202] = {242, 20, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"},
2242         [2203] = {242, 21, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"},
2243         [2204] = {242, 22, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"},
2244         [2205] = {242, 23, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"},
2245         [2206] = {242, 24, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"},
2246         [2207] = {242, 25, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"},
2247         [2208] = {242, 26, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"},
2248         [2209] = {242, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"},
2249         [2210] = {242, 28, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"},
2250         [2211] = {242, 29, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"},
2251         [2212] = {242, 30, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"},
2252         [2213] = {119, 0, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I", "Input clock"},
2253         [2214] = {119, 1, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"},
2254         [2215] = {119, 2, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I", "Input clock"},
2255         [2216] = {119, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"},
2256         [2217] = {119, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2257         [2218] = {119, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2258         [2219] = {119, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2259         [2220] = {119, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2260         [2221] = {119, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2261         [2222] = {119, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2262         [2223] = {119, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2263         [2224] = {119, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2264         [2225] = {119, 12, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2265         [2226] = {119, 13, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2266         [2227] = {119, 14, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2267         [2228] = {119, 15, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2268         [2229] = {119, 16, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2269         [2230] = {119, 17, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2270         [2231] = {119, 18, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2271         [2232] = {119, 19, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
2272         [2233] = {119, 20, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"},
2273         [2234] = {119, 21, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I", "Input clock"},
2274         [2235] = {119, 22, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"},
2275         [2236] = {119, 23, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I", "Input clock"},
2276         [2237] = {119, 24, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"},
2277         [2238] = {119, 25, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
2278         [2239] = {119, 26, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
2279         [2240] = {119, 27, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"},
2280         [2241] = {119, 28, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"},
2281         [2242] = {119, 29, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O", "Output clock"},
2282         [2243] = {119, 30, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O", "Output clock"},
2283         [2244] = {119, 31, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O", "Output clock"},
2284         [2245] = {120, 0, "DEV_PRU_ICSSG1_SERDES0_RXCLK", "Input muxed clock"},
2285         [2246] = {120, 1, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
2286         [2247] = {120, 2, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
2287         [2248] = {120, 3, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I", "Input clock"},
2288         [2249] = {120, 4, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"},
2289         [2250] = {120, 5, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I", "Input clock"},
2290         [2251] = {120, 6, "DEV_PRU_ICSSG1_SERDES0_RXFCLK", "Input muxed clock"},
2291         [2252] = {120, 7, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
2292         [2253] = {120, 8, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
2293         [2254] = {120, 9, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"},
2294         [2255] = {120, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2295         [2256] = {120, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2296         [2257] = {120, 12, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2297         [2258] = {120, 13, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2298         [2259] = {120, 14, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2299         [2260] = {120, 15, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2300         [2261] = {120, 16, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2301         [2262] = {120, 17, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2302         [2263] = {120, 18, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2303         [2264] = {120, 19, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2304         [2265] = {120, 20, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2305         [2266] = {120, 21, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2306         [2267] = {120, 22, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2307         [2268] = {120, 23, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2308         [2269] = {120, 24, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2309         [2270] = {120, 25, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
2310         [2271] = {120, 26, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"},
2311         [2272] = {120, 27, "DEV_PRU_ICSSG1_SERDES0_TXMCLK", "Input muxed clock"},
2312         [2273] = {120, 28, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
2313         [2274] = {120, 29, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
2314         [2275] = {120, 30, "DEV_PRU_ICSSG1_SERDES0_REFCLK", "Input muxed clock"},
2315         [2276] = {120, 31, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
2316         [2277] = {120, 32, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
2317         [2278] = {120, 33, "DEV_PRU_ICSSG1_SERDES1_RXFCLK", "Input muxed clock"},
2318         [2279] = {120, 34, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
2319         [2280] = {120, 35, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
2320         [2281] = {120, 36, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I", "Input clock"},
2321         [2282] = {120, 37, "DEV_PRU_ICSSG1_SERDES1_RXCLK", "Input muxed clock"},
2322         [2283] = {120, 38, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
2323         [2284] = {120, 39, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
2324         [2285] = {120, 40, "DEV_PRU_ICSSG1_SERDES1_TXFCLK", "Input muxed clock"},
2325         [2286] = {120, 41, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
2326         [2287] = {120, 42, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
2327         [2288] = {120, 43, "DEV_PRU_ICSSG1_SERDES1_TXMCLK", "Input muxed clock"},
2328         [2289] = {120, 44, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
2329         [2290] = {120, 45, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
2330         [2291] = {120, 46, "DEV_PRU_ICSSG1_SERDES0_TXFCLK", "Input muxed clock"},
2331         [2292] = {120, 47, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
2332         [2293] = {120, 48, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
2333         [2294] = {120, 49, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"},
2334         [2295] = {120, 50, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I", "Input clock"},
2335         [2296] = {120, 51, "DEV_PRU_ICSSG1_SERDES1_REFCLK", "Input muxed clock"},
2336         [2297] = {120, 52, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
2337         [2298] = {120, 53, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
2338         [2299] = {120, 54, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"},
2339         [2300] = {120, 55, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
2340         [2301] = {120, 56, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
2341         [2302] = {120, 57, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"},
2342         [2303] = {120, 58, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"},
2343         [2304] = {120, 59, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O", "Output clock"},
2344         [2305] = {120, 60, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O", "Output clock"},
2345         [2306] = {120, 61, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O", "Output clock"},
2346         [2307] = {120, 62, "DEV_PRU_ICSSG1_SERDES0_TXCLK", "Output clock"},
2347         [2308] = {120, 63, "DEV_PRU_ICSSG1_SERDES1_TXCLK", "Output clock"},
2348         [2309] = {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"},
2349         [2310] = {133, 1, "DEV_PSC0_CLK", "Input clock"},
2350         [2311] = {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"},
2351         [2312] = {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
2352         [2313] = {245, 2, "DEV_R5FSS0_CORE0_INTERFACE_PHASE", "Input clock"},
2353         [2314] = {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"},
2354         [2315] = {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
2355         [2316] = {246, 2, "DEV_R5FSS0_CORE1_INTERFACE_PHASE", "Input clock"},
2356         [2317] = {134, 0, "DEV_R5FSS0_INTROUTER0_INTR_CLK", "Input clock"},
2357         [2318] = {247, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"},
2358         [2319] = {247, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"},
2359         [2320] = {247, 2, "DEV_R5FSS1_CORE0_INTERFACE_PHASE", "Input clock"},
2360         [2321] = {248, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"},
2361         [2322] = {248, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"},
2362         [2323] = {248, 2, "DEV_R5FSS1_CORE1_INTERFACE_PHASE", "Input clock"},
2363         [2324] = {135, 0, "DEV_R5FSS1_INTROUTER0_INTR_CLK", "Input clock"},
2364         [2325] = {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"},
2365         [2326] = {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
2366         [2327] = {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2367         [2328] = {252, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2368         [2329] = {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2369         [2330] = {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2370         [2331] = {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2371         [2332] = {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2372         [2333] = {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2373         [2334] = {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"},
2374         [2335] = {253, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"},
2375         [2336] = {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
2376         [2337] = {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2377         [2338] = {253, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2378         [2339] = {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2379         [2340] = {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2380         [2341] = {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2381         [2342] = {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2382         [2343] = {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2383         [2344] = {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"},
2384         [2345] = {257, 0, "DEV_RTI15_VBUSP_CLK", "Input clock"},
2385         [2346] = {257, 1, "DEV_RTI15_RTI_CLK", "Input muxed clock"},
2386         [2347] = {257, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2387         [2348] = {257, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2388         [2349] = {257, 4, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2389         [2350] = {257, 5, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2390         [2351] = {257, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2391         [2352] = {257, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2392         [2353] = {257, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2393         [2354] = {257, 9, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"},
2394         [2355] = {256, 0, "DEV_RTI16_VBUSP_CLK", "Input clock"},
2395         [2356] = {256, 1, "DEV_RTI16_RTI_CLK", "Input muxed clock"},
2396         [2357] = {256, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2397         [2358] = {256, 3, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2398         [2359] = {256, 4, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2399         [2360] = {256, 5, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2400         [2361] = {256, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2401         [2362] = {256, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2402         [2363] = {256, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2403         [2364] = {256, 9, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"},
2404         [2365] = {254, 0, "DEV_RTI24_VBUSP_CLK", "Input clock"},
2405         [2366] = {254, 1, "DEV_RTI24_RTI_CLK", "Input muxed clock"},
2406         [2367] = {254, 2, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2407         [2368] = {254, 3, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2408         [2369] = {254, 4, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2409         [2370] = {254, 5, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2410         [2371] = {254, 6, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2411         [2372] = {254, 7, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2412         [2373] = {254, 8, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2413         [2374] = {254, 9, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI24_RTI_CLK"},
2414         [2375] = {255, 0, "DEV_RTI25_VBUSP_CLK", "Input clock"},
2415         [2376] = {255, 1, "DEV_RTI25_RTI_CLK", "Input muxed clock"},
2416         [2377] = {255, 2, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2417         [2378] = {255, 3, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2418         [2379] = {255, 4, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2419         [2380] = {255, 5, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2420         [2381] = {255, 6, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2421         [2382] = {255, 7, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2422         [2383] = {255, 8, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2423         [2384] = {255, 9, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI25_RTI_CLK"},
2424         [2385] = {258, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"},
2425         [2386] = {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"},
2426         [2387] = {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2427         [2388] = {258, 3, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2428         [2389] = {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2429         [2390] = {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2430         [2391] = {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2431         [2392] = {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2432         [2393] = {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2433         [2394] = {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"},
2434         [2395] = {259, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"},
2435         [2396] = {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"},
2436         [2397] = {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2437         [2398] = {259, 3, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2438         [2399] = {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2439         [2400] = {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2440         [2401] = {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2441         [2402] = {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2442         [2403] = {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2443         [2404] = {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"},
2444         [2405] = {260, 0, "DEV_RTI30_VBUSP_CLK", "Input clock"},
2445         [2406] = {260, 1, "DEV_RTI30_RTI_CLK", "Input muxed clock"},
2446         [2407] = {260, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2447         [2408] = {260, 3, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2448         [2409] = {260, 4, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2449         [2410] = {260, 5, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2450         [2411] = {260, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2451         [2412] = {260, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2452         [2413] = {260, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2453         [2414] = {260, 9, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"},
2454         [2415] = {261, 0, "DEV_RTI31_VBUSP_CLK", "Input clock"},
2455         [2416] = {261, 1, "DEV_RTI31_RTI_CLK", "Input muxed clock"},
2456         [2417] = {261, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2457         [2418] = {261, 3, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2458         [2419] = {261, 4, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2459         [2420] = {261, 5, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2460         [2421] = {261, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2461         [2422] = {261, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2462         [2423] = {261, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2463         [2424] = {261, 9, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"},
2464         [2425] = {264, 0, "DEV_SA2_UL0_X2_CLK", "Input clock"},
2465         [2426] = {264, 1, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"},
2466         [2427] = {264, 2, "DEV_SA2_UL0_X1_CLK", "Input clock"},
2467         [2428] = {297, 0, "DEV_SERDES_10G0_IP1_LN3_TXCLK", "Input clock"},
2468         [2429] = {297, 1, "DEV_SERDES_10G0_CLK", "Input clock"},
2469         [2430] = {297, 2, "DEV_SERDES_10G0_IP3_LN2_TXCLK", "Input clock"},
2470         [2431] = {297, 3, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input clock"},
2471         [2432] = {297, 4, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"},
2472         [2433] = {297, 5, "DEV_SERDES_10G0_IP3_LN1_TXCLK", "Input clock"},
2473         [2434] = {297, 6, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"},
2474         [2435] = {297, 7, "DEV_SERDES_10G0_IP3_LN0_TXCLK", "Input clock"},
2475         [2436] = {297, 8, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"},
2476         [2437] = {297, 9, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"},
2477         [2438] = {297, 10, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2478         [2439] = {297, 11, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2479         [2440] = {297, 12, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2480         [2441] = {297, 13, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
2481         [2442] = {297, 14, "DEV_SERDES_10G0_IP1_LN1_REFCLK", "Output clock"},
2482         [2443] = {297, 15, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"},
2483         [2444] = {297, 16, "DEV_SERDES_10G0_IP3_LN1_TXFCLK", "Output clock"},
2484         [2445] = {297, 17, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"},
2485         [2446] = {297, 18, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"},
2486         [2447] = {297, 19, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"},
2487         [2448] = {297, 20, "DEV_SERDES_10G0_IP3_LN1_TXMCLK", "Output clock"},
2488         [2449] = {297, 21, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"},
2489         [2450] = {297, 22, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"},
2490         [2451] = {297, 23, "DEV_SERDES_10G0_IP3_LN2_RXCLK", "Output clock"},
2491         [2452] = {297, 24, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"},
2492         [2453] = {297, 25, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"},
2493         [2454] = {297, 26, "DEV_SERDES_10G0_IP3_LN1_RXFCLK", "Output clock"},
2494         [2455] = {297, 27, "DEV_SERDES_10G0_IP3_LN0_RXFCLK", "Output clock"},
2495         [2456] = {297, 28, "DEV_SERDES_10G0_IP1_LN1_TXMCLK", "Output clock"},
2496         [2457] = {297, 29, "DEV_SERDES_10G0_IP1_LN1_RXFCLK", "Output clock"},
2497         [2458] = {297, 30, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"},
2498         [2459] = {297, 31, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"},
2499         [2460] = {297, 32, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"},
2500         [2461] = {297, 33, "DEV_SERDES_10G0_IP3_LN1_REFCLK", "Output clock"},
2501         [2462] = {297, 34, "DEV_SERDES_10G0_IP3_LN0_REFCLK", "Output clock"},
2502         [2463] = {297, 35, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"},
2503         [2464] = {297, 36, "DEV_SERDES_10G0_IP3_LN0_RXCLK", "Output clock"},
2504         [2465] = {297, 37, "DEV_SERDES_10G0_IP3_LN2_REFCLK", "Output clock"},
2505         [2466] = {297, 38, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"},
2506         [2467] = {297, 39, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"},
2507         [2468] = {297, 40, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"},
2508         [2469] = {297, 41, "DEV_SERDES_10G0_IP1_LN1_TXFCLK", "Output clock"},
2509         [2470] = {297, 42, "DEV_SERDES_10G0_IP3_LN0_TXFCLK", "Output clock"},
2510         [2471] = {297, 43, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"},
2511         [2472] = {297, 44, "DEV_SERDES_10G0_IP3_LN1_RXCLK", "Output clock"},
2512         [2473] = {297, 45, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"},
2513         [2474] = {297, 46, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"},
2514         [2475] = {297, 47, "DEV_SERDES_10G0_IP3_LN2_RXFCLK", "Output clock"},
2515         [2476] = {297, 48, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"},
2516         [2477] = {297, 49, "DEV_SERDES_10G0_IP3_LN2_TXMCLK", "Output clock"},
2517         [2478] = {297, 50, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"},
2518         [2479] = {297, 51, "DEV_SERDES_10G0_IP3_LN2_TXFCLK", "Output clock"},
2519         [2480] = {297, 52, "DEV_SERDES_10G0_IP3_LN0_TXMCLK", "Output clock"},
2520         [2481] = {297, 53, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"},
2521         [2482] = {297, 54, "DEV_SERDES_10G0_IP1_LN1_RXCLK", "Output clock"},
2522         [2483] = {292, 0, "DEV_SERDES_16G0_CORE_REF1_CLK", "Input muxed clock"},
2523         [2484] = {292, 1, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2524         [2485] = {292, 2, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2525         [2486] = {292, 3, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2526         [2487] = {292, 4, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
2527         [2488] = {292, 5, "DEV_SERDES_16G0_CLK", "Input clock"},
2528         [2489] = {292, 6, "DEV_SERDES_16G0_IP1_LN0_TXCLK", "Input clock"},
2529         [2490] = {292, 7, "DEV_SERDES_16G0_IP2_LN1_TXCLK", "Input clock"},
2530         [2491] = {292, 8, "DEV_SERDES_16G0_IP3_LN1_TXCLK", "Input clock"},
2531         [2492] = {292, 9, "DEV_SERDES_16G0_IP2_LN0_TXCLK", "Input clock"},
2532         [2493] = {292, 10, "DEV_SERDES_16G0_IP1_LN1_TXCLK", "Input clock"},
2533         [2494] = {292, 11, "DEV_SERDES_16G0_CORE_REF_CLK", "Input muxed clock"},
2534         [2495] = {292, 12, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2535         [2496] = {292, 13, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2536         [2497] = {292, 14, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2537         [2498] = {292, 15, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
2538         [2499] = {292, 16, "DEV_SERDES_16G0_IP2_LN0_TXFCLK", "Output clock"},
2539         [2500] = {292, 17, "DEV_SERDES_16G0_IP1_LN1_REFCLK", "Output clock"},
2540         [2501] = {292, 18, "DEV_SERDES_16G0_IP3_LN1_TXMCLK", "Output clock"},
2541         [2502] = {292, 19, "DEV_SERDES_16G0_IP3_LN1_TXFCLK", "Output clock"},
2542         [2503] = {292, 20, "DEV_SERDES_16G0_IP1_LN0_RXFCLK", "Output clock"},
2543         [2504] = {292, 21, "DEV_SERDES_16G0_IP2_LN1_REFCLK", "Output clock"},
2544         [2505] = {292, 22, "DEV_SERDES_16G0_IP2_LN1_TXFCLK", "Output clock"},
2545         [2506] = {292, 24, "DEV_SERDES_16G0_IP1_LN0_TXFCLK", "Output clock"},
2546         [2507] = {292, 25, "DEV_SERDES_16G0_IP3_LN1_RXFCLK", "Output clock"},
2547         [2508] = {292, 26, "DEV_SERDES_16G0_IP1_LN1_TXMCLK", "Output clock"},
2548         [2509] = {292, 27, "DEV_SERDES_16G0_IP1_LN1_RXFCLK", "Output clock"},
2549         [2510] = {292, 28, "DEV_SERDES_16G0_IP3_LN1_RXCLK", "Output clock"},
2550         [2511] = {292, 29, "DEV_SERDES_16G0_IP3_LN1_REFCLK", "Output clock"},
2551         [2512] = {292, 30, "DEV_SERDES_16G0_IP2_LN1_RXCLK", "Output clock"},
2552         [2513] = {292, 31, "DEV_SERDES_16G0_IP2_LN0_RXFCLK", "Output clock"},
2553         [2514] = {292, 32, "DEV_SERDES_16G0_IP1_LN0_RXCLK", "Output clock"},
2554         [2515] = {292, 33, "DEV_SERDES_16G0_REF_OUT_CLK", "Output clock"},
2555         [2516] = {292, 34, "DEV_SERDES_16G0_REF1_OUT_CLK", "Output clock"},
2556         [2517] = {292, 35, "DEV_SERDES_16G0_IP1_LN0_REFCLK", "Output clock"},
2557         [2518] = {292, 36, "DEV_SERDES_16G0_IP1_LN0_TXMCLK", "Output clock"},
2558         [2519] = {292, 37, "DEV_SERDES_16G0_IP2_LN1_RXFCLK", "Output clock"},
2559         [2520] = {292, 38, "DEV_SERDES_16G0_IP2_LN1_TXMCLK", "Output clock"},
2560         [2521] = {292, 39, "DEV_SERDES_16G0_IP2_LN0_REFCLK", "Output clock"},
2561         [2522] = {292, 40, "DEV_SERDES_16G0_IP2_LN0_TXMCLK", "Output clock"},
2562         [2523] = {292, 41, "DEV_SERDES_16G0_IP1_LN1_TXFCLK", "Output clock"},
2563         [2524] = {292, 42, "DEV_SERDES_16G0_IP2_LN0_RXCLK", "Output clock"},
2564         [2525] = {292, 43, "DEV_SERDES_16G0_IP1_LN1_RXCLK", "Output clock"},
2565         [2526] = {292, 49, "DEV_SERDES_16G0_CMN_REFCLK1_M", "Input clock"},
2566         [2527] = {292, 57, "DEV_SERDES_16G0_CMN_REFCLK1_P", "Input clock"},
2567         [2528] = {293, 0, "DEV_SERDES_16G1_CORE_REF1_CLK", "Input muxed clock"},
2568         [2529] = {293, 1, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2569         [2530] = {293, 2, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2570         [2531] = {293, 3, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2571         [2532] = {293, 4, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
2572         [2533] = {293, 5, "DEV_SERDES_16G1_CLK", "Input clock"},
2573         [2534] = {293, 6, "DEV_SERDES_16G1_IP1_LN0_TXCLK", "Input clock"},
2574         [2535] = {293, 7, "DEV_SERDES_16G1_IP2_LN1_TXCLK", "Input clock"},
2575         [2536] = {293, 8, "DEV_SERDES_16G1_IP4_LN1_TXCLK", "Input clock"},
2576         [2537] = {293, 9, "DEV_SERDES_16G1_IP4_LN0_TXCLK", "Input clock"},
2577         [2538] = {293, 10, "DEV_SERDES_16G1_IP3_LN1_TXCLK", "Input clock"},
2578         [2539] = {293, 11, "DEV_SERDES_16G1_IP2_LN0_TXCLK", "Input clock"},
2579         [2540] = {293, 12, "DEV_SERDES_16G1_IP1_LN1_TXCLK", "Input clock"},
2580         [2541] = {293, 13, "DEV_SERDES_16G1_CORE_REF_CLK", "Input muxed clock"},
2581         [2542] = {293, 14, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2582         [2543] = {293, 15, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2583         [2544] = {293, 16, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2584         [2545] = {293, 17, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
2585         [2546] = {293, 18, "DEV_SERDES_16G1_IP2_LN0_TXFCLK", "Output clock"},
2586         [2547] = {293, 19, "DEV_SERDES_16G1_IP1_LN1_REFCLK", "Output clock"},
2587         [2548] = {293, 20, "DEV_SERDES_16G1_IP4_LN1_RXFCLK", "Output clock"},
2588         [2549] = {293, 21, "DEV_SERDES_16G1_IP3_LN1_TXMCLK", "Output clock"},
2589         [2550] = {293, 22, "DEV_SERDES_16G1_IP3_LN1_TXFCLK", "Output clock"},
2590         [2551] = {293, 23, "DEV_SERDES_16G1_IP1_LN0_RXFCLK", "Output clock"},
2591         [2552] = {293, 24, "DEV_SERDES_16G1_IP2_LN1_REFCLK", "Output clock"},
2592         [2553] = {293, 25, "DEV_SERDES_16G1_IP2_LN1_TXFCLK", "Output clock"},
2593         [2554] = {293, 27, "DEV_SERDES_16G1_IP1_LN0_TXFCLK", "Output clock"},
2594         [2555] = {293, 28, "DEV_SERDES_16G1_IP3_LN1_RXFCLK", "Output clock"},
2595         [2556] = {293, 29, "DEV_SERDES_16G1_IP1_LN1_TXMCLK", "Output clock"},
2596         [2557] = {293, 30, "DEV_SERDES_16G1_IP1_LN1_RXFCLK", "Output clock"},
2597         [2558] = {293, 31, "DEV_SERDES_16G1_IP4_LN1_REFCLK", "Output clock"},
2598         [2559] = {293, 32, "DEV_SERDES_16G1_IP3_LN1_RXCLK", "Output clock"},
2599         [2560] = {293, 33, "DEV_SERDES_16G1_IP4_LN1_TXMCLK", "Output clock"},
2600         [2561] = {293, 34, "DEV_SERDES_16G1_IP3_LN1_REFCLK", "Output clock"},
2601         [2562] = {293, 35, "DEV_SERDES_16G1_IP4_LN0_REFCLK", "Output clock"},
2602         [2563] = {293, 36, "DEV_SERDES_16G1_IP2_LN1_RXCLK", "Output clock"},
2603         [2564] = {293, 37, "DEV_SERDES_16G1_IP2_LN0_RXFCLK", "Output clock"},
2604         [2565] = {293, 38, "DEV_SERDES_16G1_IP1_LN0_RXCLK", "Output clock"},
2605         [2566] = {293, 39, "DEV_SERDES_16G1_REF_OUT_CLK", "Output clock"},</