1 /*
2 * SoC Host Info
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_host_info j721e_host_info[] = {
39 [0] = {0, "DMSC", "Secure", "Device Management and Security Control"},
40 [1] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"},
41 [2] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"},
42 [3] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"},
43 [4] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"},
44 [5] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"},
45 [6] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"},
46 [7] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"},
47 [8] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"},
48 [9] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"},
49 [10] = {20, "C7X_0", "Secure", "C7x Context 0 on Main island"},
50 [11] = {21, "C7X_1", "Non Secure", "C7x context 1 on Main island"},
51 [12] = {25, "C6X_0_0", "Secure", "C6x_0 Context 0 on Main island"},
52 [13] = {26, "C6X_0_1", "Non Secure", "C6x_0 context 1 on Main island"},
53 [14] = {27, "C6X_1_0", "Secure", "C6x_1 Context 0 on Main island"},
54 [15] = {28, "C6X_1_1", "Non Secure", "C6x_1 context 1 on Main island"},
55 [16] = {30, "GPU_0", "Non Secure", "RGX context 0 on Main island"},
56 [17] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"},
57 [18] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"},
58 [19] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"},
59 [20] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"},
60 [21] = {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"},
61 [22] = {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"},
62 [23] = {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"},
63 [24] = {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on MCU island"},
64 [25] = {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"},
65 };