1 /*
2 * SoC Processors Info
3 *
4 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_processors_info j721e_processors_info[] = {
39 [0] = {202, 2, 0x20, "A72SS0_CORE0"},
40 [1] = {203, 0, 0x21, "A72SS0_CORE1"},
41 [2] = {142, 0, 0x03, "C66SS0_CORE0"},
42 [3] = {143, 0, 0x04, "C66SS1_CORE0"},
43 [4] = {15, 0, 0x30, "C71SS0"},
44 [5] = {250, 0, 0x01, "MCU_R5FSS0_CORE0"},
45 [6] = {251, 0, 0x02, "MCU_R5FSS0_CORE1"},
46 [7] = {245, 0, 0x06, "R5FSS0_CORE0"},
47 [8] = {246, 0, 0x07, "R5FSS0_CORE1"},
48 [9] = {247, 0, 0x08, "R5FSS1_CORE0"},
49 [10] = {248, 0, 0x09, "R5FSS1_CORE1"},
50 };