1 /*
2 * J721E Sec Proxy Info
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
35 #include <tisci.h>
36 #include <socinfo.h>
38 struct ti_sci_sec_proxy_info j721e_main_sp_info[] = {
39 [0] = {138, "read", 22, "DM", "nonsec_high_priority_rx"},
40 [1] = {137, "read", 67, "DM", "nonsec_low_priority_rx"},
41 [2] = {136, "read", 22, "DM", "nonsec_notify_resp_rx"},
42 [3] = {135, "write", 2, "DM", "nonsec_A72_2_notify_tx"},
43 [4] = {134, "write", 22, "DM", "nonsec_A72_2_response_tx"},
44 [5] = {133, "write", 2, "DM", "nonsec_A72_3_notify_tx"},
45 [6] = {132, "write", 7, "DM", "nonsec_A72_3_response_tx"},
46 [7] = {131, "write", 2, "DM", "nonsec_A72_4_notify_tx"},
47 [8] = {130, "write", 7, "DM", "nonsec_A72_4_response_tx"},
48 [9] = {129, "write", 2, "DM", "nonsec_C7X_1_notify_tx"},
49 [10] = {128, "write", 7, "DM", "nonsec_C7X_1_response_tx"},
50 [11] = {127, "write", 2, "DM", "nonsec_C6X_0_1_notify_tx"},
51 [12] = {126, "write", 7, "DM", "nonsec_C6X_0_1_response_tx"},
52 [13] = {125, "write", 2, "DM", "nonsec_C6X_1_1_notify_tx"},
53 [14] = {124, "write", 7, "DM", "nonsec_C6X_1_1_response_tx"},
54 [15] = {123, "write", 2, "DM", "nonsec_GPU_0_notify_tx"},
55 [16] = {122, "write", 7, "DM", "nonsec_GPU_0_response_tx"},
56 [17] = {121, "write", 2, "DM", "nonsec_MAIN_0_R5_0_notify_tx"},
57 [18] = {120, "write", 7, "DM", "nonsec_MAIN_0_R5_0_response_tx"},
58 [19] = {119, "write", 1, "DM", "nonsec_MAIN_0_R5_2_notify_tx"},
59 [20] = {118, "write", 2, "DM", "nonsec_MAIN_0_R5_2_response_tx"},
60 [21] = {117, "write", 2, "DM", "nonsec_MAIN_1_R5_0_notify_tx"},
61 [22] = {116, "write", 7, "DM", "nonsec_MAIN_1_R5_0_response_tx"},
62 [23] = {115, "write", 1, "DM", "nonsec_MAIN_1_R5_2_notify_tx"},
63 [24] = {114, "write", 2, "DM", "nonsec_MAIN_1_R5_2_response_tx"},
64 [25] = {113, "write", 2, "DM", "nonsec_ICSSG_0_notify_tx"},
65 [26] = {112, "write", 7, "DM", "nonsec_ICSSG_0_response_tx"},
66 [27] = {0, "read", 2, "A72_0", "notify"},
67 [28] = {1, "read", 30, "A72_0", "response"},
68 [29] = {2, "write", 10, "A72_0", "high_priority"},
69 [30] = {3, "write", 20, "A72_0", "low_priority"},
70 [31] = {4, "write", 2, "A72_0", "notify_resp"},
71 [32] = {5, "read", 2, "A72_1", "notify"},
72 [33] = {6, "read", 30, "A72_1", "response"},
73 [34] = {7, "write", 10, "A72_1", "high_priority"},
74 [35] = {8, "write", 20, "A72_1", "low_priority"},
75 [36] = {9, "write", 2, "A72_1", "notify_resp"},
76 [37] = {10, "read", 2, "A72_2", "notify"},
77 [38] = {11, "read", 22, "A72_2", "response"},
78 [39] = {12, "write", 2, "A72_2", "high_priority"},
79 [40] = {13, "write", 20, "A72_2", "low_priority"},
80 [41] = {14, "write", 2, "A72_2", "notify_resp"},
81 [42] = {15, "read", 2, "A72_3", "notify"},
82 [43] = {16, "read", 7, "A72_3", "response"},
83 [44] = {17, "write", 2, "A72_3", "high_priority"},
84 [45] = {18, "write", 5, "A72_3", "low_priority"},
85 [46] = {19, "write", 2, "A72_3", "notify_resp"},
86 [47] = {20, "read", 2, "A72_4", "notify"},
87 [48] = {21, "read", 7, "A72_4", "response"},
88 [49] = {22, "write", 2, "A72_4", "high_priority"},
89 [50] = {23, "write", 5, "A72_4", "low_priority"},
90 [51] = {24, "write", 2, "A72_4", "notify_resp"},
91 [52] = {25, "read", 2, "C7X_0", "notify"},
92 [53] = {26, "read", 7, "C7X_0", "response"},
93 [54] = {27, "write", 2, "C7X_0", "high_priority"},
94 [55] = {28, "write", 5, "C7X_0", "low_priority"},
95 [56] = {29, "write", 2, "C7X_0", "notify_resp"},
96 [57] = {30, "read", 2, "C7X_1", "notify"},
97 [58] = {31, "read", 7, "C7X_1", "response"},
98 [59] = {32, "write", 2, "C7X_1", "high_priority"},
99 [60] = {33, "write", 5, "C7X_1", "low_priority"},
100 [61] = {34, "write", 2, "C7X_1", "notify_resp"},
101 [62] = {35, "read", 2, "C6X_0_0", "notify"},
102 [63] = {36, "read", 7, "C6X_0_0", "response"},
103 [64] = {37, "write", 2, "C6X_0_0", "high_priority"},
104 [65] = {38, "write", 5, "C6X_0_0", "low_priority"},
105 [66] = {39, "write", 2, "C6X_0_0", "notify_resp"},
106 [67] = {40, "read", 2, "C6X_0_1", "notify"},
107 [68] = {41, "read", 7, "C6X_0_1", "response"},
108 [69] = {42, "write", 2, "C6X_0_1", "high_priority"},
109 [70] = {43, "write", 5, "C6X_0_1", "low_priority"},
110 [71] = {44, "write", 2, "C6X_0_1", "notify_resp"},
111 [72] = {45, "read", 2, "C6X_1_0", "notify"},
112 [73] = {46, "read", 7, "C6X_1_0", "response"},
113 [74] = {47, "write", 2, "C6X_1_0", "high_priority"},
114 [75] = {48, "write", 5, "C6X_1_0", "low_priority"},
115 [76] = {49, "write", 2, "C6X_1_0", "notify_resp"},
116 [77] = {50, "read", 2, "C6X_1_1", "notify"},
117 [78] = {51, "read", 7, "C6X_1_1", "response"},
118 [79] = {52, "write", 2, "C6X_1_1", "high_priority"},
119 [80] = {53, "write", 5, "C6X_1_1", "low_priority"},
120 [81] = {54, "write", 2, "C6X_1_1", "notify_resp"},
121 [82] = {55, "read", 2, "GPU_0", "notify"},
122 [83] = {56, "read", 7, "GPU_0", "response"},
123 [84] = {57, "write", 2, "GPU_0", "high_priority"},
124 [85] = {58, "write", 5, "GPU_0", "low_priority"},
125 [86] = {59, "write", 2, "GPU_0", "notify_resp"},
126 [87] = {60, "read", 2, "MAIN_0_R5_0", "notify"},
127 [88] = {61, "read", 7, "MAIN_0_R5_0", "response"},
128 [89] = {62, "write", 2, "MAIN_0_R5_0", "high_priority"},
129 [90] = {63, "write", 5, "MAIN_0_R5_0", "low_priority"},
130 [91] = {64, "write", 2, "MAIN_0_R5_0", "notify_resp"},
131 [92] = {65, "read", 2, "MAIN_0_R5_1", "notify"},
132 [93] = {66, "read", 7, "MAIN_0_R5_1", "response"},
133 [94] = {67, "write", 2, "MAIN_0_R5_1", "high_priority"},
134 [95] = {68, "write", 5, "MAIN_0_R5_1", "low_priority"},
135 [96] = {69, "write", 2, "MAIN_0_R5_1", "notify_resp"},
136 [97] = {70, "read", 1, "MAIN_0_R5_2", "notify"},
137 [98] = {71, "read", 2, "MAIN_0_R5_2", "response"},
138 [99] = {72, "write", 1, "MAIN_0_R5_2", "high_priority"},
139 [100] = {73, "write", 1, "MAIN_0_R5_2", "low_priority"},
140 [101] = {74, "write", 1, "MAIN_0_R5_2", "notify_resp"},
141 [102] = {75, "read", 1, "MAIN_0_R5_3", "notify"},
142 [103] = {76, "read", 2, "MAIN_0_R5_3", "response"},
143 [104] = {77, "write", 1, "MAIN_0_R5_3", "high_priority"},
144 [105] = {78, "write", 1, "MAIN_0_R5_3", "low_priority"},
145 [106] = {79, "write", 1, "MAIN_0_R5_3", "notify_resp"},
146 [107] = {80, "read", 2, "MAIN_1_R5_0", "notify"},
147 [108] = {81, "read", 7, "MAIN_1_R5_0", "response"},
148 [109] = {82, "write", 2, "MAIN_1_R5_0", "high_priority"},
149 [110] = {83, "write", 5, "MAIN_1_R5_0", "low_priority"},
150 [111] = {84, "write", 2, "MAIN_1_R5_0", "notify_resp"},
151 [112] = {85, "read", 2, "MAIN_1_R5_1", "notify"},
152 [113] = {86, "read", 7, "MAIN_1_R5_1", "response"},
153 [114] = {87, "write", 2, "MAIN_1_R5_1", "high_priority"},
154 [115] = {88, "write", 5, "MAIN_1_R5_1", "low_priority"},
155 [116] = {89, "write", 2, "MAIN_1_R5_1", "notify_resp"},
156 [117] = {90, "read", 1, "MAIN_1_R5_2", "notify"},
157 [118] = {91, "read", 2, "MAIN_1_R5_2", "response"},
158 [119] = {92, "write", 1, "MAIN_1_R5_2", "high_priority"},
159 [120] = {93, "write", 1, "MAIN_1_R5_2", "low_priority"},
160 [121] = {94, "write", 1, "MAIN_1_R5_2", "notify_resp"},
161 [122] = {95, "read", 1, "MAIN_1_R5_3", "notify"},
162 [123] = {96, "read", 2, "MAIN_1_R5_3", "response"},
163 [124] = {97, "write", 1, "MAIN_1_R5_3", "high_priority"},
164 [125] = {98, "write", 1, "MAIN_1_R5_3", "low_priority"},
165 [126] = {99, "write", 1, "MAIN_1_R5_3", "notify_resp"},
166 [127] = {100, "read", 2, "ICSSG_0", "notify"},
167 [128] = {101, "read", 7, "ICSSG_0", "response"},
168 [129] = {102, "write", 2, "ICSSG_0", "high_priority"},
169 [130] = {103, "write", 5, "ICSSG_0", "low_priority"},
170 [131] = {104, "write", 2, "ICSSG_0", "notify_resp"},
171 };
173 struct ti_sci_sec_proxy_info j721e_mcu_sp_info[] = {
174 [0] = {80, "read", 13, "DM", "nonsec_high_priority_rx"},
175 [1] = {79, "read", 13, "DM", "nonsec_low_priority_rx"},
176 [2] = {78, "read", 5, "DM", "nonsec_notify_resp_rx"},
177 [3] = {77, "write", 2, "DM", "nonsec_MCU_0_R5_0_notify_tx"},
178 [4] = {76, "write", 20, "DM", "nonsec_MCU_0_R5_0_response_tx"},
179 [5] = {75, "write", 1, "DM", "nonsec_MCU_0_R5_2_notify_tx"},
180 [6] = {74, "write", 2, "DM", "nonsec_MCU_0_R5_2_response_tx"},
181 [7] = {73, "write", 2, "DM", "nonsec_DMSC2DM_notify_tx"},
182 [8] = {72, "write", 4, "DM", "nonsec_DMSC2DM_response_tx"},
183 [9] = {0, "read", 2, "MCU_0_R5_0", "notify"},
184 [10] = {1, "read", 20, "MCU_0_R5_0", "response"},
185 [11] = {2, "write", 10, "MCU_0_R5_0", "high_priority"},
186 [12] = {3, "write", 10, "MCU_0_R5_0", "low_priority"},
187 [13] = {4, "write", 2, "MCU_0_R5_0", "notify_resp"},
188 [14] = {5, "read", 2, "MCU_0_R5_1", "notify"},
189 [15] = {6, "read", 20, "MCU_0_R5_1", "response"},
190 [16] = {7, "write", 10, "MCU_0_R5_1", "high_priority"},
191 [17] = {8, "write", 10, "MCU_0_R5_1", "low_priority"},
192 [18] = {9, "write", 2, "MCU_0_R5_1", "notify_resp"},
193 [19] = {10, "read", 1, "MCU_0_R5_2", "notify"},
194 [20] = {11, "read", 2, "MCU_0_R5_2", "response"},
195 [21] = {12, "write", 1, "MCU_0_R5_2", "high_priority"},
196 [22] = {13, "write", 1, "MCU_0_R5_2", "low_priority"},
197 [23] = {14, "write", 1, "MCU_0_R5_2", "notify_resp"},
198 [24] = {15, "read", 1, "MCU_0_R5_3", "notify"},
199 [25] = {16, "read", 2, "MCU_0_R5_3", "response"},
200 [26] = {17, "write", 1, "MCU_0_R5_3", "high_priority"},
201 [27] = {18, "write", 1, "MCU_0_R5_3", "low_priority"},
202 [28] = {19, "write", 1, "MCU_0_R5_3", "notify_resp"},
203 [29] = {20, "read", 2, "DM2DMSC", "notify"},
204 [30] = {21, "read", 4, "DM2DMSC", "response"},
205 [31] = {22, "write", 2, "DM2DMSC", "high_priority"},
206 [32] = {23, "write", 2, "DM2DMSC", "low_priority"},
207 [33] = {24, "write", 2, "DM2DMSC", "notify_resp"},
208 [34] = {25, "read", 2, "DMSC2DM", "notify"},
209 [35] = {26, "read", 4, "DMSC2DM", "response"},
210 [36] = {27, "write", 2, "DMSC2DM", "high_priority"},
211 [37] = {28, "write", 2, "DMSC2DM", "low_priority"},
212 [38] = {29, "write", 2, "DMSC2DM", "notify_resp"},
213 };