/* * AM65X Devices Info * * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include #include struct ti_sci_devices_info am65x_devices_info[] = { [0] = {0, "AM6_DEV_MCU_ADC0"}, [1] = {1, "AM6_DEV_MCU_ADC1"}, [2] = {2, "AM6_DEV_CAL0"}, [3] = {3, "AM6_DEV_CMPEVENT_INTRTR0"}, [4] = {5, "AM6_DEV_MCU_CPSW0"}, [5] = {6, "AM6_DEV_CPT2_AGGR0"}, [6] = {7, "AM6_DEV_MCU_CPT2_AGGR0"}, [7] = {8, "AM6_DEV_STM0"}, [8] = {9, "AM6_DEV_DCC0"}, [9] = {10, "AM6_DEV_DCC1"}, [10] = {11, "AM6_DEV_DCC2"}, [11] = {12, "AM6_DEV_DCC3"}, [12] = {13, "AM6_DEV_DCC4"}, [13] = {14, "AM6_DEV_DCC5"}, [14] = {15, "AM6_DEV_DCC6"}, [15] = {16, "AM6_DEV_DCC7"}, [16] = {17, "AM6_DEV_MCU_DCC0"}, [17] = {18, "AM6_DEV_MCU_DCC1"}, [18] = {19, "AM6_DEV_MCU_DCC2"}, [19] = {20, "AM6_DEV_DDRSS0"}, [20] = {21, "AM6_DEV_DEBUGSS_WRAP0"}, [21] = {22, "AM6_DEV_WKUP_DMSC0"}, [22] = {23, "AM6_DEV_TIMER0"}, [23] = {24, "AM6_DEV_TIMER1"}, [24] = {25, "AM6_DEV_TIMER10"}, [25] = {26, "AM6_DEV_TIMER11"}, [26] = {27, "AM6_DEV_TIMER2"}, [27] = {28, "AM6_DEV_TIMER3"}, [28] = {29, "AM6_DEV_TIMER4"}, [29] = {30, "AM6_DEV_TIMER5"}, [30] = {31, "AM6_DEV_TIMER6"}, [31] = {32, "AM6_DEV_TIMER7"}, [32] = {33, "AM6_DEV_TIMER8"}, [33] = {34, "AM6_DEV_TIMER9"}, [34] = {35, "AM6_DEV_MCU_TIMER0"}, [35] = {36, "AM6_DEV_MCU_TIMER1"}, [36] = {37, "AM6_DEV_MCU_TIMER2"}, [37] = {38, "AM6_DEV_MCU_TIMER3"}, [38] = {39, "AM6_DEV_ECAP0"}, [39] = {40, "AM6_DEV_EHRPWM0"}, [40] = {41, "AM6_DEV_EHRPWM1"}, [41] = {42, "AM6_DEV_EHRPWM2"}, [42] = {43, "AM6_DEV_EHRPWM3"}, [43] = {44, "AM6_DEV_EHRPWM4"}, [44] = {45, "AM6_DEV_EHRPWM5"}, [45] = {46, "AM6_DEV_ELM0"}, [46] = {47, "AM6_DEV_MMCSD0"}, [47] = {48, "AM6_DEV_MMCSD1"}, [48] = {49, "AM6_DEV_EQEP0"}, [49] = {50, "AM6_DEV_EQEP1"}, [50] = {51, "AM6_DEV_EQEP2"}, [51] = {52, "AM6_DEV_ESM0"}, [52] = {53, "AM6_DEV_MCU_ESM0"}, [53] = {54, "AM6_DEV_WKUP_ESM0"}, [54] = {56, "AM6_DEV_GIC0"}, [55] = {57, "AM6_DEV_GPIO0"}, [56] = {58, "AM6_DEV_GPIO1"}, [57] = {59, "AM6_DEV_WKUP_GPIO0"}, [58] = {60, "AM6_DEV_GPMC0"}, [59] = {61, "AM6_DEV_GTC0"}, [60] = {62, "AM6_DEV_PRU_ICSSG0"}, [61] = {63, "AM6_DEV_PRU_ICSSG1"}, [62] = {64, "AM6_DEV_PRU_ICSSG2"}, [63] = {65, "AM6_DEV_GPU0"}, [64] = {66, "AM6_DEV_CCDEBUGSS0"}, [65] = {67, "AM6_DEV_DSS0"}, [66] = {68, "AM6_DEV_DEBUGSS0"}, [67] = {69, "AM6_DEV_EFUSE0"}, [68] = {70, "AM6_DEV_PSC0"}, [69] = {71, "AM6_DEV_MCU_DEBUGSS0"}, [70] = {72, "AM6_DEV_MCU_EFUSE0"}, [71] = {73, "AM6_DEV_PBIST0"}, [72] = {74, "AM6_DEV_PBIST1"}, [73] = {75, "AM6_DEV_MCU_PBIST0"}, [74] = {76, "AM6_DEV_PLLCTRL0"}, [75] = {77, "AM6_DEV_WKUP_PLLCTRL0"}, [76] = {78, "AM6_DEV_MCU_ROM0"}, [77] = {79, "AM6_DEV_WKUP_PSC0"}, [78] = {80, "AM6_DEV_WKUP_VTM0"}, [79] = {81, "AM6_DEV_DEBUGSUSPENDRTR0"}, [80] = {82, "AM6_DEV_CBASS0"}, [81] = {83, "AM6_DEV_CBASS_DEBUG0"}, [82] = {84, "AM6_DEV_CBASS_FW0"}, [83] = {85, "AM6_DEV_CBASS_INFRA0"}, [84] = {86, "AM6_DEV_ECC_AGGR0"}, [85] = {87, "AM6_DEV_ECC_AGGR1"}, [86] = {88, "AM6_DEV_ECC_AGGR2"}, [87] = {89, "AM6_DEV_MCU_CBASS0"}, [88] = {90, "AM6_DEV_MCU_CBASS_DEBUG0"}, [89] = {91, "AM6_DEV_MCU_CBASS_FW0"}, [90] = {92, "AM6_DEV_MCU_ECC_AGGR0"}, [91] = {93, "AM6_DEV_MCU_ECC_AGGR1"}, [92] = {94, "AM6_DEV_WKUP_CBASS0"}, [93] = {95, "AM6_DEV_WKUP_ECC_AGGR0"}, [94] = {96, "AM6_DEV_WKUP_CBASS_FW0"}, [95] = {97, "AM6_DEV_MAIN2MCU_LVL_INTRTR0"}, [96] = {98, "AM6_DEV_MAIN2MCU_PLS_INTRTR0"}, [97] = {99, "AM6_DEV_CTRL_MMR0"}, [98] = {100, "AM6_DEV_GPIOMUX_INTRTR0"}, [99] = {101, "AM6_DEV_PLL_MMR0"}, [100] = {102, "AM6_DEV_MCU_MCAN0"}, [101] = {103, "AM6_DEV_MCU_MCAN1"}, [102] = {104, "AM6_DEV_MCASP0"}, [103] = {105, "AM6_DEV_MCASP1"}, [104] = {106, "AM6_DEV_MCASP2"}, [105] = {107, "AM6_DEV_MCU_CTRL_MMR0"}, [106] = {108, "AM6_DEV_MCU_PLL_MMR0"}, [107] = {109, "AM6_DEV_MCU_SEC_MMR0"}, [108] = {110, "AM6_DEV_I2C0"}, [109] = {111, "AM6_DEV_I2C1"}, [110] = {112, "AM6_DEV_I2C2"}, [111] = {113, "AM6_DEV_I2C3"}, [112] = {114, "AM6_DEV_MCU_I2C0"}, [113] = {115, "AM6_DEV_WKUP_I2C0"}, [114] = {116, "AM6_DEV_MCU_MSRAM0"}, [115] = {117, "AM6_DEV_DFTSS0"}, [116] = {118, "AM6_DEV_NAVSS0"}, [117] = {119, "AM6_DEV_MCU_NAVSS0"}, [118] = {120, "AM6_DEV_PCIE0"}, [119] = {121, "AM6_DEV_PCIE1"}, [120] = {122, "AM6_DEV_PDMA_DEBUG0"}, [121] = {123, "AM6_DEV_PDMA0"}, [122] = {124, "AM6_DEV_PDMA1"}, [123] = {125, "AM6_DEV_MCU_PDMA0"}, [124] = {126, "AM6_DEV_MCU_PDMA1"}, [125] = {127, "AM6_DEV_MCU_PSRAM0"}, [126] = {128, "AM6_DEV_PSRAMECC0"}, [127] = {129, "AM6_DEV_MCU_ARMSS0"}, [128] = {130, "AM6_DEV_RTI0"}, [129] = {131, "AM6_DEV_RTI1"}, [130] = {132, "AM6_DEV_RTI2"}, [131] = {133, "AM6_DEV_RTI3"}, [132] = {134, "AM6_DEV_MCU_RTI0"}, [133] = {135, "AM6_DEV_MCU_RTI1"}, [134] = {136, "AM6_DEV_SA2_UL0"}, [135] = {137, "AM6_DEV_MCSPI0"}, [136] = {138, "AM6_DEV_MCSPI1"}, [137] = {139, "AM6_DEV_MCSPI2"}, [138] = {140, "AM6_DEV_MCSPI3"}, [139] = {141, "AM6_DEV_MCSPI4"}, [140] = {142, "AM6_DEV_MCU_MCSPI0"}, [141] = {143, "AM6_DEV_MCU_MCSPI1"}, [142] = {144, "AM6_DEV_MCU_MCSPI2"}, [143] = {145, "AM6_DEV_TIMESYNC_INTRTR0"}, [144] = {146, "AM6_DEV_UART0"}, [145] = {147, "AM6_DEV_UART1"}, [146] = {148, "AM6_DEV_UART2"}, [147] = {149, "AM6_DEV_MCU_UART0"}, [148] = {150, "AM6_DEV_WKUP_UART0"}, [149] = {151, "AM6_DEV_USB3SS0"}, [150] = {152, "AM6_DEV_USB3SS1"}, [151] = {153, "AM6_DEV_SERDES0"}, [152] = {154, "AM6_DEV_SERDES1"}, [153] = {155, "AM6_DEV_WKUP_CTRL_MMR0"}, [154] = {156, "AM6_DEV_WKUP_GPIOMUX_INTRTR0"}, [155] = {157, "AM6_DEV_BOARD0"}, [156] = {159, "AM6_DEV_MCU_ARMSS0_CPU0"}, [157] = {161, "AM6_DEV_WKUP_DMSC0_CORTEX_M3_0"}, [158] = {163, "AM6_DEV_NAVSS0_CPTS0"}, [159] = {164, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0"}, [160] = {165, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1"}, [161] = {166, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2"}, [162] = {167, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3"}, [163] = {168, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4"}, [164] = {169, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5"}, [165] = {170, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6"}, [166] = {171, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7"}, [167] = {172, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8"}, [168] = {173, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9"}, [169] = {174, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10"}, [170] = {175, "AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11"}, [171] = {176, "AM6_DEV_NAVSS0_MCRC0"}, [172] = {177, "AM6_DEV_NAVSS0_PVU0"}, [173] = {178, "AM6_DEV_NAVSS0_PVU1"}, [174] = {179, "AM6_DEV_NAVSS0_UDMASS_INTA0"}, [175] = {180, "AM6_DEV_NAVSS0_MODSS_INTA0"}, [176] = {181, "AM6_DEV_NAVSS0_MODSS_INTA1"}, [177] = {182, "AM6_DEV_NAVSS0_INTR_ROUTER_0"}, [178] = {183, "AM6_DEV_NAVSS0_TIMER_MGR0"}, [179] = {184, "AM6_DEV_NAVSS0_TIMER_MGR1"}, [180] = {185, "AM6_DEV_NAVSS0_PROXY0"}, [181] = {187, "AM6_DEV_NAVSS0_RINGACC0"}, [182] = {188, "AM6_DEV_NAVSS0_UDMAP0"}, [183] = {189, "AM6_DEV_MCU_NAVSS0_INTR_AGGR_0"}, [184] = {190, "AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0"}, [185] = {191, "AM6_DEV_MCU_NAVSS0_PROXY0"}, [186] = {193, "AM6_DEV_MCU_NAVSS0_MCRC0"}, [187] = {194, "AM6_DEV_MCU_NAVSS0_UDMAP0"}, [188] = {195, "AM6_DEV_MCU_NAVSS0_RINGACC0"}, [189] = {196, "AM6_DEV_COMPUTE_CLUSTER_MSMC0"}, [190] = {197, "AM6_DEV_COMPUTE_CLUSTER_PBIST0"}, [191] = {198, "AM6_DEV_COMPUTE_CLUSTER_CPAC0"}, [192] = {199, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0"}, [193] = {200, "AM6_DEV_COMPUTE_CLUSTER_CPAC1"}, [194] = {201, "AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1"}, [195] = {202, "AM6_DEV_COMPUTE_CLUSTER_A53_0"}, [196] = {203, "AM6_DEV_COMPUTE_CLUSTER_A53_1"}, [197] = {204, "AM6_DEV_COMPUTE_CLUSTER_A53_2"}, [198] = {205, "AM6_DEV_COMPUTE_CLUSTER_A53_3"}, [199] = {206, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4"}, [200] = {207, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3"}, [201] = {208, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0"}, [202] = {209, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3"}, [203] = {210, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1"}, [204] = {211, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5"}, [205] = {212, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6"}, [206] = {213, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0"}, [207] = {214, "AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2"}, [208] = {215, "AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2"}, [209] = {216, "AM6_DEV_OLDI_TX_CORE_MAIN_0"}, [210] = {217, "AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0"}, [211] = {218, "AM6_DEV_ICEMELTER_WKUP_0"}, [212] = {219, "AM6_DEV_K3_LED_MAIN_0"}, [213] = {220, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU"}, [214] = {221, "AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP"}, [215] = {222, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU"}, [216] = {223, "AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN"}, [217] = {224, "AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC"}, [218] = {225, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA"}, [219] = {226, "AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA"}, [220] = {227, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU"}, [221] = {228, "AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN"}, [222] = {229, "AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU"}, [223] = {230, "AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU"}, [224] = {231, "AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0"}, [225] = {232, "AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0"}, [226] = {233, "AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0"}, [227] = {234, "AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0"}, [228] = {235, "AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0"}, [229] = {236, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU_VD"}, [230] = {237, "AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA_VD"}, [231] = {238, "AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC_VD"}, [232] = {239, "AM6_DEV_DUMMY_IP_LPSC_DMSC_VD"}, [233] = {240, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA_VD"}, [234] = {241, "AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_VD"}, [235] = {242, "AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP_VD"}, [236] = {243, "AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU_VD"}, [237] = {244, "AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA_VD"}, [238] = {245, "AM6_DEV_MCU_ARMSS0_CPU1"}, [239] = {246, "AM6_DEV_MCU_FSS0_FSAS_0"}, [240] = {247, "AM6_DEV_MCU_FSS0_HYPERBUS0"}, [241] = {248, "AM6_DEV_MCU_FSS0_OSPI_0"}, [242] = {249, "AM6_DEV_MCU_FSS0_OSPI_1"}, };