index 47684d22a2ad9527f11bd226a103ab6e1abe9ff2..1aee5ec4e9b7bc937b5cdd37e48a01de22273d7c 100644 (file)
/*
/*
- * SoC Host Info
+ * AM65X Hosts Info
*
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
#include <socinfo.h>
struct ti_sci_host_info am65x_host_info[] = {
#include <socinfo.h>
struct ti_sci_host_info am65x_host_info[] = {
- [0] = {0, "DMSC", "Secure", "Device Management and Security Control"},
- [1] = {3, "R5_0", "Non Secure", "Cortex R5 Context 0 on MCU island"},
- [2] = {4, "R5_1", "Secure", "Cortex R5 Context 1 on MCU island(Boot)"},
- [3] = {5, "R5_2", "Non Secure", "Cortex R5 Context 2 on MCU island"},
- [4] = {6, "R5_3", "Secure", "Cortex R5 Context 3 on MCU island"},
- [5] = {10, "A53_0", "Secure", "Cortex A53 context 0 on Main island"},
- [6] = {11, "A53_1", "Secure", "Cortex A53 context 1 on Main island"},
- [7] = {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island"},
- [8] = {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island"},
- [9] = {14, "A53_4", "Non Secure", "Cortex A53 context 4 on Main island"},
- [10] = {15, "A53_5", "Non Secure", "Cortex A53 context 5 on Main island"},
- [11] = {16, "A53_6", "Non Secure", "Cortex A53 context 6 on Main island"},
- [12] = {17, "A53_7", "Non Secure", "Cortex A53 context 7 on Main island"},
- [13] = {30, "GPU_0", "Non Secure", "SGX544 Context 0 on Main island"},
- [14] = {31, "GPU_1", "Non Secure", "SGX544 Context 1 on Main island"},
- [15] = {50, "ICSSG_0", "Non Secure", "ICSS Context 0 on Main island"},
- [16] = {51, "ICSSG_1", "Non Secure", "ICSS Context 1 on Main island"},
- [17] = {52, "ICSSG_2", "Non Secure", "ICSS Context 2 on Main island"},
-};
\ No newline at end of file
+ {0, "DMSC", "Secure", "Device Management and Security Control"},
+ {3, "R5_0", "Non Secure", "Cortex R5 Context 0 on MCU island"},
+ {4, "R5_1", "Secure", "Cortex R5 Context 1 on MCU island(Boot)"},
+ {5, "R5_2", "Non Secure", "Cortex R5 Context 2 on MCU island"},
+ {6, "R5_3", "Secure", "Cortex R5 Context 3 on MCU island"},
+ {10, "A53_0", "Secure", "Cortex A53 context 0 on Main island"},
+ {11, "A53_1", "Secure", "Cortex A53 context 1 on Main island"},
+ {12, "A53_2", "Non Secure", "Cortex A53 context 2 on Main island"},
+ {13, "A53_3", "Non Secure", "Cortex A53 context 3 on Main island"},
+ {14, "A53_4", "Non Secure", "Cortex A53 context 4 on Main island"},
+ {15, "A53_5", "Non Secure", "Cortex A53 context 5 on Main island"},
+ {16, "A53_6", "Non Secure", "Cortex A53 context 6 on Main island"},
+ {17, "A53_7", "Non Secure", "Cortex A53 context 7 on Main island"},
+ {30, "GPU_0", "Non Secure", "SGX544 Context 0 on Main island"},
+ {31, "GPU_1", "Non Secure", "SGX544 Context 1 on Main island"},
+ {50, "ICSSG_0", "Non Secure", "ICSS Context 0 on Main island"},
+ {51, "ICSSG_1", "Non Secure", "ICSS Context 1 on Main island"},
+ {52, "ICSSG_2", "Non Secure", "ICSS Context 2 on Main island"},
+};