common: cmd_dump: Gracefully handle ti_sci_cmd_get_clk_state() failure

[k3conf/k3conf.git] / soc / am65x_sr2 / am65x_sr2_clocks_info.c

diff --git a/soc/am65x_sr2/am65x_sr2_clocks_info.c b/soc/am65x_sr2/am65x_sr2_clocks_info.c
index 35491ce953618c0c27ae3aca3eae34d888eab99f..c4669e834b1cef851635096c047688059c9baae8 100644 (file)
--- a/soc/am65x_sr2/am65x_sr2_clocks_info.c
+++ b/soc/am65x_sr2/am65x_sr2_clocks_info.c
@@ -1,7 +1,7 @@
 /*
  * AM65X_SR2 Clocks Info
  *
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
@@ -36,1014 +36,1014 @@
 #include <socinfo.h>
 
 struct ti_sci_clocks_info am65x_sr2_clocks_info[] = {
-       [0] = {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"},
-       [1] = {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"},
-       [2] = {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [3] = {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [4] = {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [5] = {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
-       [6] = {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"},
-       [7] = {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"},
-       [8] = {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [9] = {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [10] = {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [11] = {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [12] = {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [13] = {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [14] = {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [15] = {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [16] = {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [17] = {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [18] = {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [19] = {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [20] = {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [21] = {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [22] = {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [23] = {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
-       [24] = {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"},
-       [25] = {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [26] = {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [27] = {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [28] = {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [29] = {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [30] = {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [31] = {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [32] = {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [33] = {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [34] = {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [35] = {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [36] = {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
-       [37] = {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"},
-       [38] = {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"},
-       [39] = {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"},
-       [40] = {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [41] = {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [42] = {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [43] = {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
-       [44] = {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"},
-       [45] = {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"},
-       [46] = {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
-       [47] = {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
-       [48] = {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"},
-       [49] = {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"},
-       [50] = {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"},
-       [51] = {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"},
-       [52] = {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"},
-       [53] = {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"},
-       [54] = {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"},
-       [55] = {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"},
-       [56] = {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"},
-       [57] = {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"},
-       [58] = {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"},
-       [59] = {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"},
-       [60] = {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"},
-       [61] = {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"},
-       [62] = {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"},
-       [63] = {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"},
-       [64] = {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"},
-       [65] = {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"},
-       [66] = {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"},
-       [67] = {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"},
-       [68] = {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"},
-       [69] = {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"},
-       [70] = {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"},
-       [71] = {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"},
-       [72] = {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"},
-       [73] = {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"},
-       [74] = {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"},
-       [75] = {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"},
-       [76] = {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"},
-       [77] = {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"},
-       [78] = {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"},
-       [79] = {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"},
-       [80] = {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"},
-       [81] = {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"},
-       [82] = {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
-       [83] = {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"},
-       [84] = {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"},
-       [85] = {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"},
-       [86] = {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"},
-       [87] = {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"},
-       [88] = {157, 119, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_OUT", "Output clock"},
-       [89] = {157, 120, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_OUT", "Output clock"},
-       [90] = {157, 121, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_OUT", "Output clock"},
-       [91] = {157, 122, "DEV_BOARD0_BUS_PRG1_RGMII2_TCLK_OUT", "Output clock"},
-       [92] = {157, 123, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_OUT", "Output clock"},
-       [93] = {157, 124, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_OUT", "Output clock"},
-       [94] = {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"},
-       [95] = {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"},
-       [96] = {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
-       [97] = {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [98] = {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
-       [99] = {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [100] = {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
-       [101] = {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [102] = {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"},
-       [103] = {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [104] = {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [105] = {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [106] = {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [107] = {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [108] = {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [109] = {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [110] = {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
-       [111] = {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
-       [112] = {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
-       [113] = {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"},
-       [114] = {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"},
-       [115] = {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"},
-       [116] = {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"},
-       [117] = {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"},
-       [118] = {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"},
-       [119] = {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"},
-       [120] = {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"},
-       [121] = {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"},
-       [122] = {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"},
-       [123] = {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"},
-       [124] = {197, 0, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVH_CLK4_CLK_CLK", "Input clock"},
-       [125] = {197, 1, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVP_CLK1_CLK_CLK", "Input clock"},
-       [126] = {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
-       [127] = {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"},
-       [128] = {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"},
-       [129] = {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"},
-       [130] = {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"},
-       [131] = {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"},
-       [132] = {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"},
-       [133] = {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"},
-       [134] = {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"},
-       [135] = {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"},
-       [136] = {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"},
-       [137] = {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"},
-       [138] = {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"},
-       [139] = {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"},
-       [140] = {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"},
-       [141] = {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"},
-       [142] = {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"},
-       [143] = {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"},
-       [144] = {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"},
-       [145] = {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"},
-       [146] = {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"},
-       [147] = {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
-       [148] = {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [149] = {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [150] = {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [151] = {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"},
-       [152] = {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [153] = {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [154] = {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [155] = {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [156] = {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [157] = {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [158] = {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [159] = {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [160] = {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [161] = {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [162] = {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [163] = {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [164] = {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"},
-       [165] = {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [166] = {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [167] = {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [168] = {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [169] = {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [170] = {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [171] = {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [172] = {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [173] = {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [174] = {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [175] = {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [176] = {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [177] = {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"},
-       [178] = {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [179] = {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [180] = {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [181] = {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [182] = {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [183] = {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [184] = {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [185] = {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [186] = {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [187] = {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [188] = {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [189] = {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [190] = {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"},
-       [191] = {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [192] = {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [193] = {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [194] = {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [195] = {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [196] = {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [197] = {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [198] = {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [199] = {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [200] = {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [201] = {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [202] = {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"},
-       [203] = {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [204] = {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [205] = {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [206] = {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [207] = {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [208] = {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [209] = {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [210] = {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [211] = {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [212] = {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [213] = {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [214] = {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"},
-       [215] = {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [216] = {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [217] = {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [218] = {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [219] = {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [220] = {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [221] = {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [222] = {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [223] = {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [224] = {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [225] = {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [226] = {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [227] = {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"},
-       [228] = {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [229] = {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [230] = {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [231] = {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [232] = {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [233] = {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [234] = {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [235] = {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [236] = {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [237] = {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [238] = {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [239] = {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [240] = {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"},
-       [241] = {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [242] = {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [243] = {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [244] = {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [245] = {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [246] = {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [247] = {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [248] = {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [249] = {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"},
-       [250] = {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"},
-       [251] = {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [252] = {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"},
-       [253] = {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [254] = {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [255] = {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"},
-       [256] = {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [257] = {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [258] = {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
-       [259] = {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
-       [260] = {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"},
-       [261] = {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
-       [262] = {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
-       [263] = {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"},
-       [264] = {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
-       [265] = {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
-       [266] = {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
-       [267] = {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
-       [268] = {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"},
-       [269] = {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"},
-       [270] = {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"},
-       [271] = {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"},
-       [272] = {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"},
-       [273] = {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"},
-       [274] = {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"},
-       [275] = {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"},
-       [276] = {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"},
-       [277] = {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
-       [278] = {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
-       [279] = {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
-       [280] = {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"},
-       [281] = {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"},
-       [282] = {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"},
-       [283] = {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
-       [284] = {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
-       [285] = {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"},
-       [286] = {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"},
-       [287] = {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"},
-       [288] = {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"},
-       [289] = {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"},
-       [290] = {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"},
-       [291] = {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"},
-       [292] = {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"},
-       [293] = {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"},
-       [294] = {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"},
-       [295] = {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"},
-       [296] = {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"},
-       [297] = {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"},
-       [298] = {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"},
-       [299] = {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"},
-       [300] = {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"},
-       [301] = {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
-       [302] = {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"},
-       [303] = {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [304] = {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [305] = {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [306] = {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
-       [307] = {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"},
-       [308] = {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"},
-       [309] = {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"},
-       [310] = {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"},
-       [311] = {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"},
-       [312] = {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"},
-       [313] = {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"},
-       [314] = {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
-       [315] = {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"},
-       [316] = {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
-       [317] = {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"},
-       [318] = {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"},
-       [319] = {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [320] = {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [321] = {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [322] = {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [323] = {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [324] = {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [325] = {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [326] = {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
-       [327] = {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"},
-       [328] = {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"},
-       [329] = {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"},
-       [330] = {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"},
-       [331] = {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"},
-       [332] = {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"},
-       [333] = {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"},
-       [334] = {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"},
-       [335] = {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"},
-       [336] = {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"},
-       [337] = {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"},
-       [338] = {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"},
-       [339] = {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [340] = {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [341] = {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [342] = {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [343] = {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [344] = {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [345] = {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [346] = {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
-       [347] = {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"},
-       [348] = {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"},
-       [349] = {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [350] = {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [351] = {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [352] = {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [353] = {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [354] = {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [355] = {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [356] = {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
-       [357] = {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"},
-       [358] = {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"},
-       [359] = {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [360] = {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [361] = {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [362] = {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [363] = {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [364] = {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [365] = {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [366] = {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
-       [367] = {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"},
-       [368] = {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [369] = {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
-       [370] = {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
-       [371] = {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [372] = {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [373] = {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
-       [374] = {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
-       [375] = {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [376] = {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [377] = {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
-       [378] = {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
-       [379] = {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [380] = {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [381] = {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"},
-       [382] = {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"},
-       [383] = {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [384] = {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"},
-       [385] = {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"},
-       [386] = {141, 2, "DEV_MCSPI4_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [387] = {141, 3, "DEV_MCSPI4_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [388] = {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"},
-       [389] = {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"},
-       [390] = {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"},
-       [391] = {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [392] = {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [393] = {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [394] = {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
-       [395] = {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"},
-       [396] = {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"},
-       [397] = {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"},
-       [398] = {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [399] = {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [400] = {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [401] = {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
-       [402] = {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"},
-       [403] = {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"},
-       [404] = {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"},
-       [405] = {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"},
-       [406] = {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
-       [407] = {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
-       [408] = {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"},
-       [409] = {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"},
-       [410] = {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"},
-       [411] = {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"},
-       [412] = {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
-       [413] = {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
-       [414] = {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"},
-       [415] = {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
-       [416] = {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
-       [417] = {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
-       [418] = {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
-       [419] = {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
-       [420] = {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"},
-       [421] = {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [422] = {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"},
-       [423] = {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"},
-       [424] = {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
-       [425] = {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [426] = {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"},
-       [427] = {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
-       [428] = {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
-       [429] = {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"},
-       [430] = {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"},
-       [431] = {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
-       [432] = {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
-       [433] = {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [434] = {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [435] = {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [436] = {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [437] = {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"},
-       [438] = {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [439] = {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [440] = {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [441] = {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [442] = {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [443] = {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [444] = {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [445] = {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [446] = {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [447] = {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [448] = {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [449] = {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [450] = {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"},
-       [451] = {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [452] = {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [453] = {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [454] = {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [455] = {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [456] = {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [457] = {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [458] = {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [459] = {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
-       [460] = {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
-       [461] = {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
-       [462] = {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
-       [463] = {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"},
-       [464] = {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
-       [465] = {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
-       [466] = {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
-       [467] = {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
-       [468] = {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
-       [469] = {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
-       [470] = {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
-       [471] = {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
-       [472] = {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
-       [473] = {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
-       [474] = {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
-       [475] = {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
-       [476] = {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
-       [477] = {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
-       [478] = {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
-       [479] = {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
-       [480] = {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
-       [481] = {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"},
-       [482] = {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"},
-       [483] = {247, 0, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"},
-       [484] = {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"},
-       [485] = {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"},
-       [486] = {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"},
-       [487] = {248, 0, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK", "Input muxed clock"},
-       [488] = {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"},
-       [489] = {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"},
-       [490] = {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK", "Input muxed clock"},
-       [491] = {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"},
-       [492] = {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"},
-       [493] = {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_PCLK_CLK", "Input clock"},
-       [494] = {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_DQS_CLK", "Input clock"},
-       [495] = {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_HCLK_CLK", "Input clock"},
-       [496] = {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_OCLK_CLK", "Output clock"},
-       [497] = {249, 0, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_PCLK_CLK", "Input clock"},
-       [498] = {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK", "Input muxed clock"},
-       [499] = {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"},
-       [500] = {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"},
-       [501] = {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_HCLK_CLK", "Input clock"},
-       [502] = {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_DQS_CLK", "Input clock"},
-       [503] = {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK", "Input muxed clock"},
-       [504] = {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"},
-       [505] = {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"},
-       [506] = {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_OCLK_CLK", "Output clock"},
-       [507] = {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"},
-       [508] = {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"},
-       [509] = {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [510] = {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [511] = {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [512] = {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [513] = {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
-       [514] = {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"},
-       [515] = {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
-       [516] = {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [517] = {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [518] = {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [519] = {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
-       [520] = {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"},
-       [521] = {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [522] = {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
-       [523] = {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
-       [524] = {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [525] = {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [526] = {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
-       [527] = {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
-       [528] = {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [529] = {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
-       [530] = {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
-       [531] = {144, 2, "DEV_MCU_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
-       [532] = {144, 3, "DEV_MCU_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
-       [533] = {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"},
-       [534] = {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"},
-       [535] = {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"},
-       [536] = {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
-       [537] = {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"},
-       [538] = {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"},
-       [539] = {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"},
-       [540] = {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"},
-       [541] = {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"},
-       [542] = {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"},
-       [543] = {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
-       [544] = {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"},
-       [545] = {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"},
-       [546] = {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"},
-       [547] = {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [548] = {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [549] = {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [550] = {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
-       [551] = {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"},
-       [552] = {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"},
-       [553] = {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [554] = {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [555] = {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [556] = {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
-       [557] = {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"},
-       [558] = {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"},
-       [559] = {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [560] = {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [561] = {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [562] = {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [563] = {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [564] = {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [565] = {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [566] = {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [567] = {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [568] = {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [569] = {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [570] = {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [571] = {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [572] = {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [573] = {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [574] = {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [575] = {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [576] = {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [577] = {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [578] = {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [579] = {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [580] = {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [581] = {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [582] = {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [583] = {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [584] = {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [585] = {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [586] = {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [587] = {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [588] = {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [589] = {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [590] = {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [591] = {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [592] = {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [593] = {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [594] = {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [595] = {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"},
-       [596] = {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
-       [597] = {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
-       [598] = {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"},
-       [599] = {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
-       [600] = {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
-       [601] = {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
-       [602] = {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
-       [603] = {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"},
-       [604] = {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"},
-       [605] = {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
-       [606] = {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"},
-       [607] = {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
-       [608] = {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
-       [609] = {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
-       [610] = {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"},
-       [611] = {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"},
-       [612] = {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
-       [613] = {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"},
-       [614] = {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"},
-       [615] = {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
-       [616] = {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"},
-       [617] = {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"},
-       [618] = {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"},
-       [619] = {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"},
-       [620] = {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"},
-       [621] = {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"},
-       [622] = {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"},
-       [623] = {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"},
-       [624] = {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"},
-       [625] = {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
-       [626] = {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"},
-       [627] = {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
-       [628] = {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"},
-       [629] = {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
-       [630] = {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
-       [631] = {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
-       [632] = {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
-       [633] = {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"},
-       [634] = {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"},
-       [635] = {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
-       [636] = {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"},
-       [637] = {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
-       [638] = {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"},
-       [639] = {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
-       [640] = {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
-       [641] = {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
-       [642] = {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
-       [643] = {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"},
-       [644] = {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"},
-       [645] = {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"},
-       [646] = {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"},
-       [647] = {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
-       [648] = {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
-       [649] = {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"},
-       [650] = {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
-       [651] = {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
-       [652] = {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
-       [653] = {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
-       [654] = {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
-       [655] = {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
-       [656] = {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"},
-       [657] = {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"},
-       [658] = {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
-       [659] = {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
-       [660] = {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [661] = {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [662] = {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"},
-       [663] = {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [664] = {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [665] = {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [666] = {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [667] = {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [668] = {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [669] = {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [670] = {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
-       [671] = {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"},
-       [672] = {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
-       [673] = {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
-       [674] = {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"},
-       [675] = {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
-       [676] = {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
-       [677] = {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"},
-       [678] = {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"},
-       [679] = {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
-       [680] = {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
-       [681] = {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [682] = {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [683] = {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"},
-       [684] = {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [685] = {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [686] = {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [687] = {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [688] = {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [689] = {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [690] = {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [691] = {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
-       [692] = {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"},
-       [693] = {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
-       [694] = {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
-       [695] = {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"},
-       [696] = {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
-       [697] = {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
-       [698] = {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"},
-       [699] = {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"},
-       [700] = {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
-       [701] = {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
-       [702] = {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"},
-       [703] = {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"},
-       [704] = {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"},
-       [705] = {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [706] = {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [707] = {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [708] = {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [709] = {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [710] = {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [711] = {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [712] = {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
-       [713] = {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"},
-       [714] = {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
-       [715] = {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
-       [716] = {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"},
-       [717] = {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"},
-       [718] = {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"},
-       [719] = {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"},
-       [720] = {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"},
-       [721] = {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"},
-       [722] = {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [723] = {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [724] = {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [725] = {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [726] = {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [727] = {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [728] = {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [729] = {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
-       [730] = {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"},
-       [731] = {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"},
-       [732] = {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [733] = {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [734] = {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [735] = {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [736] = {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [737] = {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [738] = {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [739] = {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
-       [740] = {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"},
-       [741] = {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"},
-       [742] = {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [743] = {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [744] = {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [745] = {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [746] = {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [747] = {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [748] = {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [749] = {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
-       [750] = {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"},
-       [751] = {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"},
-       [752] = {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [753] = {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [754] = {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [755] = {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [756] = {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [757] = {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [758] = {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [759] = {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
-       [760] = {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"},
-       [761] = {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"},
-       [762] = {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"},
-       [763] = {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"},
-       [764] = {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"},
-       [765] = {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"},
-       [766] = {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"},
-       [767] = {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"},
-       [768] = {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [769] = {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [770] = {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [771] = {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
-       [772] = {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"},
-       [773] = {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"},
-       [774] = {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"},
-       [775] = {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"},
-       [776] = {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"},
-       [777] = {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"},
-       [778] = {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"},
-       [779] = {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [780] = {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [781] = {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [782] = {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
-       [783] = {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"},
-       [784] = {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"},
-       [785] = {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"},
-       [786] = {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"},
-       [787] = {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"},
-       [788] = {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [789] = {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [790] = {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [791] = {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [792] = {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [793] = {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [794] = {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [795] = {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [796] = {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [797] = {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [798] = {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [799] = {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [800] = {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
-       [801] = {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [802] = {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [803] = {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [804] = {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [805] = {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [806] = {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [807] = {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [808] = {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [809] = {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [810] = {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [811] = {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [812] = {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [813] = {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [814] = {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
-       [815] = {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [816] = {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [817] = {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [818] = {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [819] = {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [820] = {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [821] = {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [822] = {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [823] = {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [824] = {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [825] = {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [826] = {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [827] = {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [828] = {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
-       [829] = {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [830] = {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [831] = {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [832] = {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [833] = {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [834] = {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [835] = {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [836] = {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [837] = {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [838] = {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [839] = {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [840] = {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [841] = {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [842] = {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
-       [843] = {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [844] = {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [845] = {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [846] = {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [847] = {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [848] = {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [849] = {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [850] = {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [851] = {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [852] = {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [853] = {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [854] = {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [855] = {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [856] = {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
-       [857] = {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [858] = {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [859] = {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [860] = {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [861] = {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [862] = {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [863] = {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [864] = {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [865] = {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [866] = {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [867] = {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [868] = {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [869] = {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [870] = {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
-       [871] = {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [872] = {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [873] = {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [874] = {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [875] = {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [876] = {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [877] = {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [878] = {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [879] = {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [880] = {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [881] = {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [882] = {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [883] = {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [884] = {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
-       [885] = {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [886] = {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [887] = {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [888] = {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [889] = {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [890] = {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [891] = {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [892] = {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [893] = {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [894] = {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [895] = {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [896] = {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [897] = {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [898] = {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
-       [899] = {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [900] = {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [901] = {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [902] = {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [903] = {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [904] = {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [905] = {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [906] = {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [907] = {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [908] = {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [909] = {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [910] = {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [911] = {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [912] = {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
-       [913] = {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [914] = {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [915] = {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [916] = {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [917] = {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [918] = {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [919] = {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [920] = {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [921] = {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [922] = {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [923] = {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [924] = {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [925] = {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [926] = {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
-       [927] = {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [928] = {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [929] = {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [930] = {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [931] = {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [932] = {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [933] = {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [934] = {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [935] = {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [936] = {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [937] = {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [938] = {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [939] = {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [940] = {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
-       [941] = {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [942] = {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
-       [943] = {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [944] = {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [945] = {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [946] = {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [947] = {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [948] = {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [949] = {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [950] = {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [951] = {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [952] = {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [953] = {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [954] = {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
-       [955] = {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"},
-       [956] = {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"},
-       [957] = {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"},
-       [958] = {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"},
-       [959] = {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"},
-       [960] = {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"},
-       [961] = {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"},
-       [962] = {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"},
-       [963] = {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"},
-       [964] = {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
-       [965] = {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"},
-       [966] = {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
-       [967] = {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
-       [968] = {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"},
-       [969] = {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"},
-       [970] = {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"},
-       [971] = {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
-       [972] = {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
-       [973] = {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"},
-       [974] = {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"},
-       [975] = {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
-       [976] = {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"},
-       [977] = {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
-       [978] = {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
-       [979] = {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"},
-       [980] = {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"},
-       [981] = {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"},
-       [982] = {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"},
-       [983] = {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
-       [984] = {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"},
-       [985] = {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
-       [986] = {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
-       [987] = {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
-       [988] = {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"},
-       [989] = {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"},
-       [990] = {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [991] = {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [992] = {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [993] = {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
-       [994] = {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
-       [995] = {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"},
-       [996] = {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"},
-       [997] = {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
-       [998] = {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
-       [999] = {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
-       [1000] = {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
-       [1001] = {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"},
-       [1002] = {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"},
-       [1003] = {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"},
-       [1004] = {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"},
-       [1005] = {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
-       [1006] = {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
-       [1007] = {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"},
-       [1008] = {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"},
-       [1009] = {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"},
+       {157, 5, "DEV_BOARD0_BUS_MCU_OSPI1CLK_IN", "Input clock"},
+       {157, 7, "DEV_BOARD0_BUS_REFCLK1P_IN", "Input muxed clock"},
+       {157, 8, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       {157, 9, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       {157, 10, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       {157, 11, "DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK1P_IN"},
+       {157, 12, "DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN", "Input clock"},
+       {157, 13, "DEV_BOARD0_BUS_MCU_OBSCLK_IN", "Input clock"},
+       {157, 14, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 15, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 16, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 17, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 18, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 19, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 20, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 21, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 22, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 23, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 24, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 25, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 26, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 27, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 28, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 29, "DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_MCU_OBSCLK_IN"},
+       {157, 36, "DEV_BOARD0_BUS_OBSCLK_IN", "Input clock"},
+       {157, 37, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 38, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 39, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 40, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 41, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 42, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 43, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 44, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 45, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 46, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 47, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 48, "DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_OBSCLK_IN"},
+       {157, 54, "DEV_BOARD0_BUS_MCU_OSPI0CLK_IN", "Input clock"},
+       {157, 55, "DEV_BOARD0_BUS_DSS0PCLK_IN", "Input clock"},
+       {157, 58, "DEV_BOARD0_BUS_REFCLK0P_IN", "Input muxed clock"},
+       {157, 59, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       {157, 60, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       {157, 61, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       {157, 62, "DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_BOARD0_BUS_REFCLK0P_IN"},
+       {157, 68, "DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN", "Input clock"},
+       {157, 69, "DEV_BOARD0_BUS_MCU_CLKOUT_IN", "Input muxed clock"},
+       {157, 70, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
+       {157, 71, "DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10", "Parent input clock option to DEV_BOARD0_BUS_MCU_CLKOUT_IN"},
+       {157, 73, "DEV_BOARD0_BUS_SYSCLKOUT_IN", "Input clock"},
+       {157, 74, "DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN", "Input clock"},
+       {157, 75, "DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT", "Output clock"},
+       {157, 76, "DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT", "Output clock"},
+       {157, 77, "DEV_BOARD0_BUS_GPMCCLK_OUT", "Output clock"},
+       {157, 78, "DEV_BOARD0_BUS_MCASP2AHCLKX_OUT", "Output clock"},
+       {157, 79, "DEV_BOARD0_BUS_MCASP2AHCLKR_OUT", "Output clock"},
+       {157, 80, "DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT", "Output clock"},
+       {157, 81, "DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT", "Output clock"},
+       {157, 82, "DEV_BOARD0_BUS_MCASP0ACLKR_OUT", "Output clock"},
+       {157, 83, "DEV_BOARD0_BUS_MCASP0ACLKX_OUT", "Output clock"},
+       {157, 84, "DEV_BOARD0_BUS_EXT_REFCLK1_OUT", "Output clock"},
+       {157, 85, "DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT", "Output clock"},
+       {157, 86, "DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT", "Output clock"},
+       {157, 88, "DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT", "Output clock"},
+       {157, 89, "DEV_BOARD0_BUS_SPI1CLK_OUT", "Output clock"},
+       {157, 90, "DEV_BOARD0_BUS_MCASP2ACLKR_OUT", "Output clock"},
+       {157, 91, "DEV_BOARD0_BUS_MCASP1ACLKX_OUT", "Output clock"},
+       {157, 92, "DEV_BOARD0_BUS_MCASP1ACLKR_OUT", "Output clock"},
+       {157, 93, "DEV_BOARD0_BUS_MCASP2ACLKX_OUT", "Output clock"},
+       {157, 94, "DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT", "Output clock"},
+       {157, 95, "DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT", "Output clock"},
+       {157, 96, "DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT", "Output clock"},
+       {157, 97, "DEV_BOARD0_BUS_MCU_SPI0CLK_OUT", "Output clock"},
+       {157, 98, "DEV_BOARD0_BUS_MCU_SPI1CLK_OUT", "Output clock"},
+       {157, 99, "DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT", "Output clock"},
+       {157, 100, "DEV_BOARD0_BUS_SPI2CLK_OUT", "Output clock"},
+       {157, 101, "DEV_BOARD0_BUS_WKUP_TCK_OUT", "Output clock"},
+       {157, 102, "DEV_BOARD0_BUS_SPI3CLK_OUT", "Output clock"},
+       {157, 104, "DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT", "Output clock"},
+       {157, 105, "DEV_BOARD0_BUS_MCASP0AHCLKR_OUT", "Output clock"},
+       {157, 106, "DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT", "Output clock"},
+       {157, 107, "DEV_BOARD0_BUS_MCASP0AHCLKX_OUT", "Output clock"},
+       {157, 108, "DEV_BOARD0_BUS_CCDC0_PCLK_OUT", "Output clock"},
+       {157, 109, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
+       {157, 110, "DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT", "Output clock"},
+       {157, 111, "DEV_BOARD0_BUS_MCASP1AHCLKX_OUT", "Output clock"},
+       {157, 113, "DEV_BOARD0_BUS_MCASP1AHCLKR_OUT", "Output clock"},
+       {157, 115, "DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT", "Output clock"},
+       {157, 116, "DEV_BOARD0_BUS_SPI0CLK_OUT", "Output clock"},
+       {157, 119, "DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_OUT", "Output clock"},
+       {157, 120, "DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_OUT", "Output clock"},
+       {157, 121, "DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_OUT", "Output clock"},
+       {157, 122, "DEV_BOARD0_BUS_PRG1_RGMII2_TCLK_OUT", "Output clock"},
+       {157, 123, "DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_OUT", "Output clock"},
+       {157, 124, "DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_OUT", "Output clock"},
+       {2, 0, "DEV_CAL0_BUS_CLK", "Input clock"},
+       {2, 1, "DEV_CAL0_BUS_CP_C_CLK", "Input clock"},
+       {82, 0, "DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       {82, 1, "DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       {83, 0, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       {83, 1, "DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       {84, 0, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       {84, 1, "DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       {85, 0, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK", "Input muxed clock"},
+       {85, 1, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 2, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 3, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 4, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 5, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 6, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 7, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 8, "DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK"},
+       {85, 9, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK", "Input clock"},
+       {85, 10, "DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK", "Input clock"},
+       {66, 0, "DEV_CCDEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+       {66, 1, "DEV_CCDEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+       {66, 2, "DEV_CCDEBUGSS0_BUS_SYS_CLK", "Input clock"},
+       {66, 3, "DEV_CCDEBUGSS0_BUS_DBG_CLK", "Input clock"},
+       {66, 4, "DEV_CCDEBUGSS0_BUS_CFG_CLK", "Input clock"},
+       {3, 0, "DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       {202, 0, "DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK", "Input clock"},
+       {203, 0, "DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK", "Input clock"},
+       {204, 0, "DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK", "Input clock"},
+       {205, 0, "DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK", "Input clock"},
+       {196, 2, "DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK", "Input clock"},
+       {197, 0, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVH_CLK4_CLK_CLK", "Input clock"},
+       {197, 1, "DEV_COMPUTE_CLUSTER_PBIST0_BUS_DIVP_CLK1_CLK_CLK", "Input clock"},
+       {6, 0, "DEV_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
+       {213, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK", "Input clock"},
+       {213, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK", "Input clock"},
+       {214, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK", "Input clock"},
+       {214, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK", "Input clock"},
+       {211, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK", "Input clock"},
+       {211, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK", "Input clock"},
+       {212, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK", "Input clock"},
+       {212, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK", "Input clock"},
+       {209, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK", "Input clock"},
+       {209, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK", "Input clock"},
+       {206, 0, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK", "Input clock"},
+       {206, 1, "DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK", "Input clock"},
+       {208, 0, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK", "Input clock"},
+       {208, 1, "DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK", "Input clock"},
+       {215, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK", "Input clock"},
+       {215, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK", "Input clock"},
+       {207, 0, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK", "Input clock"},
+       {207, 1, "DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK", "Input clock"},
+       {210, 0, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK", "Input clock"},
+       {210, 1, "DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK", "Input clock"},
+       {99, 0, "DEV_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       {9, 0, "DEV_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {9, 1, "DEV_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {9, 2, "DEV_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {9, 3, "DEV_DCC0_BUS_VBUS_CLK", "Input clock"},
+       {9, 4, "DEV_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {9, 5, "DEV_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {9, 6, "DEV_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {9, 7, "DEV_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {9, 8, "DEV_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {9, 9, "DEV_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {9, 10, "DEV_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {9, 11, "DEV_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {10, 0, "DEV_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {10, 1, "DEV_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {10, 2, "DEV_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {10, 3, "DEV_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {10, 4, "DEV_DCC1_BUS_VBUS_CLK", "Input clock"},
+       {10, 5, "DEV_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {10, 6, "DEV_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {10, 7, "DEV_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {10, 8, "DEV_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {10, 9, "DEV_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {10, 10, "DEV_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {10, 11, "DEV_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {10, 12, "DEV_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {11, 0, "DEV_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {11, 1, "DEV_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {11, 2, "DEV_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {11, 3, "DEV_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {11, 4, "DEV_DCC2_BUS_VBUS_CLK", "Input clock"},
+       {11, 5, "DEV_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {11, 6, "DEV_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {11, 7, "DEV_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {11, 8, "DEV_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {11, 9, "DEV_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {11, 10, "DEV_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {11, 11, "DEV_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {11, 12, "DEV_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {12, 0, "DEV_DCC3_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {12, 1, "DEV_DCC3_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {12, 2, "DEV_DCC3_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {12, 3, "DEV_DCC3_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {12, 4, "DEV_DCC3_BUS_VBUS_CLK", "Input clock"},
+       {12, 5, "DEV_DCC3_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {12, 6, "DEV_DCC3_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {12, 7, "DEV_DCC3_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {12, 8, "DEV_DCC3_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {12, 9, "DEV_DCC3_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {12, 10, "DEV_DCC3_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {12, 11, "DEV_DCC3_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {13, 0, "DEV_DCC4_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {13, 1, "DEV_DCC4_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {13, 2, "DEV_DCC4_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {13, 3, "DEV_DCC4_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {13, 4, "DEV_DCC4_BUS_VBUS_CLK", "Input clock"},
+       {13, 5, "DEV_DCC4_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {13, 6, "DEV_DCC4_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {13, 7, "DEV_DCC4_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {13, 8, "DEV_DCC4_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {13, 9, "DEV_DCC4_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {13, 10, "DEV_DCC4_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {13, 11, "DEV_DCC4_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {14, 0, "DEV_DCC5_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {14, 1, "DEV_DCC5_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {14, 2, "DEV_DCC5_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {14, 3, "DEV_DCC5_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {14, 4, "DEV_DCC5_BUS_VBUS_CLK", "Input clock"},
+       {14, 5, "DEV_DCC5_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {14, 6, "DEV_DCC5_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {14, 7, "DEV_DCC5_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {14, 8, "DEV_DCC5_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {14, 9, "DEV_DCC5_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {14, 10, "DEV_DCC5_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {14, 11, "DEV_DCC5_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {14, 12, "DEV_DCC5_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {15, 0, "DEV_DCC6_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {15, 1, "DEV_DCC6_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {15, 2, "DEV_DCC6_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {15, 3, "DEV_DCC6_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {15, 4, "DEV_DCC6_BUS_VBUS_CLK", "Input clock"},
+       {15, 5, "DEV_DCC6_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {15, 6, "DEV_DCC6_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {15, 7, "DEV_DCC6_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {15, 8, "DEV_DCC6_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {15, 9, "DEV_DCC6_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {15, 10, "DEV_DCC6_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {15, 11, "DEV_DCC6_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {15, 12, "DEV_DCC6_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {16, 0, "DEV_DCC7_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {16, 1, "DEV_DCC7_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {16, 2, "DEV_DCC7_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {16, 3, "DEV_DCC7_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {16, 4, "DEV_DCC7_BUS_VBUS_CLK", "Input clock"},
+       {16, 5, "DEV_DCC7_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {16, 6, "DEV_DCC7_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {16, 7, "DEV_DCC7_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {16, 8, "DEV_DCC7_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {16, 9, "DEV_DCC7_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {16, 10, "DEV_DCC7_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {16, 11, "DEV_DCC7_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {16, 12, "DEV_DCC7_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {20, 0, "DEV_DDRSS0_BUS_DDRSS_VBUS_CLK", "Input clock"},
+       {20, 1, "DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK", "Input clock"},
+       {20, 2, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       {20, 3, "DEV_DDRSS0_BUS_DDRSS_TCLK", "Input clock"},
+       {20, 4, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       {20, 5, "DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       {20, 6, "DEV_DDRSS0_BUS_DDRSS_CFG_CLK", "Input clock"},
+       {20, 7, "DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       {20, 8, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       {20, 9, "DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK", "Input clock"},
+       {68, 0, "DEV_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+       {68, 1, "DEV_DEBUGSS0_BUS_ATB5_CLK", "Input clock"},
+       {68, 2, "DEV_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+       {68, 3, "DEV_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
+       {68, 4, "DEV_DEBUGSS0_BUS_ATB4_CLK", "Input clock"},
+       {68, 5, "DEV_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
+       {68, 6, "DEV_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
+       {68, 7, "DEV_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
+       {68, 8, "DEV_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
+       {21, 0, "DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK", "Input clock"},
+       {21, 1, "DEV_DEBUGSS_WRAP0_BUS_ATB_CLK", "Input clock"},
+       {21, 2, "DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK", "Input clock"},
+       {21, 3, "DEV_DEBUGSS_WRAP0_BUS_CORE_CLK", "Input clock"},
+       {81, 0, "DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK", "Input clock"},
+       {117, 0, "DEV_DFTSS0_BUS_VBUSP_CLK_CLK", "Input clock"},
+       {67, 0, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"},
+       {67, 1, "DEV_DSS0_BUS_DSS_FUNC_CLK", "Input clock"},
+       {67, 2, "DEV_DSS0_BUS_DPI_1_IN_CLK", "Input muxed clock"},
+       {67, 3, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT07", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+       {67, 4, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+       {67, 5, "DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_DSS_BUS_OUT1", "Parent input clock option to DEV_DSS0_BUS_DPI_1_IN_CLK"},
+       {67, 6, "DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"},
+       {67, 7, "DEV_DSS0_BUS_DPI_1_OUT_CLK", "Output clock"},
+       {39, 0, "DEV_ECAP0_BUS_VBUS_CLK", "Input clock"},
+       {86, 0, "DEV_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+       {87, 0, "DEV_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
+       {88, 0, "DEV_ECC_AGGR2_BUS_AGGR_CLK", "Input clock"},
+       {69, 0, "DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK", "Input clock"},
+       {40, 0, "DEV_EHRPWM0_BUS_VBUSP_CLK", "Input clock"},
+       {41, 0, "DEV_EHRPWM1_BUS_VBUSP_CLK", "Input clock"},
+       {42, 0, "DEV_EHRPWM2_BUS_VBUSP_CLK", "Input clock"},
+       {43, 0, "DEV_EHRPWM3_BUS_VBUSP_CLK", "Input clock"},
+       {44, 0, "DEV_EHRPWM4_BUS_VBUSP_CLK", "Input clock"},
+       {45, 0, "DEV_EHRPWM5_BUS_VBUSP_CLK", "Input clock"},
+       {46, 0, "DEV_ELM0_BUS_VBUSP_CLK", "Input clock"},
+       {49, 0, "DEV_EQEP0_BUS_VBUS_CLK", "Input clock"},
+       {50, 0, "DEV_EQEP1_BUS_VBUS_CLK", "Input clock"},
+       {51, 0, "DEV_EQEP2_BUS_VBUS_CLK", "Input clock"},
+       {52, 0, "DEV_ESM0_BUS_CLK", "Input clock"},
+       {56, 0, "DEV_GIC0_BUS_VCLK_CLK", "Input clock"},
+       {57, 0, "DEV_GPIO0_BUS_MMR_CLK", "Input clock"},
+       {58, 0, "DEV_GPIO1_BUS_MMR_CLK", "Input clock"},
+       {100, 0, "DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       {60, 0, "DEV_GPMC0_BUS_FUNC_CLK", "Input muxed clock"},
+       {60, 1, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       {60, 2, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       {60, 3, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       {60, 4, "DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_BUS_FUNC_CLK"},
+       {60, 5, "DEV_GPMC0_BUS_PI_GPMC_RET_CLK", "Input clock"},
+       {60, 6, "DEV_GPMC0_BUS_VBUSP_CLK", "Input clock"},
+       {60, 7, "DEV_GPMC0_BUS_PO_GPMC_DEV_CLK", "Output clock"},
+       {65, 0, "DEV_GPU0_BUS_MEM_CLK", "Input clock"},
+       {65, 1, "DEV_GPU0_BUS_HYD_CORE_CLK", "Input clock"},
+       {65, 2, "DEV_GPU0_BUS_SGX_CORE_CLK", "Input clock"},
+       {65, 3, "DEV_GPU0_BUS_SYS_CLK", "Input clock"},
+       {232, 0, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
+       {232, 1, "DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK", "Input clock"},
+       {231, 0, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK", "Input clock"},
+       {231, 1, "DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK", "Input clock"},
+       {61, 0, "DEV_GTC0_BUS_VBUSP_CLK", "Input muxed clock"},
+       {61, 1, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {61, 2, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {61, 3, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {61, 4, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {61, 5, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {61, 6, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {61, 7, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {61, 8, "DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_GTC0_BUS_VBUSP_CLK"},
+       {110, 0, "DEV_I2C0_BUS_CLK", "Input clock"},
+       {110, 1, "DEV_I2C0_BUS_PISYS_CLK", "Input clock"},
+       {111, 0, "DEV_I2C1_BUS_CLK", "Input clock"},
+       {111, 1, "DEV_I2C1_BUS_PISYS_CLK", "Input clock"},
+       {112, 0, "DEV_I2C2_BUS_CLK", "Input clock"},
+       {112, 1, "DEV_I2C2_BUS_PISYS_CLK", "Input clock"},
+       {113, 0, "DEV_I2C3_BUS_CLK", "Input clock"},
+       {113, 1, "DEV_I2C3_BUS_PISYS_CLK", "Input clock"},
+       {217, 0, "DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK", "Input clock"},
+       {97, 0, "DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       {98, 0, "DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       {104, 0, "DEV_MCASP0_BUS_AUX_CLK", "Input muxed clock"},
+       {104, 1, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 2, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 3, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 4, "DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 5, "DEV_MCASP0_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 6, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 7, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 8, "DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP0_BUS_AUX_CLK"},
+       {104, 9, "DEV_MCASP0_BUS_VBUSP_CLK", "Input clock"},
+       {105, 0, "DEV_MCASP1_BUS_AUX_CLK", "Input muxed clock"},
+       {105, 1, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 2, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 3, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 4, "DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 5, "DEV_MCASP1_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 6, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 7, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 8, "DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP1_BUS_AUX_CLK"},
+       {105, 9, "DEV_MCASP1_BUS_VBUSP_CLK", "Input clock"},
+       {106, 0, "DEV_MCASP2_BUS_AUX_CLK", "Input muxed clock"},
+       {106, 1, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 2, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 3, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 4, "DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 5, "DEV_MCASP2_BUS_AUX_CLK_PARENT_MCASP_ARM1_PLL_DIV_BUS_OUT2", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 6, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 7, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 8, "DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_MCASP2_BUS_AUX_CLK"},
+       {106, 9, "DEV_MCASP2_BUS_VBUSP_CLK", "Input clock"},
+       {137, 0, "DEV_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {137, 1, "DEV_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
+       {137, 2, "DEV_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
+       {137, 3, "DEV_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {138, 0, "DEV_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {138, 1, "DEV_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
+       {138, 2, "DEV_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
+       {138, 3, "DEV_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {139, 0, "DEV_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {139, 1, "DEV_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
+       {139, 2, "DEV_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
+       {139, 3, "DEV_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {140, 0, "DEV_MCSPI3_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {140, 1, "DEV_MCSPI3_BUS_CLKSPIREF_CLK", "Input clock"},
+       {140, 2, "DEV_MCSPI3_BUS_VBUSP_CLK", "Input clock"},
+       {140, 3, "DEV_MCSPI3_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {141, 0, "DEV_MCSPI4_BUS_CLKSPIREF_CLK", "Input clock"},
+       {141, 1, "DEV_MCSPI4_BUS_VBUSP_CLK", "Input clock"},
+       {141, 2, "DEV_MCSPI4_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {141, 3, "DEV_MCSPI4_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {0, 0, "DEV_MCU_ADC0_BUS_VBUS_CLK", "Input clock"},
+       {0, 1, "DEV_MCU_ADC0_BUS_SYS_CLK", "Input clock"},
+       {0, 2, "DEV_MCU_ADC0_BUS_ADC_CLK", "Input muxed clock"},
+       {0, 3, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       {0, 4, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       {0, 5, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       {0, 6, "DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_BUS_ADC_CLK"},
+       {1, 0, "DEV_MCU_ADC1_BUS_VBUS_CLK", "Input clock"},
+       {1, 1, "DEV_MCU_ADC1_BUS_SYS_CLK", "Input clock"},
+       {1, 2, "DEV_MCU_ADC1_BUS_ADC_CLK", "Input muxed clock"},
+       {1, 3, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       {1, 4, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       {1, 5, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       {1, 6, "DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_BUS_ADC_CLK"},
+       {159, 0, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK", "Input clock"},
+       {159, 1, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE", "Input muxed clock"},
+       {159, 2, "DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE"},
+       {159, 3, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK", "Input muxed clock"},
+       {159, 4, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
+       {159, 5, "DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK"},
+       {245, 0, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK", "Input clock"},
+       {245, 1, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE", "Input muxed clock"},
+       {245, 2, "DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE"},
+       {245, 3, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK", "Input muxed clock"},
+       {245, 4, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
+       {245, 5, "DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK"},
+       {89, 0, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK", "Input clock"},
+       {89, 1, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
+       {89, 2, "DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+       {90, 0, "DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+       {91, 0, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK", "Input clock"},
+       {91, 1, "DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK", "Input clock"},
+       {5, 0, "DEV_MCU_CPSW0_BUS_GMII1_MR_CLK", "Input clock"},
+       {5, 1, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       {5, 2, "DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK", "Input clock"},
+       {5, 3, "DEV_MCU_CPSW0_BUS_GMII1_MT_CLK", "Input clock"},
+       {5, 4, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       {5, 5, "DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       {5, 6, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK", "Input muxed clock"},
+       {5, 7, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
+       {5, 8, "DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK"},
+       {5, 9, "DEV_MCU_CPSW0_BUS_GMII_RFT_CLK", "Input clock"},
+       {5, 10, "DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK", "Input clock"},
+       {7, 0, "DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK", "Input clock"},
+       {107, 0, "DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       {17, 0, "DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {17, 1, "DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {17, 2, "DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {17, 3, "DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {17, 4, "DEV_MCU_DCC0_BUS_VBUS_CLK", "Input clock"},
+       {17, 5, "DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {17, 6, "DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {17, 7, "DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {17, 8, "DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {17, 9, "DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {17, 10, "DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {17, 11, "DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {17, 12, "DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {18, 0, "DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {18, 1, "DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {18, 2, "DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {18, 3, "DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {18, 4, "DEV_MCU_DCC1_BUS_VBUS_CLK", "Input clock"},
+       {18, 5, "DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {18, 6, "DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {18, 7, "DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {18, 8, "DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {18, 9, "DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {18, 10, "DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {18, 11, "DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {18, 12, "DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {19, 0, "DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK", "Input clock"},
+       {19, 1, "DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK", "Input clock"},
+       {19, 2, "DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK", "Input clock"},
+       {19, 3, "DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK", "Input clock"},
+       {19, 4, "DEV_MCU_DCC2_BUS_VBUS_CLK", "Input clock"},
+       {19, 5, "DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK", "Input clock"},
+       {19, 6, "DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK", "Input clock"},
+       {19, 7, "DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK", "Input clock"},
+       {19, 8, "DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK", "Input clock"},
+       {19, 9, "DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK", "Input clock"},
+       {19, 10, "DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK", "Input clock"},
+       {19, 11, "DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK", "Input clock"},
+       {19, 12, "DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK", "Input clock"},
+       {71, 0, "DEV_MCU_DEBUGSS0_BUS_ATB1_CLK", "Input clock"},
+       {71, 1, "DEV_MCU_DEBUGSS0_BUS_ATB0_CLK", "Input clock"},
+       {71, 2, "DEV_MCU_DEBUGSS0_BUS_SYS_CLK", "Input clock"},
+       {71, 3, "DEV_MCU_DEBUGSS0_BUS_CFG_CLK", "Input clock"},
+       {71, 4, "DEV_MCU_DEBUGSS0_BUS_ATB2_CLK", "Input clock"},
+       {71, 5, "DEV_MCU_DEBUGSS0_BUS_DBG_CLK", "Input clock"},
+       {71, 6, "DEV_MCU_DEBUGSS0_BUS_ATB3_CLK", "Input clock"},
+       {92, 0, "DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+       {93, 0, "DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK", "Input clock"},
+       {72, 0, "DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK", "Input clock"},
+       {53, 0, "DEV_MCU_ESM0_BUS_CLK", "Input clock"},
+       {247, 0, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK", "Input clock"},
+       {247, 1, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK", "Input clock"},
+       {247, 2, "DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK", "Input clock"},
+       {247, 3, "DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK", "Input clock"},
+       {248, 0, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK", "Input muxed clock"},
+       {248, 1, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"},
+       {248, 2, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_RCLK_CLK"},
+       {248, 3, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK", "Input muxed clock"},
+       {248, 4, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"},
+       {248, 5, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_BUS_OSPI_ICLK_CLK"},
+       {248, 6, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_PCLK_CLK", "Input clock"},
+       {248, 7, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_DQS_CLK", "Input clock"},
+       {248, 8, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_HCLK_CLK", "Input clock"},
+       {248, 9, "DEV_MCU_FSS0_OSPI_0_BUS_OSPI_OCLK_CLK", "Output clock"},
+       {249, 0, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_PCLK_CLK", "Input clock"},
+       {249, 1, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK", "Input muxed clock"},
+       {249, 2, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"},
+       {249, 3, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_ICLK_CLK"},
+       {249, 4, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_HCLK_CLK", "Input clock"},
+       {249, 5, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_DQS_CLK", "Input clock"},
+       {249, 6, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK", "Input muxed clock"},
+       {249, 7, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"},
+       {249, 8, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_BUS_OSPI_RCLK_CLK"},
+       {249, 9, "DEV_MCU_FSS0_OSPI_1_BUS_OSPI_OCLK_CLK", "Output clock"},
+       {114, 0, "DEV_MCU_I2C0_BUS_CLK", "Input clock"},
+       {114, 1, "DEV_MCU_I2C0_BUS_PISYS_CLK", "Input clock"},
+       {102, 0, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
+       {102, 1, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       {102, 2, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       {102, 3, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       {102, 4, "DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK"},
+       {102, 5, "DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK", "Input clock"},
+       {103, 0, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK", "Input muxed clock"},
+       {103, 1, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       {103, 2, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       {103, 3, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       {103, 4, "DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK"},
+       {103, 5, "DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK", "Input clock"},
+       {142, 0, "DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {142, 1, "DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK", "Input clock"},
+       {142, 2, "DEV_MCU_MCSPI0_BUS_VBUSP_CLK", "Input clock"},
+       {142, 3, "DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {143, 0, "DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {143, 1, "DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK", "Input clock"},
+       {143, 2, "DEV_MCU_MCSPI1_BUS_VBUSP_CLK", "Input clock"},
+       {143, 3, "DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {144, 0, "DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK", "Input clock"},
+       {144, 1, "DEV_MCU_MCSPI2_BUS_VBUSP_CLK", "Input clock"},
+       {144, 2, "DEV_MCU_MCSPI2_BUS_IO_CLKSPII_CLK", "Input clock"},
+       {144, 3, "DEV_MCU_MCSPI2_BUS_IO_CLKSPIO_CLK", "Output clock"},
+       {116, 0, "DEV_MCU_MSRAM0_BUS_CCLK_CLK", "Input clock"},
+       {116, 1, "DEV_MCU_MSRAM0_BUS_VCLK_CLK", "Input clock"},
+       {119, 1, "DEV_MCU_NAVSS0_BUS_CPSW0CLK", "Input clock"},
+       {119, 2, "DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK", "Input clock"},
+       {119, 3, "DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK", "Input clock"},
+       {75, 0, "DEV_MCU_PBIST0_BUS_CLK1_CLK", "Input clock"},
+       {75, 1, "DEV_MCU_PBIST0_BUS_CLK4_CLK", "Input clock"},
+       {75, 2, "DEV_MCU_PBIST0_BUS_CLK2_CLK", "Input clock"},
+       {125, 0, "DEV_MCU_PDMA0_BUS_VCLK", "Input clock"},
+       {126, 0, "DEV_MCU_PDMA1_BUS_VCLK", "Input clock"},
+       {108, 0, "DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       {127, 0, "DEV_MCU_PSRAM0_BUS_CLK_CLK", "Input clock"},
+       {78, 0, "DEV_MCU_ROM0_BUS_CLK_CLK", "Input clock"},
+       {134, 0, "DEV_MCU_RTI0_BUS_RTI_CLK", "Input muxed clock"},
+       {134, 1, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       {134, 2, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       {134, 3, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       {134, 4, "DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_BUS_RTI_CLK"},
+       {134, 5, "DEV_MCU_RTI0_BUS_VBUSP_CLK", "Input clock"},
+       {135, 0, "DEV_MCU_RTI1_BUS_RTI_CLK", "Input muxed clock"},
+       {135, 1, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       {135, 2, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       {135, 3, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       {135, 4, "DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_BUS_RTI_CLK"},
+       {135, 5, "DEV_MCU_RTI1_BUS_VBUSP_CLK", "Input clock"},
+       {109, 0, "DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       {35, 0, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {35, 1, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {35, 2, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {35, 3, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {35, 4, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {35, 5, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {35, 6, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {35, 8, "DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {35, 9, "DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {36, 0, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {36, 1, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {36, 2, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {36, 3, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {36, 4, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {36, 5, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {36, 6, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {36, 8, "DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {36, 9, "DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {37, 0, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {37, 1, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {37, 2, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {37, 3, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {37, 4, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {37, 5, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {37, 6, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {37, 8, "DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {37, 9, "DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {38, 0, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {38, 1, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {38, 2, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {38, 3, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {38, 4, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {38, 5, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {38, 6, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {38, 8, "DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {38, 9, "DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {149, 0, "DEV_MCU_UART0_BUS_FCLK_CLK", "Input muxed clock"},
+       {149, 1, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
+       {149, 2, "DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_MCU_UART0_BUS_FCLK_CLK"},
+       {149, 3, "DEV_MCU_UART0_BUS_VBUSP_CLK", "Input clock"},
+       {47, 0, "DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
+       {47, 1, "DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
+       {48, 0, "DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK", "Input clock"},
+       {48, 1, "DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK", "Input clock"},
+       {118, 1, "DEV_NAVSS0_BUS_ICSS_G2CLK", "Input clock"},
+       {118, 2, "DEV_NAVSS0_BUS_ICSS_G0CLK", "Input clock"},
+       {118, 3, "DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
+       {118, 4, "DEV_NAVSS0_BUS_MSMC0CLK", "Input clock"},
+       {118, 5, "DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+       {118, 6, "DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
+       {118, 8, "DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
+       {118, 9, "DEV_NAVSS0_BUS_PDMA_MAIN1CLK", "Input clock"},
+       {118, 10, "DEV_NAVSS0_BUS_NBSS_VCLK", "Input clock"},
+       {118, 11, "DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+       {118, 12, "DEV_NAVSS0_BUS_NBSS_VD2CLK", "Input clock"},
+       {118, 13, "DEV_NAVSS0_BUS_ICSS_G1CLK", "Input clock"},
+       {118, 14, "DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
+       {216, 0, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK", "Input clock"},
+       {216, 1, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_DSS_BUS_OUT0", "Input clock"},
+       {216, 2, "DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_DSS_BUS_OUT0", "Input clock"},
+       {73, 0, "DEV_PBIST0_BUS_CLK1_CLK", "Input clock"},
+       {73, 1, "DEV_PBIST0_BUS_CLK4_CLK", "Input clock"},
+       {73, 2, "DEV_PBIST0_BUS_CLK2_CLK", "Input clock"},
+       {74, 0, "DEV_PBIST1_BUS_CLK1_CLK", "Input clock"},
+       {74, 1, "DEV_PBIST1_BUS_CLK4_CLK", "Input clock"},
+       {74, 2, "DEV_PBIST1_BUS_CLK2_CLK", "Input clock"},
+       {120, 0, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
+       {120, 1, "DEV_PCIE0_BUS_PCIE_CBA_CLK", "Input clock"},
+       {120, 2, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
+       {120, 3, "DEV_PCIE0_BUS_PCIE_TXI0_CLK", "Input clock"},
+       {120, 4, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+       {120, 5, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+       {120, 6, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
+       {120, 7, "DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
+       {120, 8, "DEV_PCIE0_BUS_PCIE_TXR1_CLK", "Output clock"},
+       {120, 9, "DEV_PCIE0_BUS_PCIE_TXR0_CLK", "Output clock"},
+       {121, 0, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT", "Input clock"},
+       {121, 1, "DEV_PCIE1_BUS_PCIE_CBA_CLK", "Input clock"},
+       {121, 2, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Input clock"},
+       {121, 3, "DEV_PCIE1_BUS_PCIE_TXI0_CLK", "Input clock"},
+       {121, 4, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Input clock"},
+       {121, 5, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Input clock"},
+       {121, 6, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Input clock"},
+       {121, 7, "DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Input clock"},
+       {121, 8, "DEV_PCIE1_BUS_PCIE_TXR0_CLK", "Output clock"},
+       {123, 0, "DEV_PDMA0_BUS_VCLK", "Input clock"},
+       {124, 0, "DEV_PDMA1_BUS_VCLK", "Input clock"},
+       {122, 0, "DEV_PDMA_DEBUG0_BUS_VCLK", "Input clock"},
+       {76, 0, "DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
+       {76, 1, "DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
+       {76, 2, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input muxed clock"},
+       {76, 3, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
+       {76, 4, "DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK"},
+       {101, 0, "DEV_PLL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       {62, 0, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       {62, 1, "DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+       {62, 2, "DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+       {62, 3, "DEV_PRU_ICSSG0_BUS_VCLK_CLK", "Input clock"},
+       {62, 4, "DEV_PRU_ICSSG0_BUS_UCLK_CLK", "Input clock"},
+       {62, 5, "DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+       {62, 6, "DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+       {62, 8, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       {62, 9, "DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       {62, 10, "DEV_PRU_ICSSG0_BUS_IEP_CLK", "Input muxed clock"},
+       {62, 11, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 12, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 13, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 14, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 15, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 16, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 17, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 18, "DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_IEP_CLK"},
+       {62, 19, "DEV_PRU_ICSSG0_BUS_CORE_CLK", "Input muxed clock"},
+       {62, 20, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
+       {62, 21, "DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG0_BUS_CORE_CLK"},
+       {63, 0, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       {63, 1, "DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+       {63, 2, "DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+       {63, 3, "DEV_PRU_ICSSG1_BUS_VCLK_CLK", "Input clock"},
+       {63, 4, "DEV_PRU_ICSSG1_BUS_UCLK_CLK", "Input clock"},
+       {63, 5, "DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+       {63, 6, "DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+       {63, 8, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       {63, 9, "DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       {63, 10, "DEV_PRU_ICSSG1_BUS_IEP_CLK", "Input muxed clock"},
+       {63, 11, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 12, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 13, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 14, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 15, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 16, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 17, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 18, "DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_IEP_CLK"},
+       {63, 19, "DEV_PRU_ICSSG1_BUS_CORE_CLK", "Input muxed clock"},
+       {63, 20, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
+       {63, 21, "DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG1_BUS_CORE_CLK"},
+       {64, 0, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK", "Input clock"},
+       {64, 1, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK", "Input clock"},
+       {64, 2, "DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK", "Input clock"},
+       {64, 3, "DEV_PRU_ICSSG2_BUS_VCLK_CLK", "Input clock"},
+       {64, 4, "DEV_PRU_ICSSG2_BUS_UCLK_CLK", "Input clock"},
+       {64, 5, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK", "Input clock"},
+       {64, 6, "DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK", "Input clock"},
+       {64, 8, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK", "Input clock"},
+       {64, 9, "DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK", "Input clock"},
+       {64, 10, "DEV_PRU_ICSSG2_BUS_IEP_CLK", "Input muxed clock"},
+       {64, 11, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 12, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 13, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 14, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 15, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 16, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 17, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 18, "DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_IEP_CLK"},
+       {64, 19, "DEV_PRU_ICSSG2_BUS_CORE_CLK", "Input muxed clock"},
+       {64, 20, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
+       {64, 21, "DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_PRU_ICSSG2_BUS_CORE_CLK"},
+       {64, 25, "DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK", "Output clock"},
+       {64, 26, "DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK", "Output clock"},
+       {70, 0, "DEV_PSC0_BUS_CLK", "Input clock"},
+       {70, 1, "DEV_PSC0_BUS_SLOW_CLK", "Input clock"},
+       {128, 0, "DEV_PSRAMECC0_BUS_CLK_CLK", "Input clock"},
+       {130, 0, "DEV_RTI0_BUS_RTI_CLK", "Input muxed clock"},
+       {130, 1, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 2, "DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 3, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 4, "DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 5, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 6, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 7, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 8, "DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_BUS_RTI_CLK"},
+       {130, 9, "DEV_RTI0_BUS_VBUSP_CLK", "Input clock"},
+       {131, 0, "DEV_RTI1_BUS_RTI_CLK", "Input muxed clock"},
+       {131, 1, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 2, "DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 3, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 4, "DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 5, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 6, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 7, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 8, "DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_BUS_RTI_CLK"},
+       {131, 9, "DEV_RTI1_BUS_VBUSP_CLK", "Input clock"},
+       {132, 0, "DEV_RTI2_BUS_RTI_CLK", "Input muxed clock"},
+       {132, 1, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 2, "DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 3, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 4, "DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 5, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 6, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 7, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 8, "DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI2_BUS_RTI_CLK"},
+       {132, 9, "DEV_RTI2_BUS_VBUSP_CLK", "Input clock"},
+       {133, 0, "DEV_RTI3_BUS_RTI_CLK", "Input muxed clock"},
+       {133, 1, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 2, "DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 3, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 4, "DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 5, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 6, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 7, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 8, "DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI3_BUS_RTI_CLK"},
+       {133, 9, "DEV_RTI3_BUS_VBUSP_CLK", "Input clock"},
+       {136, 0, "DEV_SA2_UL0_BUS_PKA_IN_CLK", "Input clock"},
+       {136, 1, "DEV_SA2_UL0_BUS_X1_CLK", "Input clock"},
+       {136, 2, "DEV_SA2_UL0_BUS_X2_CLK", "Input clock"},
+       {153, 0, "DEV_SERDES0_BUS_IP3_LN0_TXRCLK", "Input clock"},
+       {153, 2, "DEV_SERDES0_BUS_CLK", "Input clock"},
+       {153, 3, "DEV_SERDES0_BUS_IP2_LN0_TXRCLK", "Input clock"},
+       {153, 4, "DEV_SERDES0_BUS_LI_REFCLK", "Input muxed clock"},
+       {153, 5, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       {153, 6, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       {153, 7, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       {153, 8, "DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES0_BUS_LI_REFCLK"},
+       {153, 10, "DEV_SERDES0_BUS_LN0_TXCLK", "Output clock"},
+       {153, 11, "DEV_SERDES0_BUS_LN0_RXCLK", "Output clock"},
+       {154, 0, "DEV_SERDES1_BUS_IP3_LN0_TXRCLK", "Input clock"},
+       {154, 2, "DEV_SERDES1_BUS_CLK", "Input clock"},
+       {154, 3, "DEV_SERDES1_BUS_IP1_LN0_TXRCLK", "Input clock"},
+       {154, 4, "DEV_SERDES1_BUS_IP2_LN0_TXRCLK", "Input clock"},
+       {154, 5, "DEV_SERDES1_BUS_RI_REFCLK", "Input muxed clock"},
+       {154, 6, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       {154, 7, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       {154, 8, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       {154, 9, "DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK", "Parent input clock option to DEV_SERDES1_BUS_RI_REFCLK"},
+       {154, 11, "DEV_SERDES1_BUS_LN0_TXCLK", "Output clock"},
+       {154, 12, "DEV_SERDES1_BUS_LN0_RXCLK", "Output clock"},
+       {8, 0, "DEV_STM0_BUS_CORE_CLK", "Input clock"},
+       {8, 1, "DEV_STM0_BUS_ATB_CLK", "Input clock"},
+       {8, 2, "DEV_STM0_BUS_VBUSP_CLK", "Input clock"},
+       {23, 0, "DEV_TIMER0_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {23, 1, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 2, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 3, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 4, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 5, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 6, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 7, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 8, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 9, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 10, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 11, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 12, "DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER0_BUS_TIMER_TCLK_CLK"},
+       {23, 17, "DEV_TIMER0_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {24, 0, "DEV_TIMER1_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {24, 1, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 2, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 3, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 4, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 5, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 6, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 7, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 8, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 9, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 10, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 11, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 12, "DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER1_BUS_TIMER_TCLK_CLK"},
+       {24, 17, "DEV_TIMER1_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {25, 0, "DEV_TIMER10_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {25, 1, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 2, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 3, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 4, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 5, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 6, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 7, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 8, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 9, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 10, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 11, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 12, "DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER10_BUS_TIMER_TCLK_CLK"},
+       {25, 17, "DEV_TIMER10_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {26, 0, "DEV_TIMER11_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {26, 1, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 2, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 3, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 4, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 5, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 6, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 7, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 8, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 9, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 10, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 11, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 12, "DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER11_BUS_TIMER_TCLK_CLK"},
+       {26, 17, "DEV_TIMER11_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {27, 0, "DEV_TIMER2_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {27, 1, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 2, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 3, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 4, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 5, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 6, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 7, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 8, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 9, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 10, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 11, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 12, "DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER2_BUS_TIMER_TCLK_CLK"},
+       {27, 17, "DEV_TIMER2_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {28, 0, "DEV_TIMER3_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {28, 1, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 2, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 3, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 4, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 5, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 6, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 7, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 8, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 9, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 10, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 11, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 12, "DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER3_BUS_TIMER_TCLK_CLK"},
+       {28, 17, "DEV_TIMER3_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {29, 0, "DEV_TIMER4_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {29, 1, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 2, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 3, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 4, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 5, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 6, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 7, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 8, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 9, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 10, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 11, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 12, "DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER4_BUS_TIMER_TCLK_CLK"},
+       {29, 17, "DEV_TIMER4_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {30, 0, "DEV_TIMER5_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {30, 1, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 2, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 3, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 4, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 5, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 6, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 7, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 8, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 9, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 10, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 11, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 12, "DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER5_BUS_TIMER_TCLK_CLK"},
+       {30, 17, "DEV_TIMER5_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {31, 0, "DEV_TIMER6_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {31, 1, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 2, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 3, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 4, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 5, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 6, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 7, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 8, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 9, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 10, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 11, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 12, "DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER6_BUS_TIMER_TCLK_CLK"},
+       {31, 17, "DEV_TIMER6_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {32, 0, "DEV_TIMER7_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {32, 1, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 2, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 3, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 4, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 5, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 6, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 7, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 8, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 9, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 10, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 11, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 12, "DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER7_BUS_TIMER_TCLK_CLK"},
+       {32, 17, "DEV_TIMER7_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {33, 0, "DEV_TIMER8_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {33, 1, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 2, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 3, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 4, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 5, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 6, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 7, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 8, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 9, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 10, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 11, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 12, "DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER8_BUS_TIMER_TCLK_CLK"},
+       {33, 17, "DEV_TIMER8_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {34, 0, "DEV_TIMER9_BUS_TIMER_TCLK_CLK", "Input muxed clock"},
+       {34, 1, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 2, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 3, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 4, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 5, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 6, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 7, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 8, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 9, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 10, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 11, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 12, "DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_TIMER9_BUS_TIMER_TCLK_CLK"},
+       {34, 17, "DEV_TIMER9_BUS_TIMER_HCLK_CLK", "Input clock"},
+       {145, 0, "DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       {146, 0, "DEV_UART0_BUS_FCLK_CLK", "Input clock"},
+       {146, 1, "DEV_UART0_BUS_VBUSP_CLK", "Input clock"},
+       {147, 0, "DEV_UART1_BUS_FCLK_CLK", "Input clock"},
+       {147, 1, "DEV_UART1_BUS_VBUSP_CLK", "Input clock"},
+       {148, 0, "DEV_UART2_BUS_FCLK_CLK", "Input clock"},
+       {148, 1, "DEV_UART2_BUS_VBUSP_CLK", "Input clock"},
+       {151, 0, "DEV_USB3SS0_BUS_SUSP_CLK", "Input clock"},
+       {151, 1, "DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
+       {151, 2, "DEV_USB3SS0_BUS_REF_CLK", "Input muxed clock"},
+       {151, 3, "DEV_USB3SS0_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
+       {151, 4, "DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS0_BUS_REF_CLK"},
+       {151, 5, "DEV_USB3SS0_BUS_HSIC_CLK_CLK", "Input clock"},
+       {151, 6, "DEV_USB3SS0_BUS_BUS_CLK", "Input clock"},
+       {151, 7, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK", "Input muxed clock"},
+       {151, 8, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
+       {151, 9, "DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_USB3SS0_BUS_PIPE3_TXB_CLK"},
+       {151, 10, "DEV_USB3SS0_BUS_UTMI_CLK_CLK", "Input clock"},
+       {152, 0, "DEV_USB3SS1_BUS_SUSP_CLK", "Input clock"},
+       {152, 1, "DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK", "Input clock"},
+       {152, 2, "DEV_USB3SS1_BUS_REF_CLK", "Input muxed clock"},
+       {152, 3, "DEV_USB3SS1_BUS_REF_CLK_PARENT_HFOSC_SEL_BUS_OUT0", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
+       {152, 4, "DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48", "Parent input clock option to DEV_USB3SS1_BUS_REF_CLK"},
+       {152, 5, "DEV_USB3SS1_BUS_HSIC_CLK_CLK", "Input clock"},
+       {152, 6, "DEV_USB3SS1_BUS_BUS_CLK", "Input clock"},
+       {152, 7, "DEV_USB3SS1_BUS_PIPE3_TXB_CLK", "Input clock"},
+       {152, 8, "DEV_USB3SS1_BUS_UTMI_CLK_CLK", "Input clock"},
+       {94, 0, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
+       {94, 1, "DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK", "Input clock"},
+       {96, 0, "DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK", "Input clock"},
+       {155, 0, "DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK", "Input clock"},
+       {95, 0, "DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK", "Input clock"},
+       {54, 0, "DEV_WKUP_ESM0_BUS_CLK", "Input clock"},
+       {59, 0, "DEV_WKUP_GPIO0_BUS_MMR_CLK", "Input muxed clock"},
+       {59, 1, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       {59, 2, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       {59, 3, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       {59, 4, "DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_WKUP_GPIO0_BUS_MMR_CLK"},
+       {156, 0, "DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK", "Input clock"},
+       {115, 0, "DEV_WKUP_I2C0_BUS_CLK", "Input clock"},
+       {115, 1, "DEV_WKUP_I2C0_BUS_PISYS_CLK", "Input muxed clock"},
+       {115, 2, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
+       {115, 3, "DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_I2C0_BUS_PISYS_CLK"},
+       {77, 0, "DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK", "Input clock"},
+       {77, 1, "DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK", "Input clock"},
+       {77, 2, "DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK", "Input clock"},
+       {79, 0, "DEV_WKUP_PSC0_BUS_CLK", "Input clock"},
+       {79, 1, "DEV_WKUP_PSC0_BUS_SLOW_CLK", "Input clock"},
+       {150, 0, "DEV_WKUP_UART0_BUS_FCLK_CLK", "Input muxed clock"},
+       {150, 1, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_BUS_OUT0", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
+       {150, 2, "DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK", "Parent input clock option to DEV_WKUP_UART0_BUS_FCLK_CLK"},
+       {150, 3, "DEV_WKUP_UART0_BUS_VBUSP_CLK", "Input clock"},
+       {80, 0, "DEV_WKUP_VTM0_BUS_FIX_REF_CLK", "Input clock"},
+       {80, 1, "DEV_WKUP_VTM0_BUS_VBUSP_CLK", "Input clock"},
 };