Bump up version to 0.2
[k3conf/k3conf.git] / soc / j721e / j721e_devices_info.c
index 485972539402856b2b4e7c809dc9a6e381ed7210..eef28a98dd1277ec28e5018206afd577dafd1d1a 100644 (file)
 #include <socinfo.h>
 
 struct ti_sci_devices_info j721e_devices_info[] = {
-       [0] = {0, "J721E_DEV_MCU_ADC0"},
-       [1] = {1, "J721E_DEV_MCU_ADC1"},
+       [0] = {0, "J721E_DEV_MCU_ADC12_16FFC0"},
+       [1] = {1, "J721E_DEV_MCU_ADC12_16FFC1"},
        [2] = {2, "J721E_DEV_ATL0"},
-       [3] = {3, "J721E_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0"},
+       [3] = {3, "J721E_DEV_COMPUTE_CLUSTER0"},
        [4] = {4, "J721E_DEV_A72SS0"},
        [5] = {5, "J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP"},
        [6] = {6, "J721E_DEV_COMPUTE_CLUSTER0_CLEC"},
@@ -58,7 +58,7 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [19] = {19, "J721E_DEV_CPSW0"},
        [20] = {20, "J721E_DEV_CPT2_AGGR0"},
        [21] = {21, "J721E_DEV_CPT2_AGGR1"},
-       [22] = {22, "J721E_DEV_DMSC_WKUP_0"},
+       [22] = {22, "J721E_DEV_WKUP_DMSC0"},
        [23] = {23, "J721E_DEV_CPT2_AGGR2"},
        [24] = {24, "J721E_DEV_MCU_CPT2_AGGR0"},
        [25] = {25, "J721E_DEV_CSI_PSILSS0"},
@@ -84,7 +84,7 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [45] = {45, "J721E_DEV_MCU_DCC1"},
        [46] = {46, "J721E_DEV_MCU_DCC2"},
        [47] = {47, "J721E_DEV_DDR0"},
-       [48] = {48, "J721E_DEV_DMPAC_TOP_MAIN_0"},
+       [48] = {48, "J721E_DEV_DMPAC0"},
        [49] = {49, "J721E_DEV_TIMER0"},
        [50] = {50, "J721E_DEV_TIMER1"},
        [51] = {51, "J721E_DEV_TIMER2"},
@@ -135,7 +135,7 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [96] = {97, "J721E_DEV_ESM0"},
        [97] = {98, "J721E_DEV_MCU_ESM0"},
        [98] = {99, "J721E_DEV_WKUP_ESM0"},
-       [99] = {100, "J721E_DEV_FSS_MCU_0"},
+       [99] = {100, "J721E_DEV_MCU_FSS0"},
        [100] = {101, "J721E_DEV_MCU_FSS0_FSAS_0"},
        [101] = {102, "J721E_DEV_MCU_FSS0_HYPERBUS1P0_0"},
        [102] = {103, "J721E_DEV_MCU_FSS0_OSPI_0"},
@@ -159,7 +159,7 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [120] = {121, "J721E_DEV_C66SS0_INTROUTER0"},
        [121] = {122, "J721E_DEV_C66SS1_INTROUTER0"},
        [122] = {123, "J721E_DEV_CMPEVENT_INTRTR0"},
-       [123] = {124, "J721E_DEV_J7_LASCAR_GPU_WRAP_MAIN_0"},
+       [123] = {124, "J721E_DEV_GPU0"},
        [124] = {125, "J721E_DEV_GPU0_GPU_0"},
        [125] = {126, "J721E_DEV_GPU0_GPUCORE_0"},
        [126] = {127, "J721E_DEV_LED0"},
@@ -174,8 +174,8 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [135] = {137, "J721E_DEV_WKUP_GPIOMUX_INTRTR0"},
        [136] = {138, "J721E_DEV_WKUP_PSC0"},
        [137] = {139, "J721E_DEV_AASRC0"},
-       [138] = {140, "J721E_DEV_K3_C66_COREPAC_MAIN_0"},
-       [139] = {141, "J721E_DEV_K3_C66_COREPAC_MAIN_1"},
+       [138] = {140, "J721E_DEV_C66SS0"},
+       [139] = {141, "J721E_DEV_C66SS1"},
        [140] = {142, "J721E_DEV_C66SS0_CORE0"},
        [141] = {143, "J721E_DEV_C66SS1_CORE0"},
        [142] = {144, "J721E_DEV_DECODER0"},
@@ -230,7 +230,7 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [191] = {194, "J721E_DEV_MCU_I2C0"},
        [192] = {195, "J721E_DEV_MCU_I2C1"},
        [193] = {197, "J721E_DEV_WKUP_I2C0"},
-       [194] = {199, "J721E_DEV_NAVSS512L_MAIN_0"},
+       [194] = {199, "J721E_DEV_NAVSS0"},
        [195] = {201, "J721E_DEV_NAVSS0_CPTS_0"},
        [196] = {202, "J721E_DEV_A72SS0_CORE0"},
        [197] = {203, "J721E_DEV_A72SS0_CORE1"},
@@ -260,24 +260,24 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [221] = {229, "J721E_DEV_NAVSS0_TCU_0"},
        [222] = {230, "J721E_DEV_NAVSS0_TIMERMGR_0"},
        [223] = {231, "J721E_DEV_NAVSS0_TIMERMGR_1"},
-       [224] = {232, "J721E_DEV_NAVSS_MCU_J7_MCU_0"},
-       [225] = {233, "J721E_DEV_MCU_NAVSS0_INTAGGR_0"},
-       [226] = {234, "J721E_DEV_MCU_NAVSS0_PROXY_0"},
-       [227] = {235, "J721E_DEV_MCU_NAVSS0_RINGACC_0"},
+       [224] = {232, "J721E_DEV_MCU_NAVSS0"},
+       [225] = {233, "J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0"},
+       [226] = {234, "J721E_DEV_MCU_NAVSS0_PROXY0"},
+       [227] = {235, "J721E_DEV_MCU_NAVSS0_RINGACC0"},
        [228] = {236, "J721E_DEV_MCU_NAVSS0_UDMAP_0"},
-       [229] = {237, "J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0"},
+       [229] = {237, "J721E_DEV_MCU_NAVSS0_INTR_0"},
        [230] = {238, "J721E_DEV_MCU_NAVSS0_MCRC_0"},
        [231] = {239, "J721E_DEV_PCIE0"},
        [232] = {240, "J721E_DEV_PCIE1"},
        [233] = {241, "J721E_DEV_PCIE2"},
        [234] = {242, "J721E_DEV_PCIE3"},
-       [235] = {243, "J721E_DEV_PULSAR_SL_MAIN_0"},
-       [236] = {244, "J721E_DEV_PULSAR_SL_MAIN_1"},
+       [235] = {243, "J721E_DEV_R5FSS0"},
+       [236] = {244, "J721E_DEV_R5FSS1"},
        [237] = {245, "J721E_DEV_R5FSS0_CORE0"},
        [238] = {246, "J721E_DEV_R5FSS0_CORE1"},
        [239] = {247, "J721E_DEV_R5FSS1_CORE0"},
        [240] = {248, "J721E_DEV_R5FSS1_CORE1"},
-       [241] = {249, "J721E_DEV_PULSAR_SL_MCU_0"},
+       [241] = {249, "J721E_DEV_MCU_R5FSS0"},
        [242] = {250, "J721E_DEV_MCU_R5FSS0_CORE0"},
        [243] = {251, "J721E_DEV_MCU_R5FSS0_CORE1"},
        [244] = {252, "J721E_DEV_RTI0"},
@@ -318,7 +318,7 @@ struct ti_sci_devices_info j721e_devices_info[] = {
        [279] = {287, "J721E_DEV_WKUP_UART0"},
        [280] = {288, "J721E_DEV_USB0"},
        [281] = {289, "J721E_DEV_USB1"},
-       [282] = {290, "J721E_DEV_VPAC_TOP_MAIN_0"},
+       [282] = {290, "J721E_DEV_VPAC0"},
        [283] = {291, "J721E_DEV_VPFE0"},
        [284] = {292, "J721E_DEV_SERDES_16G0"},
        [285] = {293, "J721E_DEV_SERDES_16G1"},