soc: j721e: Update sysfw data corresponding to v2020.08b

[k3conf/k3conf.git] / soc / j721e / j721e_host_info.c

diff --git a/soc/j721e/j721e_host_info.c b/soc/j721e/j721e_host_info.c
index 15303f4d2008d87604696b3b66a2ae37c7e367ed..e4b3d2b26bef607cb60c978358f6fb5762e6473e 100644 (file)
--- a/soc/j721e/j721e_host_info.c
+++ b/soc/j721e/j721e_host_info.c
@@ -1,7 +1,7 @@
 /*
- * SoC Host Info
+ * J721E Hosts Info
  *
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
@@ -36,30 +36,33 @@
 #include <socinfo.h>
 
 struct ti_sci_host_info j721e_host_info[] = {
-       [0] = {0, "DMSC", "Secure", "Device Management and Security Control"},
-       [1] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"},
-       [2] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"},
-       [3] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"},
-       [4] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"},
-       [5] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"},
-       [6] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"},
-       [7] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"},
-       [8] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"},
-       [9] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"},
-       [10] = {20, "C7X_0", "Secure", "C7x Context 0 on Main island"},
-       [11] = {21, "C7X_1", "Non Secure", "C7x context 1 on Main island"},
-       [12] = {25, "C6X_0_0", "Secure", "C6x_0 Context 0 on Main island"},
-       [13] = {26, "C6X_0_1", "Non Secure", "C6x_0 context 1 on Main island"},
-       [14] = {27, "C6X_1_0", "Secure", "C6x_1 Context 0 on Main island"},
-       [15] = {28, "C6X_1_1", "Non Secure", "C6x_1 context 1 on Main island"},
-       [16] = {30, "GPU_0", "Non Secure", "RGX context 0 on Main island"},
-       [17] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"},
-       [18] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"},
-       [19] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"},
-       [20] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"},
-       [21] = {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"},
-       [22] = {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"},
-       [23] = {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"},
-       [24] = {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on MCU island"},
-       [25] = {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"},
+       [0] = {0, "DMSC", "Secure", "Security Controller"},
+       [1] = {254, "DM", "Non Secure", "Device Management"},
+       [2] = {3, "MCU_0_R5_0", "Non Secure", "Cortex R5 context 0 on MCU island"},
+       [3] = {4, "MCU_0_R5_1", "Secure", "Cortex R5 context 1 on MCU island(Boot)"},
+       [4] = {5, "MCU_0_R5_2", "Non Secure", "Cortex R5 context 2 on MCU island"},
+       [5] = {6, "MCU_0_R5_3", "Secure", "Cortex R5 context 3 on MCU island"},
+       [6] = {10, "A72_0", "Secure", "Cortex A72 context 0 on Main island"},
+       [7] = {11, "A72_1", "Secure", "Cortex A72 context 1 on Main island"},
+       [8] = {12, "A72_2", "Non Secure", "Cortex A72 context 2 on Main island"},
+       [9] = {13, "A72_3", "Non Secure", "Cortex A72 context 3 on Main island"},
+       [10] = {14, "A72_4", "Non Secure", "Cortex A72 context 4 on Main island"},
+       [11] = {20, "C7X_0", "Secure", "C7x Context 0 on Main island"},
+       [12] = {21, "C7X_1", "Non Secure", "C7x context 1 on Main island"},
+       [13] = {25, "C6X_0_0", "Secure", "C6x_0 Context 0 on Main island"},
+       [14] = {26, "C6X_0_1", "Non Secure", "C6x_0 context 1 on Main island"},
+       [15] = {27, "C6X_1_0", "Secure", "C6x_1 Context 0 on Main island"},
+       [16] = {28, "C6X_1_1", "Non Secure", "C6x_1 context 1 on Main island"},
+       [17] = {30, "GPU_0", "Non Secure", "RGX context 0 on Main island"},
+       [18] = {35, "MAIN_0_R5_0", "Non Secure", "Cortex R5_0 context 0 on Main island"},
+       [19] = {36, "MAIN_0_R5_1", "Secure", "Cortex R5_0 context 1 on Main island"},
+       [20] = {37, "MAIN_0_R5_2", "Non Secure", "Cortex R5_0 context 2 on Main island"},
+       [21] = {38, "MAIN_0_R5_3", "Secure", "Cortex R5_0 context 3 on MCU island"},
+       [22] = {40, "MAIN_1_R5_0", "Non Secure", "Cortex R5_1 context 0 on Main island"},
+       [23] = {41, "MAIN_1_R5_1", "Secure", "Cortex R5_1 context 1 on Main island"},
+       [24] = {42, "MAIN_1_R5_2", "Non Secure", "Cortex R5_1 context 2 on Main island"},
+       [25] = {43, "MAIN_1_R5_3", "Secure", "Cortex R5_1 context 3 on MCU island"},
+       [26] = {50, "ICSSG_0", "Non Secure", "ICSSG context 0 on Main island"},
+       [27] = {250, "DM2DMSC", "Secure", "DM to DMSC communication"},
+       [28] = {251, "DMSC2DM", "Non Secure", "DMSC to DM communication"},
 };