soc: j721e: Fix C66x input clock ids
authorSuman Anna <s-anna@ti.com>
Wed, 11 Nov 2020 16:08:34 +0000 (10:08 -0600)
committerLokesh Vutla <lokeshvutla@ti.com>
Thu, 12 Nov 2020 07:43:43 +0000 (13:13 +0530)
The C66x processor frequencies are incorrectly printed as 0 due to
wrong clock ids used in the processors info. The data is using a
debug clock -GEM_TRC_CLK, but should be using the proper input clock
- GEM_CLKIN_CLK. Update the clock ids for both the C66x devices to
fix this. This new clock id is fixed/added from SYSFW 2020.05 onwards.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
soc/j721e/j721e_processors_info.c

index 193865c079a5183cdbc10016a4db3f508d2e2903..3de526ec41e56dcb0f69f60b0d8d709ebc98568e 100644 (file)
@@ -38,8 +38,8 @@
 struct ti_sci_processors_info j721e_processors_info[] = {
        [0] = {202, 2, 0x20, "A72SS0_CORE0"},
        [1] = {203, 0, 0x21, "A72SS0_CORE1"},
-       [2] = {142, 0, 0x03, "C66SS0_CORE0"},
-       [3] = {143, 0, 0x04, "C66SS1_CORE0"},
+       [2] = {142, 6, 0x03, "C66SS0_CORE0"},
+       [3] = {143, 6, 0x04, "C66SS1_CORE0"},
        [4] = {15, 0, 0x30, "C71SS0"},
        [5] = {250, 0, 0x01, "MCU_R5FSS0_CORE0"},
        [6] = {251, 0, 0x02, "MCU_R5FSS0_CORE1"},