soc: am64x: Add devices info

Add TISCI Devices info for AM64x devices. Data based on sysfw
v2020.08b. Also assign this data to sci_info based on SoC detection.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/Makefile b/Makefile
index 411ad6034f124896b4f7bf90f79496ff0affad67..39131a885599d0d6639bfa94294fbd247af307df 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -106,6 +106,7 @@ AM64XSOURCES =\
              soc/am64x/am64x_host_info.c \
              soc/am64x/am64x_sec_proxy_info.c \
              soc/am64x/am64x_processors_info.c \
+             soc/am64x/am64x_devices_info.c \
 
 COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
 AM65XOBJECTS=  $(AM65XSOURCES:.c=.o)

diff --git a/common/socinfo.c b/common/socinfo.c
index 4fab6d5bce57c043f5f9dc6f0c26ccf6bdc9669c..5a57f1191e812fdd709f2a071b97072da2e19a29 100644 (file)
--- a/common/socinfo.c
+++ b/common/socinfo.c
@@ -64,6 +64,7 @@
 #include <soc/am64x/am64x_host_info.h>
 #include <soc/am64x/am64x_sec_proxy_info.h>
 #include <soc/am64x/am64x_processors_info.h>
+#include <soc/am64x/am64x_devices_info.h>
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_DEVICE_ID    0x43000018
@@ -197,6 +198,8 @@ static void am64x_init(void)
        sci_info->num_sp_threads[MCU_SEC_PROXY] = 0;
        sci_info->processors_info = am64x_processors_info;
        sci_info->num_processors = AM64X_MAX_PROCESSORS_IDS;
+       sci_info->devices_info = am64x_devices_info;
+       sci_info->num_devices = AM64X_MAX_DEVICES;
        soc_info.host_id = 13;
        soc_info.sec_proxy = &k3_lite_sec_proxy_base;
 }

diff --git a/soc/am64x/am64x_devices_info.c b/soc/am64x/am64x_devices_info.c
new file mode 100644 (file)
index 0000000..da132bc
--- /dev/null
+++ b/soc/am64x/am64x_devices_info.c
@@ -0,0 +1,198 @@
+/*
+ * AM64X Devices Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_devices_info am64x_devices_info[] = {
+       [0] = {0, "AM64X_DEV_ADC0"},
+       [1] = {1, "AM64X_DEV_CMP_EVENT_INTROUTER0"},
+       [2] = {2, "AM64X_DEV_DBGSUSPENDROUTER0"},
+       [3] = {3, "AM64X_DEV_MAIN_GPIOMUX_INTROUTER0"},
+       [4] = {5, "AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0"},
+       [5] = {6, "AM64X_DEV_TIMESYNC_EVENT_INTROUTER0"},
+       [6] = {7, "AM64X_DEV_MCU_M4FSS0"},
+       [7] = {9, "AM64X_DEV_MCU_M4FSS0_CORE0"},
+       [8] = {13, "AM64X_DEV_CPSW0"},
+       [9] = {14, "AM64X_DEV_CPT2_AGGR0"},
+       [10] = {15, "AM64X_DEV_STM0"},
+       [11] = {16, "AM64X_DEV_DCC0"},
+       [12] = {17, "AM64X_DEV_DCC1"},
+       [13] = {18, "AM64X_DEV_DCC2"},
+       [14] = {19, "AM64X_DEV_DCC3"},
+       [15] = {20, "AM64X_DEV_DCC4"},
+       [16] = {21, "AM64X_DEV_DCC5"},
+       [17] = {22, "AM64X_DEV_DMSC0"},
+       [18] = {23, "AM64X_DEV_MCU_DCC0"},
+       [19] = {24, "AM64X_DEV_DEBUGSS_WRAP0"},
+       [20] = {25, "AM64X_DEV_DMASS0"},
+       [21] = {26, "AM64X_DEV_DMASS0_BCDMA_0"},
+       [22] = {27, "AM64X_DEV_DMASS0_CBASS_0"},
+       [23] = {28, "AM64X_DEV_DMASS0_INTAGGR_0"},
+       [24] = {29, "AM64X_DEV_DMASS0_IPCSS_0"},
+       [25] = {30, "AM64X_DEV_DMASS0_PKTDMA_0"},
+       [26] = {31, "AM64X_DEV_DMASS0_PSILCFG_0"},
+       [27] = {32, "AM64X_DEV_DMASS0_PSILSS_0"},
+       [28] = {33, "AM64X_DEV_DMASS0_RINGACC_0"},
+       [29] = {35, "AM64X_DEV_MCU_TIMER0"},
+       [30] = {36, "AM64X_DEV_TIMER0"},
+       [31] = {37, "AM64X_DEV_TIMER1"},
+       [32] = {38, "AM64X_DEV_TIMER2"},
+       [33] = {39, "AM64X_DEV_TIMER3"},
+       [34] = {40, "AM64X_DEV_TIMER4"},
+       [35] = {41, "AM64X_DEV_TIMER5"},
+       [36] = {42, "AM64X_DEV_TIMER6"},
+       [37] = {43, "AM64X_DEV_TIMER7"},
+       [38] = {44, "AM64X_DEV_TIMER8"},
+       [39] = {45, "AM64X_DEV_TIMER9"},
+       [40] = {46, "AM64X_DEV_TIMER10"},
+       [41] = {47, "AM64X_DEV_TIMER11"},
+       [42] = {48, "AM64X_DEV_MCU_TIMER1"},
+       [43] = {49, "AM64X_DEV_MCU_TIMER2"},
+       [44] = {50, "AM64X_DEV_MCU_TIMER3"},
+       [45] = {51, "AM64X_DEV_ECAP0"},
+       [46] = {52, "AM64X_DEV_ECAP1"},
+       [47] = {53, "AM64X_DEV_ECAP2"},
+       [48] = {54, "AM64X_DEV_ELM0"},
+       [49] = {55, "AM64X_DEV_EMIF_DATA_0_VD"},
+       [50] = {57, "AM64X_DEV_MMCSD0"},
+       [51] = {58, "AM64X_DEV_MMCSD1"},
+       [52] = {59, "AM64X_DEV_EQEP0"},
+       [53] = {60, "AM64X_DEV_EQEP1"},
+       [54] = {61, "AM64X_DEV_GTC0"},
+       [55] = {62, "AM64X_DEV_EQEP2"},
+       [56] = {63, "AM64X_DEV_ESM0"},
+       [57] = {64, "AM64X_DEV_MCU_ESM0"},
+       [58] = {65, "AM64X_DEV_FSIRX0"},
+       [59] = {66, "AM64X_DEV_FSIRX1"},
+       [60] = {67, "AM64X_DEV_FSIRX2"},
+       [61] = {68, "AM64X_DEV_FSIRX3"},
+       [62] = {69, "AM64X_DEV_FSIRX4"},
+       [63] = {70, "AM64X_DEV_FSIRX5"},
+       [64] = {71, "AM64X_DEV_FSITX0"},
+       [65] = {72, "AM64X_DEV_FSITX1"},
+       [66] = {73, "AM64X_DEV_FSS0"},
+       [67] = {74, "AM64X_DEV_FSS0_FSAS_0"},
+       [68] = {75, "AM64X_DEV_FSS0_OSPI_0"},
+       [69] = {76, "AM64X_DEV_GICSS0"},
+       [70] = {77, "AM64X_DEV_GPIO0"},
+       [71] = {78, "AM64X_DEV_GPIO1"},
+       [72] = {79, "AM64X_DEV_MCU_GPIO0"},
+       [73] = {80, "AM64X_DEV_GPMC0"},
+       [74] = {81, "AM64X_DEV_PRU_ICSSG0"},
+       [75] = {82, "AM64X_DEV_PRU_ICSSG1"},
+       [76] = {83, "AM64X_DEV_LED0"},
+       [77] = {84, "AM64X_DEV_CPTS0"},
+       [78] = {85, "AM64X_DEV_DDPA0"},
+       [79] = {86, "AM64X_DEV_EPWM0"},
+       [80] = {87, "AM64X_DEV_EPWM1"},
+       [81] = {88, "AM64X_DEV_EPWM2"},
+       [82] = {89, "AM64X_DEV_EPWM3"},
+       [83] = {90, "AM64X_DEV_EPWM4"},
+       [84] = {91, "AM64X_DEV_EPWM5"},
+       [85] = {92, "AM64X_DEV_EPWM6"},
+       [86] = {93, "AM64X_DEV_EPWM7"},
+       [87] = {94, "AM64X_DEV_EPWM8"},
+       [88] = {95, "AM64X_DEV_VTM0"},
+       [89] = {96, "AM64X_DEV_MAILBOX0"},
+       [90] = {97, "AM64X_DEV_MAIN2MCU_VD"},
+       [91] = {98, "AM64X_DEV_MCAN0"},
+       [92] = {99, "AM64X_DEV_MCAN1"},
+       [93] = {100, "AM64X_DEV_MCU_MCRC64_0"},
+       [94] = {101, "AM64X_DEV_MCU2MAIN_VD"},
+       [95] = {102, "AM64X_DEV_I2C0"},
+       [96] = {103, "AM64X_DEV_I2C1"},
+       [97] = {104, "AM64X_DEV_I2C2"},
+       [98] = {105, "AM64X_DEV_I2C3"},
+       [99] = {106, "AM64X_DEV_MCU_I2C0"},
+       [100] = {107, "AM64X_DEV_MCU_I2C1"},
+       [101] = {108, "AM64X_DEV_MSRAM_256K0"},
+       [102] = {109, "AM64X_DEV_MSRAM_256K1"},
+       [103] = {110, "AM64X_DEV_MSRAM_256K2"},
+       [104] = {111, "AM64X_DEV_MSRAM_256K3"},
+       [105] = {112, "AM64X_DEV_MSRAM_256K4"},
+       [106] = {113, "AM64X_DEV_MSRAM_256K5"},
+       [107] = {114, "AM64X_DEV_PCIE0"},
+       [108] = {115, "AM64X_DEV_POSTDIV1_16FFT1"},
+       [109] = {116, "AM64X_DEV_POSTDIV4_16FF0"},
+       [110] = {117, "AM64X_DEV_POSTDIV4_16FF2"},
+       [111] = {118, "AM64X_DEV_PSRAMECC0"},
+       [112] = {119, "AM64X_DEV_R5FSS0"},
+       [113] = {120, "AM64X_DEV_R5FSS1"},
+       [114] = {121, "AM64X_DEV_R5FSS0_CORE0"},
+       [115] = {122, "AM64X_DEV_R5FSS0_CORE1"},
+       [116] = {123, "AM64X_DEV_R5FSS1_CORE0"},
+       [117] = {124, "AM64X_DEV_R5FSS1_CORE1"},
+       [118] = {125, "AM64X_DEV_RTI0"},
+       [119] = {126, "AM64X_DEV_RTI1"},
+       [120] = {127, "AM64X_DEV_RTI8"},
+       [121] = {128, "AM64X_DEV_RTI9"},
+       [122] = {130, "AM64X_DEV_RTI10"},
+       [123] = {131, "AM64X_DEV_RTI11"},
+       [124] = {132, "AM64X_DEV_MCU_RTI0"},
+       [125] = {133, "AM64X_DEV_SA2_UL0"},
+       [126] = {134, "AM64X_DEV_COMPUTE_CLUSTER0"},
+       [127] = {135, "AM64X_DEV_A53SS0_CORE_0"},
+       [128] = {136, "AM64X_DEV_A53SS0_CORE_1"},
+       [129] = {137, "AM64X_DEV_A53SS0"},
+       [130] = {138, "AM64X_DEV_DDR16SS0"},
+       [131] = {139, "AM64X_DEV_PSC0"},
+       [132] = {140, "AM64X_DEV_MCU_PSC0"},
+       [133] = {141, "AM64X_DEV_MCSPI0"},
+       [134] = {142, "AM64X_DEV_MCSPI1"},
+       [135] = {143, "AM64X_DEV_MCSPI2"},
+       [136] = {144, "AM64X_DEV_MCSPI3"},
+       [137] = {145, "AM64X_DEV_MCSPI4"},
+       [138] = {146, "AM64X_DEV_UART0"},
+       [139] = {147, "AM64X_DEV_MCU_MCSPI0"},
+       [140] = {148, "AM64X_DEV_MCU_MCSPI1"},
+       [141] = {149, "AM64X_DEV_MCU_UART0"},
+       [142] = {150, "AM64X_DEV_SPINLOCK0"},
+       [143] = {151, "AM64X_DEV_TIMERMGR0"},
+       [144] = {152, "AM64X_DEV_UART1"},
+       [145] = {153, "AM64X_DEV_UART2"},
+       [146] = {154, "AM64X_DEV_UART3"},
+       [147] = {155, "AM64X_DEV_UART4"},
+       [148] = {156, "AM64X_DEV_UART5"},
+       [149] = {157, "AM64X_DEV_BOARD0"},
+       [150] = {158, "AM64X_DEV_UART6"},
+       [151] = {160, "AM64X_DEV_MCU_UART1"},
+       [152] = {161, "AM64X_DEV_USB0"},
+       [153] = {162, "AM64X_DEV_SERDES_10G0"},
+       [154] = {163, "AM64X_DEV_PBIST0"},
+       [155] = {164, "AM64X_DEV_PBIST1"},
+       [156] = {165, "AM64X_DEV_PBIST2"},
+       [157] = {166, "AM64X_DEV_PBIST3"},
+       [158] = {167, "AM64X_DEV_COMPUTE_CLUSTER0_PBIST_0"},
+};

diff --git a/soc/am64x/am64x_devices_info.h b/soc/am64x/am64x_devices_info.h
new file mode 100644 (file)
index 0000000..bb05875
--- /dev/null
+++ b/soc/am64x/am64x_devices_info.h
@@ -0,0 +1,42 @@
+/*
+ * AM64X Devices Info
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __AM64X_DEVICES_INFO_H
+#define __AM64X_DEVICES_INFO_H
+
+#define AM64X_MAX_DEVICES      159
+
+extern struct ti_sci_devices_info am64x_devices_info[];
+
+#endif /* __AM64X_DEVICES_INFO_H */
\ No newline at end of file