soc: j721e: Add clocks information
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 22 Aug 2019 09:52:46 +0000 (15:22 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Sun, 25 Aug 2019 03:14:04 +0000 (08:44 +0530)
Add TISCI cocks information for J721e devices

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Makefile
common/socinfo.c
include/soc/j721e/j721e_clocks_info.h [new file with mode: 0644]
soc/j721e/j721e_clocks_info.c [new file with mode: 0644]

index cc8b74d6b0d1c3982983bab0d4e42a8733de5b42..67eb10d2b06701bef2dc5668ea1092b2a6ad4b24 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -77,7 +77,8 @@ J721ESOURCES =\
              soc/j721e/j721e_host_info.c \
              soc/j721e/j721e_sec_proxy_info.c \
              soc/j721e/j721e_processors_info.c \
-             soc/j721e/j721e_devices_info.c
+             soc/j721e/j721e_devices_info.c \
+             soc/j721e/j721e_clocks_info.c
 
 COMMONOBJECTS= $(COMMONSOURCES:.c=.o)
 AM65XOBJECTS=  $(AM65XSOURCES:.c=.o)
index 96495acfc39e3a96545d3e70a179a33c95db2568..d2b60d8fccb8735bcc14305383424e4eac00eae1 100644 (file)
@@ -46,6 +46,7 @@
 #include <soc/j721e/j721e_sec_proxy_info.h>
 #include <soc/j721e/j721e_processors_info.h>
 #include <soc/j721e/j721e_devices_info.h>
+#include <soc/j721e/j721e_clocks_info.h>
 
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_DEVICE_ID    0x43000018
@@ -117,6 +118,8 @@ static void j721e_init(void)
        sci_info->num_processors = J721E_MAX_PROCESSORS_IDS;
        sci_info->devices_info = j721e_devices_info;
        sci_info->num_devices = J721E_MAX_DEVICES;
+       sci_info->clocks_info = j721e_clocks_info;
+       sci_info->num_clocks = J721E_MAX_CLOCKS;
 }
 
 int soc_init(void)
diff --git a/include/soc/j721e/j721e_clocks_info.h b/include/soc/j721e/j721e_clocks_info.h
new file mode 100644 (file)
index 0000000..33a0bd2
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * SoC Clocks Info
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __J721E_CLOCKS_INFO
+#define __J721E_CLOCKS_INFO
+
+#define J721E_MAX_CLOCKS       2991
+
+extern struct ti_sci_clocks_info j721e_clocks_info[];
+#endif
diff --git a/soc/j721e/j721e_clocks_info.c b/soc/j721e/j721e_clocks_info.c
new file mode 100644 (file)
index 0000000..57d741b
--- /dev/null
@@ -0,0 +1,3030 @@
+/*
+ * SoC Clocks Info
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tisci.h>
+#include <socinfo.h>
+
+struct ti_sci_clocks_info j721e_clocks_info[] = {
+        [0] = {4, 0, "DEV_A72SS0_CLUSTER_CLK", "Input clock"},
+        [1] = {202, 0, "DEV_A72SS0_CORE0_PLL_CTRL_CLK", "Input clock"},
+        [2] = {202, 1, "DEV_A72SS0_CORE0_MSMC_CLK", "Input clock"},
+        [3] = {202, 2, "DEV_A72SS0_CORE0_ARM_CLK_CLK", "Input clock"},
+        [4] = {203, 0, "DEV_A72SS0_CORE1_ARM_CLK_CLK", "Input clock"},
+        [5] = {139, 39, "DEV_AASRC0_RX1_SYNC_0", "Input muxed clock"},
+        [6] = {139, 40, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [7] = {139, 41, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [8] = {139, 42, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [9] = {139, 43, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [10] = {139, 44, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [11] = {139, 45, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [12] = {139, 46, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [13] = {139, 47, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [14] = {139, 48, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [15] = {139, 49, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [16] = {139, 50, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [17] = {139, 51, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [18] = {139, 52, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [19] = {139, 53, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [20] = {139, 54, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [21] = {139, 55, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [22] = {139, 56, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [23] = {139, 57, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [24] = {139, 58, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [25] = {139, 59, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [26] = {139, 60, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [27] = {139, 61, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [28] = {139, 62, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [29] = {139, 63, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [30] = {139, 64, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [31] = {139, 65, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [32] = {139, 66, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [33] = {139, 67, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [34] = {139, 68, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [35] = {139, 69, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [36] = {139, 70, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [37] = {139, 71, "DEV_AASRC0_RX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [38] = {139, 72, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [39] = {139, 73, "DEV_AASRC0_RX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [40] = {139, 74, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [41] = {139, 75, "DEV_AASRC0_RX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX1_SYNC_0"},
+        [42] = {139, 1, "DEV_AASRC0_VBUSP_CLK", "Input clock"},
+        [43] = {139, 2, "DEV_AASRC0_RX0_SYNC_0", "Input muxed clock"},
+        [44] = {139, 3, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [45] = {139, 4, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [46] = {139, 5, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [47] = {139, 6, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [48] = {139, 7, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [49] = {139, 8, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [50] = {139, 9, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [51] = {139, 10, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [52] = {139, 11, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [53] = {139, 12, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [54] = {139, 13, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [55] = {139, 14, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [56] = {139, 15, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [57] = {139, 16, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [58] = {139, 17, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [59] = {139, 18, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [60] = {139, 19, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [61] = {139, 20, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [62] = {139, 21, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [63] = {139, 22, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [64] = {139, 23, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [65] = {139, 24, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [66] = {139, 25, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [67] = {139, 26, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [68] = {139, 27, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [69] = {139, 28, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [70] = {139, 29, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [71] = {139, 30, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [72] = {139, 31, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [73] = {139, 32, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [74] = {139, 33, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [75] = {139, 34, "DEV_AASRC0_RX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [76] = {139, 35, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [77] = {139, 36, "DEV_AASRC0_RX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [78] = {139, 37, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [79] = {139, 38, "DEV_AASRC0_RX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX0_SYNC_0"},
+        [80] = {139, 0, "DEV_AASRC0_SYS_CLK", "Input clock"},
+        [81] = {139, 261, "DEV_AASRC0_TX3_SYNC_0", "Input muxed clock"},
+        [82] = {139, 262, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [83] = {139, 263, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [84] = {139, 264, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [85] = {139, 265, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [86] = {139, 266, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [87] = {139, 267, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [88] = {139, 268, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [89] = {139, 269, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [90] = {139, 270, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [91] = {139, 271, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [92] = {139, 272, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [93] = {139, 273, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [94] = {139, 274, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [95] = {139, 275, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [96] = {139, 276, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [97] = {139, 277, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [98] = {139, 278, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [99] = {139, 279, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [100] = {139, 280, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [101] = {139, 281, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [102] = {139, 282, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [103] = {139, 283, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [104] = {139, 284, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [105] = {139, 285, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [106] = {139, 286, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [107] = {139, 287, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [108] = {139, 288, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [109] = {139, 289, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [110] = {139, 290, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [111] = {139, 291, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [112] = {139, 292, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [113] = {139, 293, "DEV_AASRC0_TX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [114] = {139, 294, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [115] = {139, 295, "DEV_AASRC0_TX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [116] = {139, 296, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [117] = {139, 297, "DEV_AASRC0_TX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX3_SYNC_0"},
+        [118] = {139, 76, "DEV_AASRC0_RX2_SYNC_0", "Input muxed clock"},
+        [119] = {139, 77, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [120] = {139, 78, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [121] = {139, 79, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [122] = {139, 80, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [123] = {139, 81, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [124] = {139, 82, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [125] = {139, 83, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [126] = {139, 84, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [127] = {139, 85, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [128] = {139, 86, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [129] = {139, 87, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [130] = {139, 88, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [131] = {139, 89, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [132] = {139, 90, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [133] = {139, 91, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [134] = {139, 92, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [135] = {139, 93, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [136] = {139, 94, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [137] = {139, 95, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [138] = {139, 96, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [139] = {139, 97, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [140] = {139, 98, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [141] = {139, 99, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [142] = {139, 100, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [143] = {139, 101, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [144] = {139, 102, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [145] = {139, 103, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [146] = {139, 104, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [147] = {139, 105, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [148] = {139, 106, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [149] = {139, 107, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [150] = {139, 108, "DEV_AASRC0_RX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [151] = {139, 109, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [152] = {139, 110, "DEV_AASRC0_RX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [153] = {139, 111, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [154] = {139, 112, "DEV_AASRC0_RX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX2_SYNC_0"},
+        [155] = {139, 150, "DEV_AASRC0_TX0_SYNC_0", "Input muxed clock"},
+        [156] = {139, 151, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [157] = {139, 152, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [158] = {139, 153, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [159] = {139, 154, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [160] = {139, 155, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [161] = {139, 156, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [162] = {139, 157, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [163] = {139, 158, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [164] = {139, 159, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [165] = {139, 160, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [166] = {139, 161, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [167] = {139, 162, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [168] = {139, 163, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [169] = {139, 164, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [170] = {139, 165, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [171] = {139, 166, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [172] = {139, 167, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [173] = {139, 168, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [174] = {139, 169, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [175] = {139, 170, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [176] = {139, 171, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [177] = {139, 172, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [178] = {139, 173, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [179] = {139, 174, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [180] = {139, 175, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [181] = {139, 176, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [182] = {139, 177, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [183] = {139, 178, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [184] = {139, 179, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [185] = {139, 180, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [186] = {139, 181, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [187] = {139, 182, "DEV_AASRC0_TX0_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [188] = {139, 183, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [189] = {139, 184, "DEV_AASRC0_TX0_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [190] = {139, 185, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [191] = {139, 186, "DEV_AASRC0_TX0_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX0_SYNC_0"},
+        [192] = {139, 113, "DEV_AASRC0_RX3_SYNC_0", "Input muxed clock"},
+        [193] = {139, 114, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [194] = {139, 115, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [195] = {139, 116, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [196] = {139, 117, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [197] = {139, 118, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [198] = {139, 119, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [199] = {139, 120, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [200] = {139, 121, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [201] = {139, 122, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [202] = {139, 123, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [203] = {139, 124, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [204] = {139, 125, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSR_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [205] = {139, 126, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [206] = {139, 127, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [207] = {139, 128, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [208] = {139, 129, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [209] = {139, 130, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [210] = {139, 131, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [211] = {139, 132, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [212] = {139, 133, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [213] = {139, 134, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [214] = {139, 135, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [215] = {139, 136, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [216] = {139, 137, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [217] = {139, 138, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [218] = {139, 139, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [219] = {139, 140, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [220] = {139, 141, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [221] = {139, 142, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [222] = {139, 143, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [223] = {139, 144, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [224] = {139, 145, "DEV_AASRC0_RX3_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [225] = {139, 146, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [226] = {139, 147, "DEV_AASRC0_RX3_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [227] = {139, 148, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [228] = {139, 149, "DEV_AASRC0_RX3_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_RX3_SYNC_0"},
+        [229] = {139, 187, "DEV_AASRC0_TX1_SYNC_0", "Input muxed clock"},
+        [230] = {139, 188, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [231] = {139, 189, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [232] = {139, 190, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [233] = {139, 191, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [234] = {139, 192, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [235] = {139, 193, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [236] = {139, 194, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [237] = {139, 195, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [238] = {139, 196, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [239] = {139, 197, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [240] = {139, 198, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [241] = {139, 199, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [242] = {139, 200, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [243] = {139, 201, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [244] = {139, 202, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [245] = {139, 203, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [246] = {139, 204, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [247] = {139, 205, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [248] = {139, 206, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [249] = {139, 207, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [250] = {139, 208, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [251] = {139, 209, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [252] = {139, 210, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [253] = {139, 211, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [254] = {139, 212, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [255] = {139, 213, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [256] = {139, 214, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [257] = {139, 215, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [258] = {139, 216, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [259] = {139, 217, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [260] = {139, 218, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [261] = {139, 219, "DEV_AASRC0_TX1_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [262] = {139, 220, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [263] = {139, 221, "DEV_AASRC0_TX1_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [264] = {139, 222, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [265] = {139, 223, "DEV_AASRC0_TX1_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX1_SYNC_0"},
+        [266] = {139, 224, "DEV_AASRC0_TX2_SYNC_0", "Input muxed clock"},
+        [267] = {139, 225, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [268] = {139, 226, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [269] = {139, 227, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [270] = {139, 228, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [271] = {139, 229, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [272] = {139, 230, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [273] = {139, 231, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [274] = {139, 232, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [275] = {139, 233, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [276] = {139, 234, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [277] = {139, 235, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [278] = {139, 236, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [279] = {139, 237, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [280] = {139, 238, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [281] = {139, 239, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [282] = {139, 240, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [283] = {139, 241, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [284] = {139, 242, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [285] = {139, 243, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [286] = {139, 244, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [287] = {139, 245, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [288] = {139, 246, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [289] = {139, 247, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [290] = {139, 248, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [291] = {139, 249, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [292] = {139, 250, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [293] = {139, 251, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [294] = {139, 252, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [295] = {139, 253, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [296] = {139, 254, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [297] = {139, 255, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [298] = {139, 256, "DEV_AASRC0_TX2_SYNC_0_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [299] = {139, 257, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT0", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [300] = {139, 258, "DEV_AASRC0_TX2_SYNC_0_PARENT_MCU_ADC_CLK_SEL_OUT1", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [301] = {139, 259, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [302] = {139, 260, "DEV_AASRC0_TX2_SYNC_0_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_AASRC0_TX2_SYNC_0"},
+        [303] = {2, 0, "DEV_ATL0_VBUS_CLK", "Input clock"},
+        [304] = {2, 1, "DEV_ATL0_ATL_CLK", "Input muxed clock"},
+        [305] = {2, 2, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+        [306] = {2, 3, "DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+        [307] = {2, 4, "DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+        [308] = {2, 5, "DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+        [309] = {2, 6, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+        [310] = {2, 7, "DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_ATL0_ATL_CLK"},
+        [311] = {2, 8, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1", "Output clock"},
+        [312] = {2, 9, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_0", "Output clock"},
+        [313] = {2, 10, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3", "Output clock"},
+        [314] = {2, 11, "DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2", "Output clock"},
+        [315] = {157, 282, "DEV_BOARD0_MCASP10_ACLKX_IN", "Input clock"},
+        [316] = {157, 52, "DEV_BOARD0_DSI_TXCLKP_IN", "Input clock"},
+        [317] = {157, 12, "DEV_BOARD0_SPI7_CLK_IN", "Input clock"},
+        [318] = {157, 4, "DEV_BOARD0_SPI2_CLK_IN", "Input clock"},
+        [319] = {157, 46, "DEV_BOARD0_MCU_I3C0_SCL_IN", "Input clock"},
+        [320] = {157, 51, "DEV_BOARD0_MCU_HYPERBUS0_CKN_IN", "Input clock"},
+        [321] = {157, 256, "DEV_BOARD0_MCASP6_ACLKX_IN", "Input clock"},
+        [322] = {157, 279, "DEV_BOARD0_MCASP10_ACLKR_IN", "Input clock"},
+        [323] = {157, 2, "DEV_BOARD0_SPI1_CLK_IN", "Input clock"},
+        [324] = {157, 152, "DEV_BOARD0_MCU_OBSCLK0_IN", "Input muxed clock"},
+        [325] = {157, 153, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+        [326] = {157, 154, "DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN"},
+        [327] = {157, 6, "DEV_BOARD0_SPI3_CLK_IN", "Input clock"},
+        [328] = {157, 223, "DEV_BOARD0_MCASP1_ACLKR_IN", "Input clock"},
+        [329] = {157, 371, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN", "Input muxed clock"},
+        [330] = {157, 372, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [331] = {157, 373, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [332] = {157, 374, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [333] = {157, 375, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [334] = {157, 376, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [335] = {157, 377, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [336] = {157, 378, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [337] = {157, 379, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [338] = {157, 380, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [339] = {157, 381, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [340] = {157, 382, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [341] = {157, 383, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [342] = {157, 384, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [343] = {157, 385, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [344] = {157, 386, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [345] = {157, 387, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [346] = {157, 388, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [347] = {157, 389, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [348] = {157, 390, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [349] = {157, 391, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [350] = {157, 392, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [351] = {157, 393, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [352] = {157, 394, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [353] = {157, 395, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [354] = {157, 396, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [355] = {157, 397, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [356] = {157, 398, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [357] = {157, 399, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [358] = {157, 400, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [359] = {157, 401, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [360] = {157, 404, "DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN"},
+        [361] = {157, 89, "DEV_BOARD0_UFS0_REF_CLK_IN", "Input clock"},
+        [362] = {157, 172, "DEV_BOARD0_CLKOUT_IN", "Input muxed clock"},
+        [363] = {157, 173, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
+        [364] = {157, 174, "DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10", "Parent input clock option to DEV_BOARD0_CLKOUT_IN"},
+        [365] = {157, 146, "DEV_BOARD0_OBSCLK1_IN", "Input muxed clock"},
+        [366] = {157, 147, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+        [367] = {157, 148, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK7", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+        [368] = {157, 149, "DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK3", "Parent input clock option to DEV_BOARD0_OBSCLK1_IN"},
+        [369] = {157, 53, "DEV_BOARD0_DSI_TXCLKN_IN", "Input clock"},
+        [370] = {157, 54, "DEV_BOARD0_PRG0_MDIO0_MDC_IN", "Input clock"},
+        [371] = {157, 262, "DEV_BOARD0_MCASP7_ACLKX_IN", "Input clock"},
+        [372] = {157, 259, "DEV_BOARD0_MCASP7_ACLKR_IN", "Input clock"},
+        [373] = {157, 92, "DEV_BOARD0_DDR0_CK0_N_IN", "Input clock"},
+        [374] = {157, 232, "DEV_BOARD0_MCASP2_ACLKX_IN", "Input clock"},
+        [375] = {157, 50, "DEV_BOARD0_MCU_HYPERBUS0_CK_IN", "Input clock"},
+        [376] = {157, 99, "DEV_BOARD0_MMC0_CLK_IN", "Input clock"},
+        [377] = {157, 58, "DEV_BOARD0_PRG0_RGMII2_TXC_IN", "Input clock"},
+        [378] = {157, 100, "DEV_BOARD0_MMC1_CLK_IN", "Input clock"},
+        [379] = {157, 229, "DEV_BOARD0_MCASP2_ACLKR_IN", "Input clock"},
+        [380] = {157, 101, "DEV_BOARD0_MMC2_CLK_IN", "Input clock"},
+        [381] = {157, 175, "DEV_BOARD0_MCU_CLKOUT0_IN", "Input muxed clock"},
+        [382] = {157, 176, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK4", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+        [383] = {157, 177, "DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK9", "Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN"},
+        [384] = {157, 217, "DEV_BOARD0_MCASP0_ACLKR_IN", "Input clock"},
+        [385] = {157, 83, "DEV_BOARD0_MCU_MDIO0_MDC_IN", "Input clock"},
+        [386] = {157, 61, "DEV_BOARD0_PRG1_MDIO0_MDC_IN", "Input clock"},
+        [387] = {157, 336, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN", "Input muxed clock"},
+        [388] = {157, 337, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [389] = {157, 338, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [390] = {157, 339, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [391] = {157, 340, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [392] = {157, 341, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [393] = {157, 342, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [394] = {157, 343, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [395] = {157, 344, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [396] = {157, 345, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [397] = {157, 346, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [398] = {157, 347, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [399] = {157, 348, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [400] = {157, 349, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [401] = {157, 350, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [402] = {157, 351, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [403] = {157, 352, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [404] = {157, 353, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [405] = {157, 354, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [406] = {157, 355, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [407] = {157, 356, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [408] = {157, 357, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [409] = {157, 358, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [410] = {157, 359, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [411] = {157, 360, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [412] = {157, 361, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [413] = {157, 362, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [414] = {157, 363, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [415] = {157, 364, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [416] = {157, 365, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [417] = {157, 366, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [418] = {157, 369, "DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN"},
+        [419] = {157, 55, "DEV_BOARD0_PRG0_RGMII1_TXC_IN", "Input clock"},
+        [420] = {157, 272, "DEV_BOARD0_MCASP9_ACLKR_IN", "Input clock"},
+        [421] = {157, 18, "DEV_BOARD0_MCU_OSPI0_CLK_IN", "Input clock"},
+        [422] = {157, 62, "DEV_BOARD0_PRG1_RGMII1_TXC_IN", "Input clock"},
+        [423] = {157, 170, "DEV_BOARD0_MCU_SYSCLKOUT0_IN", "Input clock"},
+        [424] = {157, 65, "DEV_BOARD0_PRG1_RGMII2_TXC_IN", "Input clock"},
+        [425] = {157, 288, "DEV_BOARD0_MCASP11_ACLKX_IN", "Input clock"},
+        [426] = {157, 44, "DEV_BOARD0_I3C0_SCL_IN", "Input clock"},
+        [427] = {157, 91, "DEV_BOARD0_DDR0_CK0_IN", "Input clock"},
+        [428] = {157, 10, "DEV_BOARD0_SPI6_CLK_IN", "Input clock"},
+        [429] = {157, 42, "DEV_BOARD0_WKUP_I2C0_SCL_IN", "Input clock"},
+        [430] = {157, 16, "DEV_BOARD0_MCU_SPI1_CLK_IN", "Input clock"},
+        [431] = {157, 250, "DEV_BOARD0_MCASP5_ACLKX_IN", "Input clock"},
+        [432] = {157, 253, "DEV_BOARD0_MCASP6_ACLKR_IN", "Input clock"},
+        [433] = {157, 226, "DEV_BOARD0_MCASP1_ACLKX_IN", "Input clock"},
+        [434] = {157, 406, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN", "Input muxed clock"},
+        [435] = {157, 407, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [436] = {157, 408, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [437] = {157, 409, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [438] = {157, 410, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [439] = {157, 411, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [440] = {157, 412, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [441] = {157, 413, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [442] = {157, 414, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [443] = {157, 415, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [444] = {157, 416, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [445] = {157, 417, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [446] = {157, 418, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [447] = {157, 419, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [448] = {157, 420, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [449] = {157, 421, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [450] = {157, 422, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [451] = {157, 423, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [452] = {157, 424, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [453] = {157, 425, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [454] = {157, 426, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [455] = {157, 427, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [456] = {157, 428, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [457] = {157, 429, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [458] = {157, 430, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [459] = {157, 431, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [460] = {157, 432, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [461] = {157, 433, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [462] = {157, 434, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [463] = {157, 435, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [464] = {157, 436, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [465] = {157, 439, "DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN"},
+        [466] = {157, 14, "DEV_BOARD0_MCU_SPI0_CLK_IN", "Input clock"},
+        [467] = {157, 301, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN", "Input muxed clock"},
+        [468] = {157, 302, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [469] = {157, 303, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [470] = {157, 304, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [471] = {157, 305, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [472] = {157, 306, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [473] = {157, 307, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [474] = {157, 308, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [475] = {157, 309, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [476] = {157, 310, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [477] = {157, 311, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [478] = {157, 312, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [479] = {157, 313, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [480] = {157, 314, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [481] = {157, 315, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [482] = {157, 316, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [483] = {157, 317, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [484] = {157, 318, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [485] = {157, 319, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [486] = {157, 320, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [487] = {157, 321, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [488] = {157, 322, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [489] = {157, 323, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [490] = {157, 324, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [491] = {157, 325, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [492] = {157, 326, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [493] = {157, 327, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [494] = {157, 328, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [495] = {157, 329, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [496] = {157, 330, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [497] = {157, 331, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [498] = {157, 334, "DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT", "Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN"},
+        [499] = {157, 84, "DEV_BOARD0_MCU_RGMII1_TXC_IN", "Input clock"},
+        [500] = {157, 38, "DEV_BOARD0_MCU_I2C0_SCL_IN", "Input clock"},
+        [501] = {157, 269, "DEV_BOARD0_MCASP8_ACLKX_IN", "Input clock"},
+        [502] = {157, 102, "DEV_BOARD0_GPMC0_CLK_IN", "Input clock"},
+        [503] = {157, 244, "DEV_BOARD0_MCASP4_ACLKX_IN", "Input clock"},
+        [504] = {157, 285, "DEV_BOARD0_MCASP11_ACLKR_IN", "Input clock"},
+        [505] = {157, 171, "DEV_BOARD0_TRC_CLK_IN", "Input clock"},
+        [506] = {157, 109, "DEV_BOARD0_VOUT1_PCLK_IN", "Input clock"},
+        [507] = {157, 275, "DEV_BOARD0_MCASP9_ACLKX_IN", "Input clock"},
+        [508] = {157, 247, "DEV_BOARD0_MCASP5_ACLKR_IN", "Input clock"},
+        [509] = {157, 22, "DEV_BOARD0_MCU_OSPI1_LBCLKO_IN", "Input clock"},
+        [510] = {157, 111, "DEV_BOARD0_VOUT2_PCLK_IN", "Input clock"},
+        [511] = {157, 48, "DEV_BOARD0_MCU_I3C1_SCL_IN", "Input clock"},
+        [512] = {157, 169, "DEV_BOARD0_SYSCLKOUT0_IN", "Input clock"},
+        [513] = {157, 8, "DEV_BOARD0_SPI5_CLK_IN", "Input clock"},
+        [514] = {157, 238, "DEV_BOARD0_MCASP3_ACLKX_IN", "Input clock"},
+        [515] = {157, 265, "DEV_BOARD0_MCASP8_ACLKR_IN", "Input clock"},
+        [516] = {157, 68, "DEV_BOARD0_MDIO0_MDC_IN", "Input clock"},
+        [517] = {157, 241, "DEV_BOARD0_MCASP4_ACLKR_IN", "Input clock"},
+        [518] = {157, 21, "DEV_BOARD0_MCU_OSPI1_CLK_IN", "Input clock"},
+        [519] = {157, 0, "DEV_BOARD0_SPI0_CLK_IN", "Input clock"},
+        [520] = {157, 104, "DEV_BOARD0_GPMC0_FCLK_MUX_IN", "Input clock"},
+        [521] = {157, 19, "DEV_BOARD0_MCU_OSPI0_LBCLKO_IN", "Input clock"},
+        [522] = {157, 220, "DEV_BOARD0_MCASP0_ACLKX_IN", "Input clock"},
+        [523] = {157, 113, "DEV_BOARD0_OBSCLK0_IN", "Input clock"},
+        [524] = {157, 114, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [525] = {157, 115, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [526] = {157, 116, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [527] = {157, 117, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [528] = {157, 118, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [529] = {157, 119, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [530] = {157, 120, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [531] = {157, 126, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [532] = {157, 127, "DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [533] = {157, 128, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [534] = {157, 129, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [535] = {157, 130, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [536] = {157, 131, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [537] = {157, 132, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [538] = {157, 133, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [539] = {157, 137, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [540] = {157, 138, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [541] = {157, 139, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [542] = {157, 140, "DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [543] = {157, 141, "DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [544] = {157, 142, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [545] = {157, 143, "DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [546] = {157, 144, "DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [547] = {157, 145, "DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_BOARD0_OBSCLK0_IN"},
+        [548] = {157, 235, "DEV_BOARD0_MCASP3_ACLKR_IN", "Input clock"},
+        [549] = {157, 63, "DEV_BOARD0_PRG1_RGMII1_TXC_OUT", "Output clock"},
+        [550] = {157, 286, "DEV_BOARD0_MCASP11_ACLKR_OUT", "Output clock"},
+        [551] = {157, 271, "DEV_BOARD0_MCASP8_AFSX_OUT", "Output clock"},
+        [552] = {157, 281, "DEV_BOARD0_MCASP10_AFSR_OUT", "Output clock"},
+        [553] = {157, 27, "DEV_BOARD0_I2C1_SCL_OUT", "Output clock"},
+        [554] = {157, 257, "DEV_BOARD0_MCASP6_ACLKX_OUT", "Output clock"},
+        [555] = {157, 273, "DEV_BOARD0_MCASP9_ACLKR_OUT", "Output clock"},
+        [556] = {157, 280, "DEV_BOARD0_MCASP10_ACLKR_OUT", "Output clock"},
+        [557] = {157, 260, "DEV_BOARD0_MCASP7_ACLKR_OUT", "Output clock"},
+        [558] = {157, 31, "DEV_BOARD0_I2C3_SCL_OUT", "Output clock"},
+        [559] = {157, 64, "DEV_BOARD0_PRG1_RGMII1_RXC_OUT", "Output clock"},
+        [560] = {157, 186, "DEV_BOARD0_PCIE_REFCLK0N_OUT", "Output clock"},
+        [561] = {157, 33, "DEV_BOARD0_I2C4_SCL_OUT", "Output clock"},
+        [562] = {157, 56, "DEV_BOARD0_PRG0_RGMII1_TXC_OUT", "Output clock"},
+        [563] = {157, 284, "DEV_BOARD0_MCASP10_AFSX_OUT", "Output clock"},
+        [564] = {157, 289, "DEV_BOARD0_MCASP11_ACLKX_OUT", "Output clock"},
+        [565] = {157, 267, "DEV_BOARD0_MCASP8_ACLKR_OUT", "Output clock"},
+        [566] = {157, 237, "DEV_BOARD0_MCASP3_AFSR_OUT", "Output clock"},
+        [567] = {157, 47, "DEV_BOARD0_MCU_I3C0_SCL_OUT", "Output clock"},
+        [568] = {157, 264, "DEV_BOARD0_MCASP7_AFSX_OUT", "Output clock"},
+        [569] = {157, 268, "DEV_BOARD0_MCASP8_AFSR_OUT", "Output clock"},
+        [570] = {157, 254, "DEV_BOARD0_MCASP6_ACLKR_OUT", "Output clock"},
+        [571] = {157, 246, "DEV_BOARD0_MCASP4_AFSX_OUT", "Output clock"},
+        [572] = {157, 283, "DEV_BOARD0_MCASP10_ACLKX_OUT", "Output clock"},
+        [573] = {157, 278, "DEV_BOARD0_MCASP9_AFSX_OUT", "Output clock"},
+        [574] = {157, 59, "DEV_BOARD0_PRG0_RGMII2_TXC_OUT", "Output clock"},
+        [575] = {157, 87, "DEV_BOARD0_MCU_RMII1_REF_CLK_OUT", "Output clock"},
+        [576] = {157, 103, "DEV_BOARD0_GPMC0_CLK_OUT", "Output clock"},
+        [577] = {157, 201, "DEV_BOARD0_PCIE_REFCLK3P_OUT", "Output clock"},
+        [578] = {157, 41, "DEV_BOARD0_MCU_I2C1_SCL_OUT", "Output clock"},
+        [579] = {157, 182, "DEV_BOARD0_TCK_OUT", "Output clock"},
+        [580] = {157, 248, "DEV_BOARD0_MCASP5_ACLKR_OUT", "Output clock"},
+        [581] = {157, 74, "DEV_BOARD0_RGMII5_RXC_OUT", "Output clock"},
+        [582] = {157, 197, "DEV_BOARD0_PCIE_REFCLK2P_OUT", "Output clock"},
+        [583] = {157, 300, "DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT", "Output clock"},
+        [584] = {157, 37, "DEV_BOARD0_I2C6_SCL_OUT", "Output clock"},
+        [585] = {157, 219, "DEV_BOARD0_MCASP0_AFSR_OUT", "Output clock"},
+        [586] = {157, 252, "DEV_BOARD0_MCASP5_AFSX_OUT", "Output clock"},
+        [587] = {157, 405, "DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT", "Output clock"},
+        [588] = {157, 72, "DEV_BOARD0_RGMII4_RXC_OUT", "Output clock"},
+        [589] = {157, 20, "DEV_BOARD0_MCU_OSPI0_DQS_OUT", "Output clock"},
+        [590] = {157, 245, "DEV_BOARD0_MCASP4_ACLKX_OUT", "Output clock"},
+        [591] = {157, 249, "DEV_BOARD0_MCASP5_AFSR_OUT", "Output clock"},
+        [592] = {157, 105, "DEV_BOARD0_MLB0_MLBCLK_OUT", "Output clock"},
+        [593] = {157, 218, "DEV_BOARD0_MCASP0_ACLKR_OUT", "Output clock"},
+        [594] = {157, 240, "DEV_BOARD0_MCASP3_AFSX_OUT", "Output clock"},
+        [595] = {157, 39, "DEV_BOARD0_MCU_I2C0_SCL_OUT", "Output clock"},
+        [596] = {157, 192, "DEV_BOARD0_PCIE_REFCLK1N_OUT", "Output clock"},
+        [597] = {157, 227, "DEV_BOARD0_MCASP1_ACLKX_OUT", "Output clock"},
+        [598] = {157, 222, "DEV_BOARD0_MCASP0_AFSX_OUT", "Output clock"},
+        [599] = {157, 88, "DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT", "Output clock"},
+        [600] = {157, 287, "DEV_BOARD0_MCASP11_AFSR_OUT", "Output clock"},
+        [601] = {157, 243, "DEV_BOARD0_MCASP4_AFSR_OUT", "Output clock"},
+        [602] = {157, 370, "DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT", "Output clock"},
+        [603] = {157, 43, "DEV_BOARD0_WKUP_I2C0_SCL_OUT", "Output clock"},
+        [604] = {157, 106, "DEV_BOARD0_MLB0_MLBCP_OUT", "Output clock"},
+        [605] = {157, 179, "DEV_BOARD0_EXT_REFCLK1_OUT", "Output clock"},
+        [606] = {157, 198, "DEV_BOARD0_PCIE_REFCLK2N_OUT", "Output clock"},
+        [607] = {157, 202, "DEV_BOARD0_PCIE_REFCLK3N_OUT", "Output clock"},
+        [608] = {157, 181, "DEV_BOARD0_HFOSC1_CLK_OUT", "Output clock"},
+        [609] = {157, 236, "DEV_BOARD0_MCASP3_ACLKR_OUT", "Output clock"},
+        [610] = {157, 239, "DEV_BOARD0_MCASP3_ACLKX_OUT", "Output clock"},
+        [611] = {157, 221, "DEV_BOARD0_MCASP0_ACLKX_OUT", "Output clock"},
+        [612] = {157, 178, "DEV_BOARD0_LED_CLK_OUT", "Output clock"},
+        [613] = {157, 67, "DEV_BOARD0_PRG1_RGMII2_RXC_OUT", "Output clock"},
+        [614] = {157, 25, "DEV_BOARD0_I2C0_SCL_OUT", "Output clock"},
+        [615] = {157, 76, "DEV_BOARD0_RGMII6_RXC_OUT", "Output clock"},
+        [616] = {157, 270, "DEV_BOARD0_MCASP8_ACLKX_OUT", "Output clock"},
+        [617] = {157, 66, "DEV_BOARD0_PRG1_RGMII2_TXC_OUT", "Output clock"},
+        [618] = {157, 276, "DEV_BOARD0_MCASP9_ACLKX_OUT", "Output clock"},
+        [619] = {157, 80, "DEV_BOARD0_RGMII8_RXC_OUT", "Output clock"},
+        [620] = {157, 290, "DEV_BOARD0_MCASP11_AFSX_OUT", "Output clock"},
+        [621] = {157, 274, "DEV_BOARD0_MCASP9_AFSR_OUT", "Output clock"},
+        [622] = {157, 185, "DEV_BOARD0_PCIE_REFCLK0P_OUT", "Output clock"},
+        [623] = {157, 225, "DEV_BOARD0_MCASP1_AFSR_OUT", "Output clock"},
+        [624] = {157, 191, "DEV_BOARD0_PCIE_REFCLK1P_OUT", "Output clock"},
+        [625] = {157, 242, "DEV_BOARD0_MCASP4_ACLKR_OUT", "Output clock"},
+        [626] = {157, 82, "DEV_BOARD0_CPTS0_RFT_CLK_OUT", "Output clock"},
+        [627] = {157, 45, "DEV_BOARD0_I3C0_SCL_OUT", "Output clock"},
+        [628] = {157, 230, "DEV_BOARD0_MCASP2_ACLKR_OUT", "Output clock"},
+        [629] = {157, 81, "DEV_BOARD0_RMII_REF_CLK_OUT", "Output clock"},
+        [630] = {157, 57, "DEV_BOARD0_PRG0_RGMII1_RXC_OUT", "Output clock"},
+        [631] = {157, 263, "DEV_BOARD0_MCASP7_ACLKX_OUT", "Output clock"},
+        [632] = {157, 228, "DEV_BOARD0_MCASP1_AFSX_OUT", "Output clock"},
+        [633] = {157, 233, "DEV_BOARD0_MCASP2_ACLKX_OUT", "Output clock"},
+        [634] = {157, 78, "DEV_BOARD0_RGMII7_RXC_OUT", "Output clock"},
+        [635] = {157, 85, "DEV_BOARD0_MCU_RGMII1_TXC_OUT", "Output clock"},
+        [636] = {157, 255, "DEV_BOARD0_MCASP6_AFSR_OUT", "Output clock"},
+        [637] = {157, 258, "DEV_BOARD0_MCASP6_AFSX_OUT", "Output clock"},
+        [638] = {157, 231, "DEV_BOARD0_MCASP2_AFSR_OUT", "Output clock"},
+        [639] = {157, 251, "DEV_BOARD0_MCASP5_ACLKX_OUT", "Output clock"},
+        [640] = {157, 35, "DEV_BOARD0_I2C5_SCL_OUT", "Output clock"},
+        [641] = {157, 108, "DEV_BOARD0_VPFE0_PCLK_OUT", "Output clock"},
+        [642] = {157, 224, "DEV_BOARD0_MCASP1_ACLKR_OUT", "Output clock"},
+        [643] = {157, 86, "DEV_BOARD0_MCU_RGMII1_RXC_OUT", "Output clock"},
+        [644] = {157, 70, "DEV_BOARD0_RGMII3_RXC_OUT", "Output clock"},
+        [645] = {157, 261, "DEV_BOARD0_MCASP7_AFSR_OUT", "Output clock"},
+        [646] = {157, 23, "DEV_BOARD0_MCU_OSPI1_DQS_OUT", "Output clock"},
+        [647] = {157, 60, "DEV_BOARD0_PRG0_RGMII2_RXC_OUT", "Output clock"},
+        [648] = {157, 29, "DEV_BOARD0_I2C2_SCL_OUT", "Output clock"},
+        [649] = {157, 180, "DEV_BOARD0_MCU_EXT_REFCLK0_OUT", "Output clock"},
+        [650] = {157, 234, "DEV_BOARD0_MCASP2_AFSX_OUT", "Output clock"},
+        [651] = {157, 49, "DEV_BOARD0_MCU_I3C1_SCL_OUT", "Output clock"},
+        [652] = {157, 110, "DEV_BOARD0_VOUT1_EXTPCLKIN_OUT", "Output clock"},
+        [653] = {157, 335, "DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT", "Output clock"},
+        [654] = {157, 112, "DEV_BOARD0_VOUT2_EXTPCLKIN_OUT", "Output clock"},
+        [655] = {142, 0, "DEV_C66SS0_CORE0_GEM_TRC_CLK", "Input clock"},
+        [656] = {142, 1, "DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
+        [657] = {121, 0, "DEV_C66SS0_INTROUTER0_INTR_CLK", "Input clock"},
+        [658] = {143, 0, "DEV_C66SS1_CORE0_GEM_TRC_CLK", "Input clock"},
+        [659] = {143, 1, "DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK", "Output clock"},
+        [660] = {122, 0, "DEV_C66SS1_INTROUTER0_INTR_CLK", "Input clock"},
+        [661] = {15, 0, "DEV_C71SS0_C7X_CLK", "Input clock"},
+        [662] = {15, 1, "DEV_C71SS0_PLL_CTRL_CLK", "Input clock"},
+        [663] = {16, 0, "DEV_C71SS0_MMA_PLL_CTRL_CLK", "Input clock"},
+        [664] = {16, 1, "DEV_C71SS0_MMA_MMA_CLK", "Input clock"},
+        [665] = {123, 0, "DEV_CMPEVENT_INTRTR0_INTR_CLK", "Input clock"},
+        [666] = {5, 0, "DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK", "Input clock"},
+        [667] = {6, 0, "DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK", "Input clock"},
+        [668] = {6, 1, "DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK", "Input clock"},
+        [669] = {7, 0, "DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK", "Input clock"},
+        [670] = {7, 1, "DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK", "Input clock"},
+        [671] = {8, 0, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK", "Input clock"},
+        [672] = {8, 1, "DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK", "Input clock"},
+        [673] = {9, 0, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK", "Input clock"},
+        [674] = {9, 1, "DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK", "Input clock"},
+        [675] = {12, 0, "DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK", "Input clock"},
+        [676] = {13, 0, "DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK", "Input clock"},
+        [677] = {14, 0, "DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK", "Input clock"},
+        [678] = {17, 0, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK", "Input clock"},
+        [679] = {17, 1, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK", "Input clock"},
+        [680] = {17, 2, "DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK", "Input clock"},
+        [681] = {19, 0, "DEV_CPSW0_GMII3_MT_CLK", "Input clock"},
+        [682] = {19, 1, "DEV_CPSW0_SERDES6_TXFCLK", "Input clock"},
+        [683] = {19, 2, "DEV_CPSW0_SERDES8_TXMCLK", "Input clock"},
+        [684] = {19, 3, "DEV_CPSW0_GMII2_MR_CLK", "Input clock"},
+        [685] = {19, 4, "DEV_CPSW0_SERDES2_TXFCLK", "Input clock"},
+        [686] = {19, 5, "DEV_CPSW0_SERDES4_RXCLK", "Input clock"},
+        [687] = {19, 6, "DEV_CPSW0_SERDES7_TXMCLK", "Input clock"},
+        [688] = {19, 7, "DEV_CPSW0_SERDES7_RXCLK", "Input clock"},
+        [689] = {19, 8, "DEV_CPSW0_SERDES6_REFCLK", "Input clock"},
+        [690] = {19, 9, "DEV_CPSW0_SERDES5_TXFCLK", "Input clock"},
+        [691] = {19, 10, "DEV_CPSW0_SERDES5_RXCLK", "Input clock"},
+        [692] = {19, 11, "DEV_CPSW0_GMII4_MT_CLK", "Input clock"},
+        [693] = {19, 12, "DEV_CPSW0_SERDES3_TXFCLK", "Input clock"},
+        [694] = {19, 13, "DEV_CPSW0_SERDES2_REFCLK", "Input clock"},
+        [695] = {19, 14, "DEV_CPSW0_SERDES4_RXFCLK", "Input clock"},
+        [696] = {19, 15, "DEV_CPSW0_SERDES6_RXFCLK", "Input clock"},
+        [697] = {19, 16, "DEV_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
+        [698] = {19, 17, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [699] = {19, 18, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [700] = {19, 19, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [701] = {19, 20, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [702] = {19, 21, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [703] = {19, 22, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [704] = {19, 23, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [705] = {19, 24, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [706] = {19, 25, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [707] = {19, 26, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [708] = {19, 27, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [709] = {19, 28, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [710] = {19, 29, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [711] = {19, 30, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [712] = {19, 31, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [713] = {19, 32, "DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK"},
+        [714] = {19, 33, "DEV_CPSW0_SERDES5_RXFCLK", "Input clock"},
+        [715] = {19, 34, "DEV_CPSW0_SERDES5_TXMCLK", "Input clock"},
+        [716] = {19, 35, "DEV_CPSW0_GMII5_MT_CLK", "Input clock"},
+        [717] = {19, 36, "DEV_CPSW0_SERDES2_RXCLK", "Input clock"},
+        [718] = {19, 37, "DEV_CPSW0_SERDES8_RXFCLK", "Input clock"},
+        [719] = {19, 38, "DEV_CPSW0_SERDES1_RXFCLK", "Input clock"},
+        [720] = {19, 39, "DEV_CPSW0_SERDES8_RXCLK", "Input clock"},
+        [721] = {19, 40, "DEV_CPSW0_GMII_RFT_CLK", "Input clock"},
+        [722] = {19, 41, "DEV_CPSW0_SERDES3_REFCLK", "Input clock"},
+        [723] = {19, 42, "DEV_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
+        [724] = {19, 43, "DEV_CPSW0_SERDES7_REFCLK", "Input clock"},
+        [725] = {19, 44, "DEV_CPSW0_GMII6_MT_CLK", "Input clock"},
+        [726] = {19, 45, "DEV_CPSW0_SERDES6_TXMCLK", "Input clock"},
+        [727] = {19, 46, "DEV_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
+        [728] = {19, 47, "DEV_CPSW0_GMII4_MR_CLK", "Input clock"},
+        [729] = {19, 48, "DEV_CPSW0_SERDES2_TXMCLK", "Input clock"},
+        [730] = {19, 49, "DEV_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
+        [731] = {19, 50, "DEV_CPSW0_SERDES4_TXMCLK", "Input clock"},
+        [732] = {19, 51, "DEV_CPSW0_SERDES3_RXFCLK", "Input clock"},
+        [733] = {19, 52, "DEV_CPSW0_GMII8_MT_CLK", "Input clock"},
+        [734] = {19, 53, "DEV_CPSW0_SERDES7_TXFCLK", "Input clock"},
+        [735] = {19, 54, "DEV_CPSW0_GMII7_MT_CLK", "Input clock"},
+        [736] = {19, 55, "DEV_CPSW0_GMII7_MR_CLK", "Input clock"},
+        [737] = {19, 56, "DEV_CPSW0_SERDES6_RXCLK", "Input clock"},
+        [738] = {19, 57, "DEV_CPSW0_SERDES3_RXCLK", "Input clock"},
+        [739] = {19, 89, "DEV_CPSW0_CPPI_CLK_CLK", "Input clock"},
+        [740] = {19, 58, "DEV_CPSW0_SERDES4_REFCLK", "Input clock"},
+        [741] = {19, 59, "DEV_CPSW0_SERDES1_RXCLK", "Input clock"},
+        [742] = {19, 60, "DEV_CPSW0_SERDES1_TXFCLK", "Input clock"},
+        [743] = {19, 61, "DEV_CPSW0_GMII6_MR_CLK", "Input clock"},
+        [744] = {19, 62, "DEV_CPSW0_SERDES1_REFCLK", "Input clock"},
+        [745] = {19, 63, "DEV_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
+        [746] = {19, 64, "DEV_CPSW0_SERDES5_REFCLK", "Input clock"},
+        [747] = {19, 65, "DEV_CPSW0_GMII2_MT_CLK", "Input clock"},
+        [748] = {19, 66, "DEV_CPSW0_SERDES8_TXFCLK", "Input clock"},
+        [749] = {19, 67, "DEV_CPSW0_GMII8_MR_CLK", "Input clock"},
+        [750] = {19, 68, "DEV_CPSW0_GMII1_MR_CLK", "Input clock"},
+        [751] = {19, 69, "DEV_CPSW0_SERDES8_REFCLK", "Input clock"},
+        [752] = {19, 70, "DEV_CPSW0_SERDES3_TXMCLK", "Input clock"},
+        [753] = {19, 71, "DEV_CPSW0_GMII3_MR_CLK", "Input clock"},
+        [754] = {19, 72, "DEV_CPSW0_SERDES1_TXMCLK", "Input clock"},
+        [755] = {19, 73, "DEV_CPSW0_SERDES7_RXFCLK", "Input clock"},
+        [756] = {19, 74, "DEV_CPSW0_GMII5_MR_CLK", "Input clock"},
+        [757] = {19, 75, "DEV_CPSW0_GMII1_MT_CLK", "Input clock"},
+        [758] = {19, 76, "DEV_CPSW0_SERDES2_RXFCLK", "Input clock"},
+        [759] = {19, 77, "DEV_CPSW0_SERDES4_TXFCLK", "Input clock"},
+        [760] = {19, 78, "DEV_CPSW0_SERDES3_TXCLK", "Output clock"},
+        [761] = {19, 79, "DEV_CPSW0_CPTS_GENF0_0", "Output clock"},
+        [762] = {19, 80, "DEV_CPSW0_SERDES5_TXCLK", "Output clock"},
+        [763] = {19, 81, "DEV_CPSW0_SERDES6_TXCLK", "Output clock"},
+        [764] = {19, 82, "DEV_CPSW0_SERDES8_TXCLK", "Output clock"},
+        [765] = {19, 83, "DEV_CPSW0_SERDES1_TXCLK", "Output clock"},
+        [766] = {19, 84, "DEV_CPSW0_SERDES4_TXCLK", "Output clock"},
+        [767] = {19, 85, "DEV_CPSW0_SERDES2_TXCLK", "Output clock"},
+        [768] = {19, 86, "DEV_CPSW0_SERDES7_TXCLK", "Output clock"},
+        [769] = {19, 87, "DEV_CPSW0_MDIO_MDCLK_O_0", "Output clock"},
+        [770] = {20, 0, "DEV_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+        [771] = {21, 0, "DEV_CPT2_AGGR1_VCLK_CLK", "Input clock"},
+        [772] = {23, 0, "DEV_CPT2_AGGR2_VCLK_CLK", "Input clock"},
+        [773] = {25, 0, "DEV_CSI_PSILSS0_MAIN_CLK", "Input clock"},
+        [774] = {26, 0, "DEV_CSI_RX_IF0_VBUS_CLK_CLK", "Input clock"},
+        [775] = {26, 1, "DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK", "Input clock"},
+        [776] = {26, 2, "DEV_CSI_RX_IF0_MAIN_CLK_CLK", "Input clock"},
+        [777] = {26, 3, "DEV_CSI_RX_IF0_VP_CLK_CLK", "Input clock"},
+        [778] = {27, 0, "DEV_CSI_RX_IF1_VBUS_CLK_CLK", "Input clock"},
+        [779] = {27, 1, "DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK", "Input clock"},
+        [780] = {27, 2, "DEV_CSI_RX_IF1_MAIN_CLK_CLK", "Input clock"},
+        [781] = {27, 3, "DEV_CSI_RX_IF1_VP_CLK_CLK", "Input clock"},
+        [782] = {28, 0, "DEV_CSI_TX_IF0_ESC_CLK_CLK", "Input clock"},
+        [783] = {28, 1, "DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK", "Input clock"},
+        [784] = {28, 2, "DEV_CSI_TX_IF0_VBUS_CLK_CLK", "Input clock"},
+        [785] = {28, 3, "DEV_CSI_TX_IF0_MAIN_CLK_CLK", "Input clock"},
+        [786] = {30, 0, "DEV_DCC0_DCC_INPUT10_CLK", "Input clock"},
+        [787] = {30, 1, "DEV_DCC0_DCC_INPUT01_CLK", "Input clock"},
+        [788] = {30, 2, "DEV_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+        [789] = {30, 3, "DEV_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+        [790] = {30, 4, "DEV_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+        [791] = {30, 5, "DEV_DCC0_VBUS_CLK", "Input clock"},
+        [792] = {30, 6, "DEV_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+        [793] = {30, 7, "DEV_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+        [794] = {30, 8, "DEV_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+        [795] = {30, 9, "DEV_DCC0_DCC_INPUT00_CLK", "Input clock"},
+        [796] = {30, 10, "DEV_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+        [797] = {30, 11, "DEV_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+        [798] = {30, 12, "DEV_DCC0_DCC_INPUT02_CLK", "Input clock"},
+        [799] = {31, 0, "DEV_DCC1_DCC_INPUT10_CLK", "Input clock"},
+        [800] = {31, 1, "DEV_DCC1_DCC_INPUT01_CLK", "Input clock"},
+        [801] = {31, 2, "DEV_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+        [802] = {31, 3, "DEV_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
+        [803] = {31, 4, "DEV_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+        [804] = {31, 5, "DEV_DCC1_VBUS_CLK", "Input clock"},
+        [805] = {31, 6, "DEV_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+        [806] = {31, 7, "DEV_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+        [807] = {31, 8, "DEV_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+        [808] = {31, 9, "DEV_DCC1_DCC_INPUT00_CLK", "Input clock"},
+        [809] = {31, 10, "DEV_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+        [810] = {31, 11, "DEV_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+        [811] = {31, 12, "DEV_DCC1_DCC_INPUT02_CLK", "Input clock"},
+        [812] = {41, 0, "DEV_DCC10_DCC_INPUT10_CLK", "Input clock"},
+        [813] = {41, 1, "DEV_DCC10_DCC_INPUT01_CLK", "Input clock"},
+        [814] = {41, 2, "DEV_DCC10_DCC_CLKSRC2_CLK", "Input clock"},
+        [815] = {41, 3, "DEV_DCC10_DCC_CLKSRC7_CLK", "Input clock"},
+        [816] = {41, 4, "DEV_DCC10_DCC_CLKSRC0_CLK", "Input clock"},
+        [817] = {41, 5, "DEV_DCC10_VBUS_CLK", "Input clock"},
+        [818] = {41, 6, "DEV_DCC10_DCC_CLKSRC4_CLK", "Input clock"},
+        [819] = {41, 7, "DEV_DCC10_DCC_CLKSRC1_CLK", "Input clock"},
+        [820] = {41, 8, "DEV_DCC10_DCC_CLKSRC3_CLK", "Input clock"},
+        [821] = {41, 9, "DEV_DCC10_DCC_INPUT00_CLK", "Input clock"},
+        [822] = {41, 10, "DEV_DCC10_DCC_CLKSRC5_CLK", "Input clock"},
+        [823] = {41, 11, "DEV_DCC10_DCC_CLKSRC6_CLK", "Input clock"},
+        [824] = {41, 12, "DEV_DCC10_DCC_INPUT02_CLK", "Input clock"},
+        [825] = {42, 0, "DEV_DCC11_DCC_INPUT10_CLK", "Input clock"},
+        [826] = {42, 1, "DEV_DCC11_DCC_INPUT01_CLK", "Input clock"},
+        [827] = {42, 2, "DEV_DCC11_DCC_CLKSRC2_CLK", "Input clock"},
+        [828] = {42, 3, "DEV_DCC11_DCC_CLKSRC7_CLK", "Input clock"},
+        [829] = {42, 4, "DEV_DCC11_DCC_CLKSRC0_CLK", "Input clock"},
+        [830] = {42, 5, "DEV_DCC11_VBUS_CLK", "Input clock"},
+        [831] = {42, 6, "DEV_DCC11_DCC_CLKSRC4_CLK", "Input clock"},
+        [832] = {42, 7, "DEV_DCC11_DCC_CLKSRC1_CLK", "Input clock"},
+        [833] = {42, 8, "DEV_DCC11_DCC_CLKSRC3_CLK", "Input clock"},
+        [834] = {42, 9, "DEV_DCC11_DCC_INPUT00_CLK", "Input clock"},
+        [835] = {42, 10, "DEV_DCC11_DCC_CLKSRC5_CLK", "Input clock"},
+        [836] = {42, 11, "DEV_DCC11_DCC_CLKSRC6_CLK", "Input clock"},
+        [837] = {42, 12, "DEV_DCC11_DCC_INPUT02_CLK", "Input clock"},
+        [838] = {43, 0, "DEV_DCC12_DCC_INPUT10_CLK", "Input clock"},
+        [839] = {43, 1, "DEV_DCC12_DCC_INPUT01_CLK", "Input clock"},
+        [840] = {43, 2, "DEV_DCC12_DCC_CLKSRC2_CLK", "Input clock"},
+        [841] = {43, 3, "DEV_DCC12_DCC_CLKSRC7_CLK", "Input clock"},
+        [842] = {43, 4, "DEV_DCC12_DCC_CLKSRC0_CLK", "Input clock"},
+        [843] = {43, 5, "DEV_DCC12_VBUS_CLK", "Input clock"},
+        [844] = {43, 6, "DEV_DCC12_DCC_CLKSRC4_CLK", "Input clock"},
+        [845] = {43, 7, "DEV_DCC12_DCC_CLKSRC1_CLK", "Input clock"},
+        [846] = {43, 8, "DEV_DCC12_DCC_CLKSRC3_CLK", "Input clock"},
+        [847] = {43, 9, "DEV_DCC12_DCC_INPUT00_CLK", "Input clock"},
+        [848] = {43, 10, "DEV_DCC12_DCC_CLKSRC5_CLK", "Input clock"},
+        [849] = {43, 11, "DEV_DCC12_DCC_CLKSRC6_CLK", "Input clock"},
+        [850] = {43, 12, "DEV_DCC12_DCC_INPUT02_CLK", "Input clock"},
+        [851] = {32, 0, "DEV_DCC2_DCC_INPUT10_CLK", "Input clock"},
+        [852] = {32, 1, "DEV_DCC2_DCC_INPUT01_CLK", "Input clock"},
+        [853] = {32, 2, "DEV_DCC2_DCC_CLKSRC2_CLK", "Input clock"},
+        [854] = {32, 3, "DEV_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+        [855] = {32, 4, "DEV_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+        [856] = {32, 5, "DEV_DCC2_VBUS_CLK", "Input clock"},
+        [857] = {32, 6, "DEV_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
+        [858] = {32, 7, "DEV_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
+        [859] = {32, 8, "DEV_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+        [860] = {32, 9, "DEV_DCC2_DCC_INPUT00_CLK", "Input clock"},
+        [861] = {32, 10, "DEV_DCC2_DCC_CLKSRC5_CLK", "Input clock"},
+        [862] = {32, 11, "DEV_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+        [863] = {32, 12, "DEV_DCC2_DCC_INPUT02_CLK", "Input clock"},
+        [864] = {33, 0, "DEV_DCC3_DCC_INPUT10_CLK", "Input clock"},
+        [865] = {33, 1, "DEV_DCC3_DCC_INPUT01_CLK", "Input clock"},
+        [866] = {33, 2, "DEV_DCC3_DCC_CLKSRC2_CLK", "Input clock"},
+        [867] = {33, 3, "DEV_DCC3_DCC_CLKSRC7_CLK", "Input clock"},
+        [868] = {33, 4, "DEV_DCC3_DCC_CLKSRC0_CLK", "Input clock"},
+        [869] = {33, 5, "DEV_DCC3_VBUS_CLK", "Input clock"},
+        [870] = {33, 6, "DEV_DCC3_DCC_CLKSRC4_CLK", "Input clock"},
+        [871] = {33, 7, "DEV_DCC3_DCC_CLKSRC1_CLK", "Input clock"},
+        [872] = {33, 8, "DEV_DCC3_DCC_CLKSRC3_CLK", "Input clock"},
+        [873] = {33, 9, "DEV_DCC3_DCC_INPUT00_CLK", "Input clock"},
+        [874] = {33, 10, "DEV_DCC3_DCC_CLKSRC5_CLK", "Input clock"},
+        [875] = {33, 11, "DEV_DCC3_DCC_CLKSRC6_CLK", "Input clock"},
+        [876] = {33, 12, "DEV_DCC3_DCC_INPUT02_CLK", "Input clock"},
+        [877] = {34, 0, "DEV_DCC4_DCC_INPUT10_CLK", "Input clock"},
+        [878] = {34, 1, "DEV_DCC4_DCC_INPUT01_CLK", "Input clock"},
+        [879] = {34, 2, "DEV_DCC4_DCC_CLKSRC2_CLK", "Input clock"},
+        [880] = {34, 3, "DEV_DCC4_DCC_CLKSRC7_CLK", "Input clock"},
+        [881] = {34, 4, "DEV_DCC4_DCC_CLKSRC0_CLK", "Input clock"},
+        [882] = {34, 5, "DEV_DCC4_VBUS_CLK", "Input clock"},
+        [883] = {34, 6, "DEV_DCC4_DCC_CLKSRC4_CLK", "Input clock"},
+        [884] = {34, 7, "DEV_DCC4_DCC_CLKSRC1_CLK", "Input clock"},
+        [885] = {34, 8, "DEV_DCC4_DCC_CLKSRC3_CLK", "Input clock"},
+        [886] = {34, 9, "DEV_DCC4_DCC_INPUT00_CLK", "Input clock"},
+        [887] = {34, 10, "DEV_DCC4_DCC_CLKSRC5_CLK", "Input clock"},
+        [888] = {34, 11, "DEV_DCC4_DCC_CLKSRC6_CLK", "Input clock"},
+        [889] = {34, 12, "DEV_DCC4_DCC_INPUT02_CLK", "Input clock"},
+        [890] = {36, 0, "DEV_DCC5_DCC_INPUT10_CLK", "Input clock"},
+        [891] = {36, 1, "DEV_DCC5_DCC_INPUT01_CLK", "Input clock"},
+        [892] = {36, 2, "DEV_DCC5_DCC_CLKSRC2_CLK", "Input clock"},
+        [893] = {36, 3, "DEV_DCC5_DCC_CLKSRC7_CLK", "Input clock"},
+        [894] = {36, 4, "DEV_DCC5_DCC_CLKSRC0_CLK", "Input clock"},
+        [895] = {36, 5, "DEV_DCC5_VBUS_CLK", "Input clock"},
+        [896] = {36, 6, "DEV_DCC5_DCC_CLKSRC4_CLK", "Input clock"},
+        [897] = {36, 7, "DEV_DCC5_DCC_CLKSRC1_CLK", "Input clock"},
+        [898] = {36, 8, "DEV_DCC5_DCC_CLKSRC3_CLK", "Input clock"},
+        [899] = {36, 9, "DEV_DCC5_DCC_INPUT00_CLK", "Input clock"},
+        [900] = {36, 10, "DEV_DCC5_DCC_CLKSRC5_CLK", "Input clock"},
+        [901] = {36, 11, "DEV_DCC5_DCC_CLKSRC6_CLK", "Input clock"},
+        [902] = {36, 12, "DEV_DCC5_DCC_INPUT02_CLK", "Input clock"},
+        [903] = {37, 0, "DEV_DCC6_DCC_INPUT10_CLK", "Input clock"},
+        [904] = {37, 1, "DEV_DCC6_DCC_INPUT01_CLK", "Input clock"},
+        [905] = {37, 2, "DEV_DCC6_DCC_CLKSRC2_CLK", "Input clock"},
+        [906] = {37, 3, "DEV_DCC6_DCC_CLKSRC7_CLK", "Input clock"},
+        [907] = {37, 4, "DEV_DCC6_DCC_CLKSRC0_CLK", "Input clock"},
+        [908] = {37, 5, "DEV_DCC6_VBUS_CLK", "Input clock"},
+        [909] = {37, 6, "DEV_DCC6_DCC_CLKSRC4_CLK", "Input clock"},
+        [910] = {37, 7, "DEV_DCC6_DCC_CLKSRC1_CLK", "Input clock"},
+        [911] = {37, 8, "DEV_DCC6_DCC_CLKSRC3_CLK", "Input clock"},
+        [912] = {37, 9, "DEV_DCC6_DCC_INPUT00_CLK", "Input clock"},
+        [913] = {37, 10, "DEV_DCC6_DCC_CLKSRC5_CLK", "Input clock"},
+        [914] = {37, 11, "DEV_DCC6_DCC_CLKSRC6_CLK", "Input clock"},
+        [915] = {37, 12, "DEV_DCC6_DCC_INPUT02_CLK", "Input clock"},
+        [916] = {38, 0, "DEV_DCC7_DCC_INPUT10_CLK", "Input clock"},
+        [917] = {38, 1, "DEV_DCC7_DCC_INPUT01_CLK", "Input clock"},
+        [918] = {38, 2, "DEV_DCC7_DCC_CLKSRC2_CLK", "Input clock"},
+        [919] = {38, 3, "DEV_DCC7_DCC_CLKSRC7_CLK", "Input clock"},
+        [920] = {38, 4, "DEV_DCC7_DCC_CLKSRC0_CLK", "Input clock"},
+        [921] = {38, 5, "DEV_DCC7_VBUS_CLK", "Input clock"},
+        [922] = {38, 6, "DEV_DCC7_DCC_CLKSRC4_CLK", "Input clock"},
+        [923] = {38, 7, "DEV_DCC7_DCC_CLKSRC1_CLK", "Input clock"},
+        [924] = {38, 8, "DEV_DCC7_DCC_CLKSRC3_CLK", "Input clock"},
+        [925] = {38, 9, "DEV_DCC7_DCC_INPUT00_CLK", "Input clock"},
+        [926] = {38, 10, "DEV_DCC7_DCC_CLKSRC5_CLK", "Input clock"},
+        [927] = {38, 11, "DEV_DCC7_DCC_CLKSRC6_CLK", "Input clock"},
+        [928] = {38, 12, "DEV_DCC7_DCC_INPUT02_CLK", "Input clock"},
+        [929] = {39, 0, "DEV_DCC8_DCC_INPUT10_CLK", "Input clock"},
+        [930] = {39, 1, "DEV_DCC8_DCC_INPUT01_CLK", "Input clock"},
+        [931] = {39, 2, "DEV_DCC8_DCC_CLKSRC2_CLK", "Input clock"},
+        [932] = {39, 3, "DEV_DCC8_DCC_CLKSRC7_CLK", "Input clock"},
+        [933] = {39, 4, "DEV_DCC8_DCC_CLKSRC0_CLK", "Input clock"},
+        [934] = {39, 5, "DEV_DCC8_VBUS_CLK", "Input clock"},
+        [935] = {39, 6, "DEV_DCC8_DCC_CLKSRC4_CLK", "Input clock"},
+        [936] = {39, 7, "DEV_DCC8_DCC_CLKSRC1_CLK", "Input clock"},
+        [937] = {39, 8, "DEV_DCC8_DCC_CLKSRC3_CLK", "Input clock"},
+        [938] = {39, 9, "DEV_DCC8_DCC_INPUT00_CLK", "Input clock"},
+        [939] = {39, 10, "DEV_DCC8_DCC_CLKSRC5_CLK", "Input clock"},
+        [940] = {39, 11, "DEV_DCC8_DCC_CLKSRC6_CLK", "Input clock"},
+        [941] = {39, 12, "DEV_DCC8_DCC_INPUT02_CLK", "Input clock"},
+        [942] = {40, 0, "DEV_DCC9_DCC_INPUT10_CLK", "Input clock"},
+        [943] = {40, 1, "DEV_DCC9_DCC_INPUT01_CLK", "Input clock"},
+        [944] = {40, 2, "DEV_DCC9_DCC_CLKSRC2_CLK", "Input clock"},
+        [945] = {40, 3, "DEV_DCC9_DCC_CLKSRC7_CLK", "Input clock"},
+        [946] = {40, 4, "DEV_DCC9_DCC_CLKSRC0_CLK", "Input clock"},
+        [947] = {40, 5, "DEV_DCC9_VBUS_CLK", "Input clock"},
+        [948] = {40, 6, "DEV_DCC9_DCC_CLKSRC4_CLK", "Input clock"},
+        [949] = {40, 7, "DEV_DCC9_DCC_CLKSRC1_CLK", "Input clock"},
+        [950] = {40, 8, "DEV_DCC9_DCC_CLKSRC3_CLK", "Input clock"},
+        [951] = {40, 9, "DEV_DCC9_DCC_INPUT00_CLK", "Input clock"},
+        [952] = {40, 10, "DEV_DCC9_DCC_CLKSRC5_CLK", "Input clock"},
+        [953] = {40, 11, "DEV_DCC9_DCC_CLKSRC6_CLK", "Input clock"},
+        [954] = {40, 12, "DEV_DCC9_DCC_INPUT02_CLK", "Input clock"},
+        [955] = {47, 0, "DEV_DDR0_DDRSS_VBUS_CLK", "Input clock"},
+        [956] = {47, 1, "DEV_DDR0_PLL_CTRL_CLK", "Input clock"},
+        [957] = {47, 2, "DEV_DDR0_DDRSS_DDR_PLL_CLK", "Input clock"},
+        [958] = {47, 3, "DEV_DDR0_DDRSS_CFG_CLK", "Input clock"},
+        [959] = {47, 4, "DEV_DDR0_DDRSS_IO_CK_N_0", "Output clock"},
+        [960] = {47, 5, "DEV_DDR0_DDRSS_IO_CK_0", "Output clock"},
+        [961] = {304, 25, "DEV_DEBUGSS_WRAP0_JTAG_TCK", "Input clock"},
+        [962] = {304, 5, "DEV_DEBUGSS_WRAP0_TREXPT_CLK", "Input clock"},
+        [963] = {304, 9, "DEV_DEBUGSS_WRAP0_CORE_CLK", "Input clock"},
+        [964] = {304, 35, "DEV_DEBUGSS_WRAP0_ATB_CLK", "Input clock"},
+        [965] = {304, 32, "DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK_0", "Output clock"},
+        [966] = {144, 0, "DEV_DECODER0_SYS_CLK", "Input clock"},
+        [967] = {305, 0, "DEV_DMPAC0_SDE_0_CLK", "Input clock"},
+        [968] = {147, 0, "DEV_DPHY_RX0_MAIN_CLK_CLK", "Input clock"},
+        [969] = {147, 1, "DEV_DPHY_RX0_PPI_RX_BYTE_CLK", "Output clock"},
+        [970] = {148, 0, "DEV_DPHY_RX1_MAIN_CLK_CLK", "Input clock"},
+        [971] = {148, 1, "DEV_DPHY_RX1_PPI_RX_BYTE_CLK", "Output clock"},
+        [972] = {296, 0, "DEV_DPHY_TX0_CLK", "Input clock"},
+        [973] = {296, 1, "DEV_DPHY_TX0_PSM_CLK", "Input clock"},
+        [974] = {296, 2, "DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK", "Input clock"},
+        [975] = {296, 3, "DEV_DPHY_TX0_DPHY_REF_CLK", "Input muxed clock"},
+        [976] = {296, 4, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+        [977] = {296, 5, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+        [978] = {296, 6, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+        [979] = {296, 7, "DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK"},
+        [980] = {296, 8, "DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+        [981] = {296, 9, "DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK", "Output clock"},
+        [982] = {296, 10, "DEV_DPHY_TX0_CK_P_0", "Output clock"},
+        [983] = {296, 11, "DEV_DPHY_TX0_CK_M_0", "Output clock"},
+        [984] = {296, 12, "DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK", "Output clock"},
+        [985] = {152, 1, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK", "Input muxed clock"},
+        [986] = {152, 2, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
+        [987] = {152, 3, "DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK"},
+        [988] = {152, 13, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK", "Input muxed clock"},
+        [989] = {152, 14, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+        [990] = {152, 15, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+        [991] = {152, 16, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+        [992] = {152, 17, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+        [993] = {152, 18, "DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK"},
+        [994] = {152, 9, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK", "Input muxed clock"},
+        [995] = {152, 10, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+        [996] = {152, 11, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+        [997] = {152, 12, "DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK"},
+        [998] = {152, 34, "DEV_DSS0_DPI1_EXT_CLKSEL", "Input muxed clock"},
+        [999] = {152, 35, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
+        [1000] = {152, 36, "DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL"},
+        [1001] = {152, 0, "DEV_DSS0_DSS_FUNC_CLK", "Input clock"},
+        [1002] = {152, 4, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK", "Input muxed clock"},
+        [1003] = {152, 5, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+        [1004] = {152, 6, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+        [1005] = {152, 7, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+        [1006] = {152, 8, "DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK"},
+        [1007] = {152, 31, "DEV_DSS0_DPI0_EXT_CLKSEL", "Input muxed clock"},
+        [1008] = {152, 32, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
+        [1009] = {152, 33, "DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT", "Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL"},
+        [1010] = {152, 23, "DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK", "Output clock"},
+        [1011] = {152, 24, "DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK", "Output clock"},
+        [1012] = {152, 29, "DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK", "Output clock"},
+        [1013] = {152, 27, "DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK", "Output clock"},
+        [1014] = {152, 25, "DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK", "Output clock"},
+        [1015] = {150, 0, "DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK", "Input clock"},
+        [1016] = {150, 1, "DEV_DSS_DSI0_DPI_0_CLK", "Input clock"},
+        [1017] = {150, 2, "DEV_DSS_DSI0_PLL_CTRL_CLK", "Input clock"},
+        [1018] = {150, 5, "DEV_DSS_DSI0_SYS_CLK", "Input clock"},
+        [1019] = {150, 3, "DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK", "Input clock"},
+        [1020] = {150, 4, "DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK", "Input clock"},
+        [1021] = {151, 0, "DEV_DSS_EDP0_PHY_LN1_TXFCLK", "Input clock"},
+        [1022] = {151, 1, "DEV_DSS_EDP0_DPI_2_CLK", "Input clock"},
+        [1023] = {151, 2, "DEV_DSS_EDP0_PHY_LN2_TXFCLK", "Input clock"},
+        [1024] = {151, 3, "DEV_DSS_EDP0_PHY_LN0_RXCLK", "Input clock"},
+        [1025] = {151, 4, "DEV_DSS_EDP0_PHY_LN2_TXMCLK", "Input clock"},
+        [1026] = {151, 5, "DEV_DSS_EDP0_PHY_LN0_RXFCLK", "Input clock"},
+        [1027] = {151, 6, "DEV_DSS_EDP0_PHY_LN0_REFCLK", "Input clock"},
+        [1028] = {151, 7, "DEV_DSS_EDP0_PHY_LN1_RXCLK", "Input clock"},
+        [1029] = {151, 8, "DEV_DSS_EDP0_PHY_LN2_RXFCLK", "Input clock"},
+        [1030] = {151, 9, "DEV_DSS_EDP0_DPI_4_CLK", "Input clock"},
+        [1031] = {151, 10, "DEV_DSS_EDP0_DPI_2_2X_CLK", "Input clock"},
+        [1032] = {151, 11, "DEV_DSS_EDP0_PHY_LN0_TXFCLK", "Input clock"},
+        [1033] = {151, 12, "DEV_DSS_EDP0_PHY_LN2_RXCLK", "Input clock"},
+        [1034] = {151, 13, "DEV_DSS_EDP0_PHY_LN2_REFCLK", "Input clock"},
+        [1035] = {151, 14, "DEV_DSS_EDP0_PHY_LN3_REFCLK", "Input clock"},
+        [1036] = {151, 15, "DEV_DSS_EDP0_DPI_5_CLK", "Input clock"},
+        [1037] = {151, 16, "DEV_DSS_EDP0_PHY_LN3_RXCLK", "Input clock"},
+        [1038] = {151, 17, "DEV_DSS_EDP0_PHY_LN1_REFCLK", "Input clock"},
+        [1039] = {151, 18, "DEV_DSS_EDP0_AIF_I2S_CLK", "Input clock"},
+        [1040] = {151, 19, "DEV_DSS_EDP0_PHY_LN3_TXFCLK", "Input clock"},
+        [1041] = {151, 20, "DEV_DSS_EDP0_DPI_3_CLK", "Input clock"},
+        [1042] = {151, 36, "DEV_DSS_EDP0_DPTX_MOD_CLK", "Input clock"},
+        [1043] = {151, 21, "DEV_DSS_EDP0_PHY_LN1_RXFCLK", "Input clock"},
+        [1044] = {151, 22, "DEV_DSS_EDP0_PHY_LN1_TXMCLK", "Input clock"},
+        [1045] = {151, 23, "DEV_DSS_EDP0_PLL_CTRL_CLK", "Input clock"},
+        [1046] = {151, 24, "DEV_DSS_EDP0_PHY_LN3_TXMCLK", "Input clock"},
+        [1047] = {151, 25, "DEV_DSS_EDP0_PHY_LN3_RXFCLK", "Input clock"},
+        [1048] = {151, 26, "DEV_DSS_EDP0_PHY_LN0_TXMCLK", "Input clock"},
+        [1049] = {151, 27, "DEV_DSS_EDP0_PHY_LN2_TXCLK", "Output clock"},
+        [1050] = {151, 28, "DEV_DSS_EDP0_PHY_LN3_TXCLK", "Output clock"},
+        [1051] = {151, 29, "DEV_DSS_EDP0_PHY_LN0_TXCLK", "Output clock"},
+        [1052] = {151, 30, "DEV_DSS_EDP0_PHY_LN1_TXCLK", "Output clock"},
+        [1053] = {80, 0, "DEV_ECAP0_VBUS_CLK", "Input clock"},
+        [1054] = {81, 0, "DEV_ECAP1_VBUS_CLK", "Input clock"},
+        [1055] = {82, 0, "DEV_ECAP2_VBUS_CLK", "Input clock"},
+        [1056] = {83, 0, "DEV_EHRPWM0_VBUSP_CLK", "Input clock"},
+        [1057] = {84, 0, "DEV_EHRPWM1_VBUSP_CLK", "Input clock"},
+        [1058] = {85, 0, "DEV_EHRPWM2_VBUSP_CLK", "Input clock"},
+        [1059] = {86, 0, "DEV_EHRPWM3_VBUSP_CLK", "Input clock"},
+        [1060] = {87, 0, "DEV_EHRPWM4_VBUSP_CLK", "Input clock"},
+        [1061] = {88, 0, "DEV_EHRPWM5_VBUSP_CLK", "Input clock"},
+        [1062] = {89, 0, "DEV_ELM0_VBUSP_CLK", "Input clock"},
+        [1063] = {153, 0, "DEV_ENCODER0_SYS_CLK", "Input clock"},
+        [1064] = {94, 0, "DEV_EQEP0_VBUS_CLK", "Input clock"},
+        [1065] = {95, 0, "DEV_EQEP1_VBUS_CLK", "Input clock"},
+        [1066] = {96, 0, "DEV_EQEP2_VBUS_CLK", "Input clock"},
+        [1067] = {97, 0, "DEV_ESM0_CLK", "Input clock"},
+        [1068] = {105, 0, "DEV_GPIO0_MMR_CLK", "Input clock"},
+        [1069] = {106, 0, "DEV_GPIO1_MMR_CLK", "Input clock"},
+        [1070] = {107, 0, "DEV_GPIO2_MMR_CLK", "Input clock"},
+        [1071] = {108, 0, "DEV_GPIO3_MMR_CLK", "Input clock"},
+        [1072] = {109, 0, "DEV_GPIO4_MMR_CLK", "Input clock"},
+        [1073] = {110, 0, "DEV_GPIO5_MMR_CLK", "Input clock"},
+        [1074] = {111, 0, "DEV_GPIO6_MMR_CLK", "Input clock"},
+        [1075] = {112, 0, "DEV_GPIO7_MMR_CLK", "Input clock"},
+        [1076] = {131, 0, "DEV_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
+        [1077] = {115, 0, "DEV_GPMC0_PI_GPMC_RET_CLK", "Input clock"},
+        [1078] = {115, 1, "DEV_GPMC0_VBUSP_CLK", "Input clock"},
+        [1079] = {115, 2, "DEV_GPMC0_FUNC_CLK", "Input muxed clock"},
+        [1080] = {115, 3, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+        [1081] = {115, 4, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+        [1082] = {115, 5, "DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK3", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+        [1083] = {115, 6, "DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4", "Parent input clock option to DEV_GPMC0_FUNC_CLK"},
+        [1084] = {115, 7, "DEV_GPMC0_PO_GPMC_DEV_CLK", "Output clock"},
+        [1085] = {125, 0, "DEV_GPU0_GPU_0_GPU_PLL_CLK", "Input clock"},
+        [1086] = {61, 0, "DEV_GTC0_VBUSP_CLK", "Input clock"},
+        [1087] = {61, 1, "DEV_GTC0_GTC_CLK", "Input muxed clock"},
+        [1088] = {61, 2, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1089] = {61, 3, "DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1090] = {61, 4, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1091] = {61, 5, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1092] = {61, 6, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1093] = {61, 7, "DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1094] = {61, 8, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1095] = {61, 9, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1096] = {61, 10, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1097] = {61, 11, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1098] = {61, 12, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1099] = {61, 13, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1100] = {61, 14, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1101] = {61, 15, "DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1102] = {61, 16, "DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1103] = {61, 17, "DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_GTC0_GTC_CLK"},
+        [1104] = {187, 0, "DEV_I2C0_PISYS_CLK", "Input clock"},
+        [1105] = {187, 1, "DEV_I2C0_PISCL_0", "Input clock"},
+        [1106] = {187, 2, "DEV_I2C0_CLK", "Input clock"},
+        [1107] = {188, 0, "DEV_I2C1_PISYS_CLK", "Input clock"},
+        [1108] = {188, 1, "DEV_I2C1_PISCL_0", "Input clock"},
+        [1109] = {188, 2, "DEV_I2C1_CLK", "Input clock"},
+        [1110] = {189, 0, "DEV_I2C2_PISYS_CLK", "Input clock"},
+        [1111] = {189, 1, "DEV_I2C2_PISCL_0", "Input clock"},
+        [1112] = {189, 2, "DEV_I2C2_CLK", "Input clock"},
+        [1113] = {190, 0, "DEV_I2C3_PISYS_CLK", "Input clock"},
+        [1114] = {190, 1, "DEV_I2C3_PISCL_0", "Input clock"},
+        [1115] = {190, 2, "DEV_I2C3_CLK", "Input clock"},
+        [1116] = {191, 0, "DEV_I2C4_PISYS_CLK", "Input clock"},
+        [1117] = {191, 1, "DEV_I2C4_PISCL_0", "Input clock"},
+        [1118] = {191, 2, "DEV_I2C4_CLK", "Input clock"},
+        [1119] = {192, 0, "DEV_I2C5_PISYS_CLK", "Input clock"},
+        [1120] = {192, 1, "DEV_I2C5_PISCL_0", "Input clock"},
+        [1121] = {192, 2, "DEV_I2C5_CLK", "Input clock"},
+        [1122] = {193, 0, "DEV_I2C6_PISYS_CLK", "Input clock"},
+        [1123] = {193, 1, "DEV_I2C6_PISCL_0", "Input clock"},
+        [1124] = {193, 2, "DEV_I2C6_CLK", "Input clock"},
+        [1125] = {116, 0, "DEV_I3C0_I3C_PCLK_CLK", "Input clock"},
+        [1126] = {116, 1, "DEV_I3C0_I3C_SCL_DI", "Input clock"},
+        [1127] = {116, 2, "DEV_I3C0_I3C_SCLK_CLK", "Input clock"},
+        [1128] = {116, 3, "DEV_I3C0_I3C_SCL_DO_0", "Output clock"},
+        [1129] = {127, 0, "DEV_LED0_LED_CLK", "Input clock"},
+        [1130] = {127, 1, "DEV_LED0_VBUS_CLK", "Input clock"},
+        [1131] = {128, 0, "DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK", "Input clock"},
+        [1132] = {130, 0, "DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK", "Input clock"},
+        [1133] = {156, 0, "DEV_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+        [1134] = {156, 1, "DEV_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1135] = {156, 2, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+        [1136] = {156, 3, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+        [1137] = {156, 4, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+        [1138] = {156, 5, "DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK"},
+        [1139] = {158, 0, "DEV_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+        [1140] = {158, 1, "DEV_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1141] = {158, 2, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+        [1142] = {158, 3, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+        [1143] = {158, 4, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+        [1144] = {158, 5, "DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK"},
+        [1145] = {168, 0, "DEV_MCAN10_MCANSS_HCLK_CLK", "Input clock"},
+        [1146] = {168, 1, "DEV_MCAN10_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1147] = {168, 2, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+        [1148] = {168, 3, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+        [1149] = {168, 4, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+        [1150] = {168, 5, "DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK"},
+        [1151] = {169, 0, "DEV_MCAN11_MCANSS_HCLK_CLK", "Input clock"},
+        [1152] = {169, 1, "DEV_MCAN11_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1153] = {169, 2, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+        [1154] = {169, 3, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+        [1155] = {169, 4, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+        [1156] = {169, 5, "DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK"},
+        [1157] = {170, 0, "DEV_MCAN12_MCANSS_HCLK_CLK", "Input clock"},
+        [1158] = {170, 1, "DEV_MCAN12_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1159] = {170, 2, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+        [1160] = {170, 3, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+        [1161] = {170, 4, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+        [1162] = {170, 5, "DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK"},
+        [1163] = {171, 0, "DEV_MCAN13_MCANSS_HCLK_CLK", "Input clock"},
+        [1164] = {171, 1, "DEV_MCAN13_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1165] = {171, 2, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+        [1166] = {171, 3, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+        [1167] = {171, 4, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+        [1168] = {171, 5, "DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK"},
+        [1169] = {160, 0, "DEV_MCAN2_MCANSS_HCLK_CLK", "Input clock"},
+        [1170] = {160, 1, "DEV_MCAN2_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1171] = {160, 2, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+        [1172] = {160, 3, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+        [1173] = {160, 4, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+        [1174] = {160, 5, "DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK"},
+        [1175] = {161, 0, "DEV_MCAN3_MCANSS_HCLK_CLK", "Input clock"},
+        [1176] = {161, 1, "DEV_MCAN3_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1177] = {161, 2, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+        [1178] = {161, 3, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+        [1179] = {161, 4, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+        [1180] = {161, 5, "DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK"},
+        [1181] = {162, 0, "DEV_MCAN4_MCANSS_HCLK_CLK", "Input clock"},
+        [1182] = {162, 1, "DEV_MCAN4_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1183] = {162, 2, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+        [1184] = {162, 3, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+        [1185] = {162, 4, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+        [1186] = {162, 5, "DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK"},
+        [1187] = {163, 0, "DEV_MCAN5_MCANSS_HCLK_CLK", "Input clock"},
+        [1188] = {163, 1, "DEV_MCAN5_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1189] = {163, 2, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+        [1190] = {163, 3, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+        [1191] = {163, 4, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+        [1192] = {163, 5, "DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK"},
+        [1193] = {164, 0, "DEV_MCAN6_MCANSS_HCLK_CLK", "Input clock"},
+        [1194] = {164, 1, "DEV_MCAN6_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1195] = {164, 2, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+        [1196] = {164, 3, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+        [1197] = {164, 4, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+        [1198] = {164, 5, "DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK"},
+        [1199] = {165, 0, "DEV_MCAN7_MCANSS_HCLK_CLK", "Input clock"},
+        [1200] = {165, 1, "DEV_MCAN7_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1201] = {165, 2, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+        [1202] = {165, 3, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+        [1203] = {165, 4, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+        [1204] = {165, 5, "DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK"},
+        [1205] = {166, 0, "DEV_MCAN8_MCANSS_HCLK_CLK", "Input clock"},
+        [1206] = {166, 1, "DEV_MCAN8_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1207] = {166, 2, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+        [1208] = {166, 3, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+        [1209] = {166, 4, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+        [1210] = {166, 5, "DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK"},
+        [1211] = {167, 0, "DEV_MCAN9_MCANSS_HCLK_CLK", "Input clock"},
+        [1212] = {167, 1, "DEV_MCAN9_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1213] = {167, 2, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+        [1214] = {167, 3, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+        [1215] = {167, 4, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+        [1216] = {167, 5, "DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK"},
+        [1217] = {174, 11, "DEV_MCASP0_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1218] = {174, 13, "DEV_MCASP0_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1219] = {174, 29, "DEV_MCASP0_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1220] = {174, 30, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1221] = {174, 31, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1222] = {174, 32, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1223] = {174, 33, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1224] = {174, 34, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1225] = {174, 35, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1226] = {174, 36, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1227] = {174, 37, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1228] = {174, 38, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1229] = {174, 39, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1230] = {174, 40, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1231] = {174, 41, "DEV_MCASP0_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN_0"},
+        [1232] = {174, 0, "DEV_MCASP0_VBUSP_CLK", "Input clock"},
+        [1233] = {174, 1, "DEV_MCASP0_AUX_CLK", "Input muxed clock"},
+        [1234] = {174, 2, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+        [1235] = {174, 3, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+        [1236] = {174, 4, "DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+        [1237] = {174, 6, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+        [1238] = {174, 7, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+        [1239] = {174, 8, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+        [1240] = {174, 9, "DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_AUX_CLK"},
+        [1241] = {174, 15, "DEV_MCASP0_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1242] = {174, 16, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1243] = {174, 17, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1244] = {174, 18, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1245] = {174, 19, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1246] = {174, 20, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1247] = {174, 21, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1248] = {174, 22, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1249] = {174, 23, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1250] = {174, 24, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1251] = {174, 25, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1252] = {174, 26, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1253] = {174, 27, "DEV_MCASP0_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN_0"},
+        [1254] = {174, 12, "DEV_MCASP0_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1255] = {174, 14, "DEV_MCASP0_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1256] = {174, 28, "DEV_MCASP0_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1257] = {174, 10, "DEV_MCASP0_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1258] = {175, 11, "DEV_MCASP1_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1259] = {175, 13, "DEV_MCASP1_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1260] = {175, 29, "DEV_MCASP1_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1261] = {175, 30, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1262] = {175, 31, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1263] = {175, 32, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1264] = {175, 33, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1265] = {175, 34, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1266] = {175, 35, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1267] = {175, 36, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1268] = {175, 37, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1269] = {175, 38, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1270] = {175, 39, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1271] = {175, 40, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1272] = {175, 41, "DEV_MCASP1_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN_0"},
+        [1273] = {175, 0, "DEV_MCASP1_VBUSP_CLK", "Input clock"},
+        [1274] = {175, 1, "DEV_MCASP1_AUX_CLK", "Input muxed clock"},
+        [1275] = {175, 2, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+        [1276] = {175, 3, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+        [1277] = {175, 4, "DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+        [1278] = {175, 6, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+        [1279] = {175, 7, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+        [1280] = {175, 8, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+        [1281] = {175, 9, "DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_AUX_CLK"},
+        [1282] = {175, 15, "DEV_MCASP1_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1283] = {175, 16, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1284] = {175, 17, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1285] = {175, 18, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1286] = {175, 19, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1287] = {175, 20, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1288] = {175, 21, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1289] = {175, 22, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1290] = {175, 23, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1291] = {175, 24, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1292] = {175, 25, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1293] = {175, 26, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1294] = {175, 27, "DEV_MCASP1_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN_0"},
+        [1295] = {175, 12, "DEV_MCASP1_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1296] = {175, 14, "DEV_MCASP1_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1297] = {175, 28, "DEV_MCASP1_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1298] = {175, 10, "DEV_MCASP1_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1299] = {184, 11, "DEV_MCASP10_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1300] = {184, 13, "DEV_MCASP10_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1301] = {184, 29, "DEV_MCASP10_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1302] = {184, 30, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1303] = {184, 31, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1304] = {184, 32, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1305] = {184, 33, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1306] = {184, 34, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1307] = {184, 35, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1308] = {184, 36, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1309] = {184, 37, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1310] = {184, 38, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1311] = {184, 39, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1312] = {184, 40, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1313] = {184, 41, "DEV_MCASP10_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN_0"},
+        [1314] = {184, 0, "DEV_MCASP10_VBUSP_CLK", "Input clock"},
+        [1315] = {184, 1, "DEV_MCASP10_AUX_CLK", "Input muxed clock"},
+        [1316] = {184, 2, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+        [1317] = {184, 3, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+        [1318] = {184, 4, "DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+        [1319] = {184, 6, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+        [1320] = {184, 7, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+        [1321] = {184, 8, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+        [1322] = {184, 9, "DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_AUX_CLK"},
+        [1323] = {184, 15, "DEV_MCASP10_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1324] = {184, 16, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1325] = {184, 17, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1326] = {184, 18, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1327] = {184, 19, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1328] = {184, 20, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1329] = {184, 21, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1330] = {184, 22, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1331] = {184, 23, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1332] = {184, 24, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1333] = {184, 25, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1334] = {184, 26, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1335] = {184, 27, "DEV_MCASP10_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN_0"},
+        [1336] = {184, 12, "DEV_MCASP10_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1337] = {184, 14, "DEV_MCASP10_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1338] = {184, 28, "DEV_MCASP10_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1339] = {184, 10, "DEV_MCASP10_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1340] = {185, 11, "DEV_MCASP11_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1341] = {185, 13, "DEV_MCASP11_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1342] = {185, 29, "DEV_MCASP11_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1343] = {185, 30, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1344] = {185, 31, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1345] = {185, 32, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1346] = {185, 33, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1347] = {185, 34, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1348] = {185, 35, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1349] = {185, 36, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1350] = {185, 37, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1351] = {185, 38, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1352] = {185, 39, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1353] = {185, 40, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1354] = {185, 41, "DEV_MCASP11_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN_0"},
+        [1355] = {185, 0, "DEV_MCASP11_VBUSP_CLK", "Input clock"},
+        [1356] = {185, 1, "DEV_MCASP11_AUX_CLK", "Input muxed clock"},
+        [1357] = {185, 2, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+        [1358] = {185, 3, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+        [1359] = {185, 4, "DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+        [1360] = {185, 6, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+        [1361] = {185, 7, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+        [1362] = {185, 8, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+        [1363] = {185, 9, "DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_AUX_CLK"},
+        [1364] = {185, 15, "DEV_MCASP11_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1365] = {185, 16, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1366] = {185, 17, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1367] = {185, 18, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1368] = {185, 19, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1369] = {185, 20, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1370] = {185, 21, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1371] = {185, 22, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1372] = {185, 23, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1373] = {185, 24, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1374] = {185, 25, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1375] = {185, 26, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1376] = {185, 27, "DEV_MCASP11_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN_0"},
+        [1377] = {185, 12, "DEV_MCASP11_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1378] = {185, 14, "DEV_MCASP11_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1379] = {185, 28, "DEV_MCASP11_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1380] = {185, 10, "DEV_MCASP11_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1381] = {176, 11, "DEV_MCASP2_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1382] = {176, 13, "DEV_MCASP2_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1383] = {176, 29, "DEV_MCASP2_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1384] = {176, 30, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1385] = {176, 31, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1386] = {176, 32, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1387] = {176, 33, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1388] = {176, 34, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1389] = {176, 35, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1390] = {176, 36, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1391] = {176, 37, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1392] = {176, 38, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1393] = {176, 39, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1394] = {176, 40, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1395] = {176, 41, "DEV_MCASP2_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN_0"},
+        [1396] = {176, 0, "DEV_MCASP2_VBUSP_CLK", "Input clock"},
+        [1397] = {176, 1, "DEV_MCASP2_AUX_CLK", "Input muxed clock"},
+        [1398] = {176, 2, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+        [1399] = {176, 3, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+        [1400] = {176, 4, "DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+        [1401] = {176, 6, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+        [1402] = {176, 7, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+        [1403] = {176, 8, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+        [1404] = {176, 9, "DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_AUX_CLK"},
+        [1405] = {176, 15, "DEV_MCASP2_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1406] = {176, 16, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1407] = {176, 17, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1408] = {176, 18, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1409] = {176, 19, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1410] = {176, 20, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1411] = {176, 21, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1412] = {176, 22, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1413] = {176, 23, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1414] = {176, 24, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1415] = {176, 25, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1416] = {176, 26, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1417] = {176, 27, "DEV_MCASP2_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN_0"},
+        [1418] = {176, 12, "DEV_MCASP2_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1419] = {176, 14, "DEV_MCASP2_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1420] = {176, 28, "DEV_MCASP2_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1421] = {176, 10, "DEV_MCASP2_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1422] = {177, 11, "DEV_MCASP3_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1423] = {177, 13, "DEV_MCASP3_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1424] = {177, 29, "DEV_MCASP3_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1425] = {177, 30, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1426] = {177, 31, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1427] = {177, 32, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1428] = {177, 33, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1429] = {177, 34, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1430] = {177, 35, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1431] = {177, 36, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1432] = {177, 37, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1433] = {177, 38, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1434] = {177, 39, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1435] = {177, 40, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1436] = {177, 41, "DEV_MCASP3_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN_0"},
+        [1437] = {177, 0, "DEV_MCASP3_VBUSP_CLK", "Input clock"},
+        [1438] = {177, 1, "DEV_MCASP3_AUX_CLK", "Input muxed clock"},
+        [1439] = {177, 2, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+        [1440] = {177, 3, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+        [1441] = {177, 4, "DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+        [1442] = {177, 6, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+        [1443] = {177, 7, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+        [1444] = {177, 8, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+        [1445] = {177, 9, "DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_AUX_CLK"},
+        [1446] = {177, 15, "DEV_MCASP3_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1447] = {177, 16, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1448] = {177, 17, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1449] = {177, 18, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1450] = {177, 19, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1451] = {177, 20, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1452] = {177, 21, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1453] = {177, 22, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1454] = {177, 23, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1455] = {177, 24, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1456] = {177, 25, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1457] = {177, 26, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1458] = {177, 27, "DEV_MCASP3_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN_0"},
+        [1459] = {177, 12, "DEV_MCASP3_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1460] = {177, 14, "DEV_MCASP3_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1461] = {177, 28, "DEV_MCASP3_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1462] = {177, 10, "DEV_MCASP3_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1463] = {178, 11, "DEV_MCASP4_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1464] = {178, 13, "DEV_MCASP4_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1465] = {178, 29, "DEV_MCASP4_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1466] = {178, 30, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1467] = {178, 31, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1468] = {178, 32, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1469] = {178, 33, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1470] = {178, 34, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1471] = {178, 35, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1472] = {178, 36, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1473] = {178, 37, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1474] = {178, 38, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1475] = {178, 39, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1476] = {178, 40, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1477] = {178, 41, "DEV_MCASP4_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN_0"},
+        [1478] = {178, 0, "DEV_MCASP4_VBUSP_CLK", "Input clock"},
+        [1479] = {178, 1, "DEV_MCASP4_AUX_CLK", "Input muxed clock"},
+        [1480] = {178, 2, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+        [1481] = {178, 3, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+        [1482] = {178, 4, "DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+        [1483] = {178, 6, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+        [1484] = {178, 7, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+        [1485] = {178, 8, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+        [1486] = {178, 9, "DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_AUX_CLK"},
+        [1487] = {178, 15, "DEV_MCASP4_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1488] = {178, 16, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1489] = {178, 17, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1490] = {178, 18, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1491] = {178, 19, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1492] = {178, 20, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1493] = {178, 21, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1494] = {178, 22, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1495] = {178, 23, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1496] = {178, 24, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1497] = {178, 25, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1498] = {178, 26, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1499] = {178, 27, "DEV_MCASP4_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN_0"},
+        [1500] = {178, 12, "DEV_MCASP4_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1501] = {178, 14, "DEV_MCASP4_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1502] = {178, 28, "DEV_MCASP4_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1503] = {178, 10, "DEV_MCASP4_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1504] = {179, 11, "DEV_MCASP5_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1505] = {179, 13, "DEV_MCASP5_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1506] = {179, 29, "DEV_MCASP5_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1507] = {179, 30, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1508] = {179, 31, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1509] = {179, 32, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1510] = {179, 33, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1511] = {179, 34, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1512] = {179, 35, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1513] = {179, 36, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1514] = {179, 37, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1515] = {179, 38, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1516] = {179, 39, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1517] = {179, 40, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1518] = {179, 41, "DEV_MCASP5_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN_0"},
+        [1519] = {179, 0, "DEV_MCASP5_VBUSP_CLK", "Input clock"},
+        [1520] = {179, 1, "DEV_MCASP5_AUX_CLK", "Input muxed clock"},
+        [1521] = {179, 2, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+        [1522] = {179, 3, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+        [1523] = {179, 4, "DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+        [1524] = {179, 6, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+        [1525] = {179, 7, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+        [1526] = {179, 8, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+        [1527] = {179, 9, "DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_AUX_CLK"},
+        [1528] = {179, 15, "DEV_MCASP5_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1529] = {179, 16, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1530] = {179, 17, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1531] = {179, 18, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1532] = {179, 19, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1533] = {179, 20, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1534] = {179, 21, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1535] = {179, 22, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1536] = {179, 23, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1537] = {179, 24, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1538] = {179, 25, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1539] = {179, 26, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1540] = {179, 27, "DEV_MCASP5_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN_0"},
+        [1541] = {179, 12, "DEV_MCASP5_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1542] = {179, 14, "DEV_MCASP5_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1543] = {179, 28, "DEV_MCASP5_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1544] = {179, 10, "DEV_MCASP5_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1545] = {180, 11, "DEV_MCASP6_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1546] = {180, 13, "DEV_MCASP6_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1547] = {180, 29, "DEV_MCASP6_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1548] = {180, 30, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1549] = {180, 31, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1550] = {180, 32, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1551] = {180, 33, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1552] = {180, 34, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1553] = {180, 35, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1554] = {180, 36, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1555] = {180, 37, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1556] = {180, 38, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1557] = {180, 39, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1558] = {180, 40, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1559] = {180, 41, "DEV_MCASP6_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN_0"},
+        [1560] = {180, 0, "DEV_MCASP6_VBUSP_CLK", "Input clock"},
+        [1561] = {180, 1, "DEV_MCASP6_AUX_CLK", "Input muxed clock"},
+        [1562] = {180, 2, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+        [1563] = {180, 3, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+        [1564] = {180, 4, "DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+        [1565] = {180, 6, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+        [1566] = {180, 7, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+        [1567] = {180, 8, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+        [1568] = {180, 9, "DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_AUX_CLK"},
+        [1569] = {180, 15, "DEV_MCASP6_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1570] = {180, 16, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1571] = {180, 17, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1572] = {180, 18, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1573] = {180, 19, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1574] = {180, 20, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1575] = {180, 21, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1576] = {180, 22, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1577] = {180, 23, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1578] = {180, 24, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1579] = {180, 25, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1580] = {180, 26, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1581] = {180, 27, "DEV_MCASP6_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN_0"},
+        [1582] = {180, 12, "DEV_MCASP6_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1583] = {180, 14, "DEV_MCASP6_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1584] = {180, 28, "DEV_MCASP6_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1585] = {180, 10, "DEV_MCASP6_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1586] = {181, 11, "DEV_MCASP7_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1587] = {181, 13, "DEV_MCASP7_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1588] = {181, 29, "DEV_MCASP7_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1589] = {181, 30, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1590] = {181, 31, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1591] = {181, 32, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1592] = {181, 33, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1593] = {181, 34, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1594] = {181, 35, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1595] = {181, 36, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1596] = {181, 37, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1597] = {181, 38, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1598] = {181, 39, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1599] = {181, 40, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1600] = {181, 41, "DEV_MCASP7_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN_0"},
+        [1601] = {181, 0, "DEV_MCASP7_VBUSP_CLK", "Input clock"},
+        [1602] = {181, 1, "DEV_MCASP7_AUX_CLK", "Input muxed clock"},
+        [1603] = {181, 2, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+        [1604] = {181, 3, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+        [1605] = {181, 4, "DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+        [1606] = {181, 6, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+        [1607] = {181, 7, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+        [1608] = {181, 8, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+        [1609] = {181, 9, "DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_AUX_CLK"},
+        [1610] = {181, 15, "DEV_MCASP7_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1611] = {181, 16, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1612] = {181, 17, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1613] = {181, 18, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1614] = {181, 19, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1615] = {181, 20, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1616] = {181, 21, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1617] = {181, 22, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1618] = {181, 23, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1619] = {181, 24, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1620] = {181, 25, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1621] = {181, 26, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1622] = {181, 27, "DEV_MCASP7_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN_0"},
+        [1623] = {181, 12, "DEV_MCASP7_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1624] = {181, 14, "DEV_MCASP7_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1625] = {181, 28, "DEV_MCASP7_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1626] = {181, 10, "DEV_MCASP7_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1627] = {182, 11, "DEV_MCASP8_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1628] = {182, 13, "DEV_MCASP8_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1629] = {182, 29, "DEV_MCASP8_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1630] = {182, 30, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1631] = {182, 31, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1632] = {182, 32, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1633] = {182, 33, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1634] = {182, 34, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1635] = {182, 35, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1636] = {182, 36, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1637] = {182, 37, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1638] = {182, 38, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1639] = {182, 39, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1640] = {182, 40, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1641] = {182, 41, "DEV_MCASP8_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN_0"},
+        [1642] = {182, 0, "DEV_MCASP8_VBUSP_CLK", "Input clock"},
+        [1643] = {182, 1, "DEV_MCASP8_AUX_CLK", "Input muxed clock"},
+        [1644] = {182, 2, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
+        [1645] = {182, 3, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
+        [1646] = {182, 4, "DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
+        [1647] = {182, 6, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
+        [1648] = {182, 7, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
+        [1649] = {182, 8, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
+        [1650] = {182, 9, "DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_AUX_CLK"},
+        [1651] = {182, 15, "DEV_MCASP8_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1652] = {182, 16, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1653] = {182, 17, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1654] = {182, 18, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1655] = {182, 19, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1656] = {182, 20, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1657] = {182, 21, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1658] = {182, 22, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1659] = {182, 23, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1660] = {182, 24, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1661] = {182, 25, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1662] = {182, 26, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1663] = {182, 27, "DEV_MCASP8_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN_0"},
+        [1664] = {182, 12, "DEV_MCASP8_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1665] = {182, 14, "DEV_MCASP8_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1666] = {182, 28, "DEV_MCASP8_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1667] = {182, 10, "DEV_MCASP8_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1668] = {183, 11, "DEV_MCASP9_MCASP_ACLKX_PIN_0", "Input clock"},
+        [1669] = {183, 13, "DEV_MCASP9_MCASP_ACLKR_PIN_0", "Input clock"},
+        [1670] = {183, 29, "DEV_MCASP9_MCASP_AHCLKR_PIN_0", "Input muxed clock"},
+        [1671] = {183, 30, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1672] = {183, 31, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1673] = {183, 32, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1674] = {183, 33, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1675] = {183, 34, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1676] = {183, 35, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1677] = {183, 36, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1678] = {183, 37, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1679] = {183, 38, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1680] = {183, 39, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1681] = {183, 40, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1682] = {183, 41, "DEV_MCASP9_MCASP_AHCLKR_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN_0"},
+        [1683] = {183, 0, "DEV_MCASP9_VBUSP_CLK", "Input clock"},
+        [1684] = {183, 1, "DEV_MCASP9_AUX_CLK", "Input muxed clock"},
+        [1685] = {183, 2, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
+        [1686] = {183, 3, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
+        [1687] = {183, 4, "DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
+        [1688] = {183, 6, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
+        [1689] = {183, 7, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
+        [1690] = {183, 8, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
+        [1691] = {183, 9, "DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_AUX_CLK"},
+        [1692] = {183, 15, "DEV_MCASP9_MCASP_AHCLKX_PIN_0", "Input muxed clock"},
+        [1693] = {183, 16, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1694] = {183, 17, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1695] = {183, 18, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1696] = {183, 19, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1697] = {183, 20, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1698] = {183, 21, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_MCASP_AHCLKO_MUX_OUT3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1699] = {183, 22, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCLK_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1700] = {183, 23, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_BOARD_0_MLB0_MLBCP_OUT", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1701] = {183, 24, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_0", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1702] = {183, 25, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1703] = {183, 26, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1704] = {183, 27, "DEV_MCASP9_MCASP_AHCLKX_PIN_0_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3", "Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN_0"},
+        [1705] = {183, 12, "DEV_MCASP9_MCASP_ACLKR_POUT_0", "Output clock"},
+        [1706] = {183, 14, "DEV_MCASP9_MCASP_AHCLKX_POUT_0", "Output clock"},
+        [1707] = {183, 28, "DEV_MCASP9_MCASP_AHCLKR_POUT_0", "Output clock"},
+        [1708] = {183, 10, "DEV_MCASP9_MCASP_ACLKX_POUT_0", "Output clock"},
+        [1709] = {266, 0, "DEV_MCSPI0_VBUSP_CLK", "Input clock"},
+        [1710] = {266, 1, "DEV_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+        [1711] = {266, 2, "DEV_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+        [1712] = {267, 0, "DEV_MCSPI1_VBUSP_CLK", "Input clock"},
+        [1713] = {267, 1, "DEV_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+        [1714] = {267, 2, "DEV_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+        [1715] = {268, 0, "DEV_MCSPI2_VBUSP_CLK", "Input clock"},
+        [1716] = {268, 1, "DEV_MCSPI2_CLKSPIREF_CLK", "Input clock"},
+        [1717] = {268, 2, "DEV_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
+        [1718] = {269, 0, "DEV_MCSPI3_VBUSP_CLK", "Input clock"},
+        [1719] = {269, 1, "DEV_MCSPI3_CLKSPIREF_CLK", "Input clock"},
+        [1720] = {269, 2, "DEV_MCSPI3_IO_CLKSPII_CLK", "Input muxed clock"},
+        [1721] = {269, 3, "DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK"},
+        [1722] = {269, 4, "DEV_MCSPI3_IO_CLKSPIO_CLK", "Output clock"},
+        [1723] = {270, 0, "DEV_MCSPI4_VBUSP_CLK", "Input clock"},
+        [1724] = {270, 1, "DEV_MCSPI4_CLKSPIREF_CLK", "Input clock"},
+        [1725] = {270, 2, "DEV_MCSPI4_IO_CLKSPII_CLK", "Input clock"},
+        [1726] = {270, 3, "DEV_MCSPI4_IO_CLKSPIO_CLK", "Output clock"},
+        [1727] = {271, 0, "DEV_MCSPI5_VBUSP_CLK", "Input clock"},
+        [1728] = {271, 1, "DEV_MCSPI5_CLKSPIREF_CLK", "Input clock"},
+        [1729] = {271, 2, "DEV_MCSPI5_IO_CLKSPIO_CLK", "Output clock"},
+        [1730] = {272, 0, "DEV_MCSPI6_VBUSP_CLK", "Input clock"},
+        [1731] = {272, 1, "DEV_MCSPI6_CLKSPIREF_CLK", "Input clock"},
+        [1732] = {272, 2, "DEV_MCSPI6_IO_CLKSPIO_CLK", "Output clock"},
+        [1733] = {273, 0, "DEV_MCSPI7_VBUSP_CLK", "Input clock"},
+        [1734] = {273, 1, "DEV_MCSPI7_CLKSPIREF_CLK", "Input clock"},
+        [1735] = {273, 2, "DEV_MCSPI7_IO_CLKSPIO_CLK", "Output clock"},
+        [1736] = {0, 0, "DEV_MCU_ADC0_SYS_CLK", "Input clock"},
+        [1737] = {0, 1, "DEV_MCU_ADC0_ADC_CLK", "Input muxed clock"},
+        [1738] = {0, 2, "DEV_MCU_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+        [1739] = {0, 3, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+        [1740] = {0, 4, "DEV_MCU_ADC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+        [1741] = {0, 5, "DEV_MCU_ADC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC0_ADC_CLK"},
+        [1742] = {0, 6, "DEV_MCU_ADC0_VBUS_CLK", "Input clock"},
+        [1743] = {1, 0, "DEV_MCU_ADC1_SYS_CLK", "Input clock"},
+        [1744] = {1, 1, "DEV_MCU_ADC1_ADC_CLK", "Input muxed clock"},
+        [1745] = {1, 2, "DEV_MCU_ADC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+        [1746] = {1, 3, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+        [1747] = {1, 4, "DEV_MCU_ADC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+        [1748] = {1, 5, "DEV_MCU_ADC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_ADC1_ADC_CLK"},
+        [1749] = {1, 6, "DEV_MCU_ADC1_VBUS_CLK", "Input clock"},
+        [1750] = {18, 0, "DEV_MCU_CPSW0_RGMII1_RXC_I", "Input clock"},
+        [1751] = {18, 1, "DEV_MCU_CPSW0_RGMII_MHZ_250_CLK", "Input clock"},
+        [1752] = {18, 2, "DEV_MCU_CPSW0_CPTS_RFT_CLK", "Input muxed clock"},
+        [1753] = {18, 3, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1754] = {18, 4, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1755] = {18, 5, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1756] = {18, 6, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1757] = {18, 7, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1758] = {18, 8, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1759] = {18, 9, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1760] = {18, 10, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1761] = {18, 11, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1762] = {18, 12, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1763] = {18, 13, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1764] = {18, 14, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1765] = {18, 15, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1766] = {18, 16, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1767] = {18, 17, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1768] = {18, 18, "DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK"},
+        [1769] = {18, 19, "DEV_MCU_CPSW0_GMII_RFT_CLK", "Input clock"},
+        [1770] = {18, 20, "DEV_MCU_CPSW0_RMII_MHZ_50_CLK", "Input clock"},
+        [1771] = {18, 21, "DEV_MCU_CPSW0_RGMII_MHZ_50_CLK", "Input clock"},
+        [1772] = {18, 22, "DEV_MCU_CPSW0_CPPI_CLK_CLK", "Input clock"},
+        [1773] = {18, 23, "DEV_MCU_CPSW0_RGMII_MHZ_5_CLK", "Input clock"},
+        [1774] = {18, 24, "DEV_MCU_CPSW0_GMII1_MR_CLK", "Input clock"},
+        [1775] = {18, 25, "DEV_MCU_CPSW0_GMII1_MT_CLK", "Input clock"},
+        [1776] = {18, 26, "DEV_MCU_CPSW0_RGMII1_TXC_I", "Input clock"},
+        [1777] = {18, 27, "DEV_MCU_CPSW0_RGMII1_TXC_O", "Output clock"},
+        [1778] = {18, 28, "DEV_MCU_CPSW0_CPTS_GENF0_0", "Output clock"},
+        [1779] = {18, 29, "DEV_MCU_CPSW0_MDIO_MDCLK_O_0", "Output clock"},
+        [1780] = {24, 0, "DEV_MCU_CPT2_AGGR0_VCLK_CLK", "Input clock"},
+        [1781] = {44, 0, "DEV_MCU_DCC0_DCC_INPUT10_CLK", "Input clock"},
+        [1782] = {44, 1, "DEV_MCU_DCC0_DCC_INPUT01_CLK", "Input clock"},
+        [1783] = {44, 2, "DEV_MCU_DCC0_DCC_CLKSRC2_CLK", "Input clock"},
+        [1784] = {44, 3, "DEV_MCU_DCC0_DCC_CLKSRC7_CLK", "Input clock"},
+        [1785] = {44, 4, "DEV_MCU_DCC0_DCC_CLKSRC0_CLK", "Input clock"},
+        [1786] = {44, 5, "DEV_MCU_DCC0_VBUS_CLK", "Input clock"},
+        [1787] = {44, 6, "DEV_MCU_DCC0_DCC_CLKSRC4_CLK", "Input clock"},
+        [1788] = {44, 7, "DEV_MCU_DCC0_DCC_CLKSRC1_CLK", "Input clock"},
+        [1789] = {44, 8, "DEV_MCU_DCC0_DCC_CLKSRC3_CLK", "Input clock"},
+        [1790] = {44, 9, "DEV_MCU_DCC0_DCC_INPUT00_CLK", "Input clock"},
+        [1791] = {44, 10, "DEV_MCU_DCC0_DCC_CLKSRC5_CLK", "Input clock"},
+        [1792] = {44, 11, "DEV_MCU_DCC0_DCC_CLKSRC6_CLK", "Input clock"},
+        [1793] = {44, 12, "DEV_MCU_DCC0_DCC_INPUT02_CLK", "Input clock"},
+        [1794] = {45, 0, "DEV_MCU_DCC1_DCC_INPUT10_CLK", "Input clock"},
+        [1795] = {45, 1, "DEV_MCU_DCC1_DCC_INPUT01_CLK", "Input clock"},
+        [1796] = {45, 2, "DEV_MCU_DCC1_DCC_CLKSRC2_CLK", "Input clock"},
+        [1797] = {45, 3, "DEV_MCU_DCC1_DCC_CLKSRC7_CLK", "Input clock"},
+        [1798] = {45, 4, "DEV_MCU_DCC1_DCC_CLKSRC0_CLK", "Input clock"},
+        [1799] = {45, 5, "DEV_MCU_DCC1_VBUS_CLK", "Input clock"},
+        [1800] = {45, 6, "DEV_MCU_DCC1_DCC_CLKSRC4_CLK", "Input clock"},
+        [1801] = {45, 7, "DEV_MCU_DCC1_DCC_CLKSRC1_CLK", "Input clock"},
+        [1802] = {45, 8, "DEV_MCU_DCC1_DCC_CLKSRC3_CLK", "Input clock"},
+        [1803] = {45, 9, "DEV_MCU_DCC1_DCC_INPUT00_CLK", "Input clock"},
+        [1804] = {45, 10, "DEV_MCU_DCC1_DCC_CLKSRC5_CLK", "Input clock"},
+        [1805] = {45, 11, "DEV_MCU_DCC1_DCC_CLKSRC6_CLK", "Input clock"},
+        [1806] = {45, 12, "DEV_MCU_DCC1_DCC_INPUT02_CLK", "Input clock"},
+        [1807] = {46, 0, "DEV_MCU_DCC2_DCC_INPUT10_CLK", "Input clock"},
+        [1808] = {46, 1, "DEV_MCU_DCC2_DCC_INPUT01_CLK", "Input clock"},
+        [1809] = {46, 2, "DEV_MCU_DCC2_DCC_CLKSRC7_CLK", "Input clock"},
+        [1810] = {46, 3, "DEV_MCU_DCC2_DCC_CLKSRC0_CLK", "Input clock"},
+        [1811] = {46, 4, "DEV_MCU_DCC2_VBUS_CLK", "Input clock"},
+        [1812] = {46, 5, "DEV_MCU_DCC2_DCC_CLKSRC4_CLK", "Input clock"},
+        [1813] = {46, 6, "DEV_MCU_DCC2_DCC_CLKSRC1_CLK", "Input clock"},
+        [1814] = {46, 7, "DEV_MCU_DCC2_DCC_CLKSRC3_CLK", "Input clock"},
+        [1815] = {46, 8, "DEV_MCU_DCC2_DCC_INPUT00_CLK", "Input clock"},
+        [1816] = {46, 9, "DEV_MCU_DCC2_DCC_CLKSRC6_CLK", "Input clock"},
+        [1817] = {46, 10, "DEV_MCU_DCC2_DCC_INPUT02_CLK", "Input clock"},
+        [1818] = {98, 0, "DEV_MCU_ESM0_CLK", "Input clock"},
+        [1819] = {101, 0, "DEV_MCU_FSS0_FSAS_0_GCLK", "Input clock"},
+        [1820] = {102, 0, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK", "Input clock"},
+        [1821] = {102, 1, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK", "Input clock"},
+        [1822] = {102, 2, "DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK", "Input clock"},
+        [1823] = {102, 3, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK", "Input clock"},
+        [1824] = {102, 4, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK", "Input clock"},
+        [1825] = {102, 5, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N", "Output clock"},
+        [1826] = {102, 6, "DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P", "Output clock"},
+        [1827] = {103, 0, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK", "Input muxed clock"},
+        [1828] = {103, 1, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+        [1829] = {103, 2, "DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK"},
+        [1830] = {103, 3, "DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK", "Input clock"},
+        [1831] = {103, 4, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK", "Input muxed clock"},
+        [1832] = {103, 5, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+        [1833] = {103, 6, "DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK"},
+        [1834] = {103, 7, "DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK", "Input clock"},
+        [1835] = {103, 8, "DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK", "Input clock"},
+        [1836] = {103, 9, "DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK", "Output clock"},
+        [1837] = {104, 0, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK", "Input muxed clock"},
+        [1838] = {104, 1, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
+        [1839] = {104, 2, "DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK"},
+        [1840] = {104, 3, "DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK", "Input clock"},
+        [1841] = {104, 4, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK", "Input muxed clock"},
+        [1842] = {104, 5, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
+        [1843] = {104, 6, "DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK", "Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK"},
+        [1844] = {104, 7, "DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK", "Input clock"},
+        [1845] = {104, 8, "DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK", "Input clock"},
+        [1846] = {104, 9, "DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK", "Output clock"},
+        [1847] = {194, 0, "DEV_MCU_I2C0_PISYS_CLK", "Input clock"},
+        [1848] = {194, 1, "DEV_MCU_I2C0_PISCL_0", "Input clock"},
+        [1849] = {194, 2, "DEV_MCU_I2C0_CLK", "Input clock"},
+        [1850] = {194, 3, "DEV_MCU_I2C0_PORSCL_0", "Output clock"},
+        [1851] = {195, 0, "DEV_MCU_I2C1_PISYS_CLK", "Input clock"},
+        [1852] = {195, 1, "DEV_MCU_I2C1_PISCL_0", "Input clock"},
+        [1853] = {195, 2, "DEV_MCU_I2C1_CLK", "Input clock"},
+        [1854] = {117, 0, "DEV_MCU_I3C0_I3C_PCLK_CLK", "Input clock"},
+        [1855] = {117, 1, "DEV_MCU_I3C0_I3C_SCL_DI", "Input clock"},
+        [1856] = {117, 2, "DEV_MCU_I3C0_I3C_SCLK_CLK", "Input clock"},
+        [1857] = {117, 3, "DEV_MCU_I3C0_I3C_SCL_DO_0", "Output clock"},
+        [1858] = {118, 0, "DEV_MCU_I3C1_I3C_PCLK_CLK", "Input clock"},
+        [1859] = {118, 1, "DEV_MCU_I3C1_I3C_SCL_DI", "Input clock"},
+        [1860] = {118, 2, "DEV_MCU_I3C1_I3C_SCLK_CLK", "Input clock"},
+        [1861] = {118, 3, "DEV_MCU_I3C1_I3C_SCL_DO_0", "Output clock"},
+        [1862] = {172, 0, "DEV_MCU_MCAN0_MCANSS_HCLK_CLK", "Input clock"},
+        [1863] = {172, 1, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1864] = {172, 2, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+        [1865] = {172, 3, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+        [1866] = {172, 4, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+        [1867] = {172, 5, "DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK"},
+        [1868] = {173, 0, "DEV_MCU_MCAN1_MCANSS_HCLK_CLK", "Input clock"},
+        [1869] = {173, 1, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK", "Input muxed clock"},
+        [1870] = {173, 2, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+        [1871] = {173, 3, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+        [1872] = {173, 4, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+        [1873] = {173, 5, "DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK"},
+        [1874] = {274, 0, "DEV_MCU_MCSPI0_VBUSP_CLK", "Input clock"},
+        [1875] = {274, 1, "DEV_MCU_MCSPI0_CLKSPIREF_CLK", "Input clock"},
+        [1876] = {274, 2, "DEV_MCU_MCSPI0_IO_CLKSPIO_CLK", "Output clock"},
+        [1877] = {275, 0, "DEV_MCU_MCSPI1_VBUSP_CLK", "Input clock"},
+        [1878] = {275, 1, "DEV_MCU_MCSPI1_CLKSPIREF_CLK", "Input clock"},
+        [1879] = {275, 2, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK", "Input muxed clock"},
+        [1880] = {275, 3, "DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK", "Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK"},
+        [1881] = {275, 4, "DEV_MCU_MCSPI1_IO_CLKSPIO_CLK", "Output clock"},
+        [1882] = {276, 0, "DEV_MCU_MCSPI2_VBUSP_CLK", "Input clock"},
+        [1883] = {276, 1, "DEV_MCU_MCSPI2_CLKSPIREF_CLK", "Input clock"},
+        [1884] = {276, 2, "DEV_MCU_MCSPI2_IO_CLKSPII_CLK", "Input clock"},
+        [1885] = {276, 3, "DEV_MCU_MCSPI2_IO_CLKSPIO_CLK", "Output clock"},
+        [1886] = {233, 0, "DEV_MCU_NAVSS0_INTAGGR_0_SYS_CLK", "Input clock"},
+        [1887] = {237, 0, "DEV_MCU_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"},
+        [1888] = {238, 0, "DEV_MCU_NAVSS0_MCRC_0_CLK", "Input clock"},
+        [1889] = {302, 0, "DEV_MCU_NAVSS0_MODSS_VD2CLK", "Input clock"},
+        [1890] = {234, 0, "DEV_MCU_NAVSS0_PROXY_0_CLK_CLK", "Input clock"},
+        [1891] = {235, 0, "DEV_MCU_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"},
+        [1892] = {236, 0, "DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
+        [1893] = {303, 0, "DEV_MCU_NAVSS0_UDMASS_VD2CLK", "Input clock"},
+        [1894] = {250, 0, "DEV_MCU_R5FSS0_CORE0_CPU_CLK", "Input muxed clock"},
+        [1895] = {250, 1, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
+        [1896] = {250, 2, "DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK"},
+        [1897] = {250, 3, "DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
+        [1898] = {251, 0, "DEV_MCU_R5FSS0_CORE1_CPU_CLK", "Input muxed clock"},
+        [1899] = {251, 1, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
+        [1900] = {251, 2, "DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK"},
+        [1901] = {251, 3, "DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
+        [1902] = {262, 0, "DEV_MCU_RTI0_VBUSP_CLK", "Input clock"},
+        [1903] = {262, 1, "DEV_MCU_RTI0_RTI_CLK", "Input muxed clock"},
+        [1904] = {262, 2, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+        [1905] = {262, 3, "DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+        [1906] = {262, 4, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+        [1907] = {262, 5, "DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI0_RTI_CLK"},
+        [1908] = {263, 0, "DEV_MCU_RTI1_VBUSP_CLK", "Input clock"},
+        [1909] = {263, 1, "DEV_MCU_RTI1_RTI_CLK", "Input muxed clock"},
+        [1910] = {263, 2, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+        [1911] = {263, 3, "DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+        [1912] = {263, 4, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+        [1913] = {263, 5, "DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_RTI1_RTI_CLK"},
+        [1914] = {265, 0, "DEV_MCU_SA2_UL0_X2_CLK", "Input clock"},
+        [1915] = {265, 1, "DEV_MCU_SA2_UL0_PKA_IN_CLK", "Input clock"},
+        [1916] = {265, 2, "DEV_MCU_SA2_UL0_X1_CLK", "Input clock"},
+        [1917] = {35, 0, "DEV_MCU_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+        [1918] = {35, 1, "DEV_MCU_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1919] = {35, 2, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1920] = {35, 3, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1921] = {35, 4, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1922] = {35, 5, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1923] = {35, 6, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1924] = {35, 7, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1925] = {35, 8, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1926] = {35, 9, "DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK"},
+        [1927] = {35, 10, "DEV_MCU_TIMER0_TIMER_PWM_0", "Output clock"},
+        [1928] = {71, 0, "DEV_MCU_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+        [1929] = {71, 1, "DEV_MCU_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1930] = {71, 2, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+        [1931] = {71, 3, "DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK"},
+        [1932] = {72, 0, "DEV_MCU_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+        [1933] = {72, 1, "DEV_MCU_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1934] = {72, 2, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1935] = {72, 3, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1936] = {72, 4, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1937] = {72, 5, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1938] = {72, 6, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1939] = {72, 7, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1940] = {72, 8, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1941] = {72, 9, "DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK"},
+        [1942] = {72, 10, "DEV_MCU_TIMER2_TIMER_PWM_0", "Output clock"},
+        [1943] = {73, 0, "DEV_MCU_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+        [1944] = {73, 1, "DEV_MCU_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1945] = {73, 2, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+        [1946] = {73, 3, "DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK"},
+        [1947] = {74, 0, "DEV_MCU_TIMER4_TIMER_HCLK_CLK", "Input clock"},
+        [1948] = {74, 1, "DEV_MCU_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1949] = {74, 2, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1950] = {74, 3, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1951] = {74, 4, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1952] = {74, 5, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1953] = {74, 6, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1954] = {74, 7, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1955] = {74, 8, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1956] = {74, 9, "DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK"},
+        [1957] = {74, 10, "DEV_MCU_TIMER4_TIMER_PWM_0", "Output clock"},
+        [1958] = {75, 0, "DEV_MCU_TIMER5_TIMER_HCLK_CLK", "Input clock"},
+        [1959] = {75, 1, "DEV_MCU_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1960] = {75, 2, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
+        [1961] = {75, 3, "DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK"},
+        [1962] = {76, 0, "DEV_MCU_TIMER6_TIMER_HCLK_CLK", "Input clock"},
+        [1963] = {76, 1, "DEV_MCU_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1964] = {76, 2, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1965] = {76, 3, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1966] = {76, 4, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1967] = {76, 5, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1968] = {76, 6, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1969] = {76, 7, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1970] = {76, 8, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1971] = {76, 9, "DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK"},
+        [1972] = {76, 10, "DEV_MCU_TIMER6_TIMER_PWM_0", "Output clock"},
+        [1973] = {77, 0, "DEV_MCU_TIMER7_TIMER_HCLK_CLK", "Input clock"},
+        [1974] = {77, 1, "DEV_MCU_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1975] = {77, 2, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
+        [1976] = {77, 3, "DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK"},
+        [1977] = {78, 0, "DEV_MCU_TIMER8_TIMER_HCLK_CLK", "Input clock"},
+        [1978] = {78, 1, "DEV_MCU_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1979] = {78, 2, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1980] = {78, 3, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK5", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1981] = {78, 4, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1982] = {78, 5, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1983] = {78, 6, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1984] = {78, 7, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1985] = {78, 8, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0_0", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1986] = {78, 9, "DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK"},
+        [1987] = {78, 10, "DEV_MCU_TIMER8_TIMER_PWM_0", "Output clock"},
+        [1988] = {79, 0, "DEV_MCU_TIMER9_TIMER_HCLK_CLK", "Input clock"},
+        [1989] = {79, 1, "DEV_MCU_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
+        [1990] = {79, 2, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
+        [1991] = {79, 3, "DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM_0", "Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK"},
+        [1992] = {149, 0, "DEV_MCU_UART0_FCLK_CLK", "Input muxed clock"},
+        [1993] = {149, 1, "DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
+        [1994] = {149, 2, "DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK", "Parent input clock option to DEV_MCU_UART0_FCLK_CLK"},
+        [1995] = {149, 3, "DEV_MCU_UART0_VBUSP_CLK", "Input clock"},
+        [1996] = {186, 0, "DEV_MLB0_MLBSS_MLB_CLK", "Input clock"},
+        [1997] = {186, 1, "DEV_MLB0_MLBSS_SCLK_CLK", "Input clock"},
+        [1998] = {186, 2, "DEV_MLB0_MLBSS_HCLK_CLK", "Input clock"},
+        [1999] = {186, 3, "DEV_MLB0_MLBSS_PCLK_CLK", "Input clock"},
+        [2000] = {186, 4, "DEV_MLB0_MLBSS_AMLB_CLK", "Input clock"},
+        [2001] = {91, 0, "DEV_MMCSD0_EMMCSS_VBUS_CLK", "Input clock"},
+        [2002] = {91, 1, "DEV_MMCSD0_EMMCSS_XIN_CLK", "Input muxed clock"},
+        [2003] = {91, 2, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+        [2004] = {91, 3, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+        [2005] = {91, 4, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+        [2006] = {91, 5, "DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK"},
+        [2007] = {91, 6, "DEV_MMCSD0_EMMCSS_IO_CLK_0", "Output clock"},
+        [2008] = {92, 0, "DEV_MMCSD1_EMMCSDSS_XIN_CLK", "Input muxed clock"},
+        [2009] = {92, 1, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+        [2010] = {92, 2, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+        [2011] = {92, 3, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+        [2012] = {92, 4, "DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK"},
+        [2013] = {92, 5, "DEV_MMCSD1_EMMCSDSS_VBUS_CLK", "Input clock"},
+        [2014] = {92, 6, "DEV_MMCSD1_EMMCSDSS_IO_CLK_I_0", "Input clock"},
+        [2015] = {92, 7, "DEV_MMCSD1_EMMCSDSS_IO_CLK_O_0", "Output clock"},
+        [2016] = {93, 0, "DEV_MMCSD2_EMMCSDSS_XIN_CLK", "Input muxed clock"},
+        [2017] = {93, 1, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
+        [2018] = {93, 2, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
+        [2019] = {93, 3, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
+        [2020] = {93, 4, "DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK", "Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK"},
+        [2021] = {93, 5, "DEV_MMCSD2_EMMCSDSS_VBUS_CLK", "Input clock"},
+        [2022] = {93, 6, "DEV_MMCSD2_EMMCSDSS_IO_CLK_I_0", "Input clock"},
+        [2023] = {93, 7, "DEV_MMCSD2_EMMCSDSS_IO_CLK_O_0", "Output clock"},
+        [2024] = {201, 0, "DEV_NAVSS0_CPTS_0_VBUSP_GCLK", "Input clock"},
+        [2025] = {201, 1, "DEV_NAVSS0_CPTS_0_RCLK", "Input muxed clock"},
+        [2026] = {201, 2, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2027] = {201, 3, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2028] = {201, 4, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2029] = {201, 5, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2030] = {201, 6, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2031] = {201, 7, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2032] = {201, 8, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2033] = {201, 9, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2034] = {201, 10, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2035] = {201, 11, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2036] = {201, 12, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2037] = {201, 13, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2038] = {201, 14, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2039] = {201, 15, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2040] = {201, 16, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2041] = {201, 17, "DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_NAVSS0_CPTS_0_RCLK"},
+        [2042] = {201, 18, "DEV_NAVSS0_CPTS_0_TS_GENF0", "Output clock"},
+        [2043] = {201, 19, "DEV_NAVSS0_CPTS_0_TS_GENF1", "Output clock"},
+        [2044] = {206, 0, "DEV_NAVSS0_DTI_0_CLK_CLK", "Input clock"},
+        [2045] = {206, 1, "DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK", "Input clock"},
+        [2046] = {206, 2, "DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK", "Input clock"},
+        [2047] = {206, 3, "DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK", "Input clock"},
+        [2048] = {206, 4, "DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK", "Input clock"},
+        [2049] = {213, 0, "DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK", "Input clock"},
+        [2050] = {214, 0, "DEV_NAVSS0_MAILBOX_0_VCLK_CLK", "Input clock"},
+        [2051] = {215, 0, "DEV_NAVSS0_MAILBOX_1_VCLK_CLK", "Input clock"},
+        [2052] = {224, 0, "DEV_NAVSS0_MAILBOX_10_VCLK_CLK", "Input clock"},
+        [2053] = {225, 0, "DEV_NAVSS0_MAILBOX_11_VCLK_CLK", "Input clock"},
+        [2054] = {216, 0, "DEV_NAVSS0_MAILBOX_2_VCLK_CLK", "Input clock"},
+        [2055] = {217, 0, "DEV_NAVSS0_MAILBOX_3_VCLK_CLK", "Input clock"},
+        [2056] = {218, 0, "DEV_NAVSS0_MAILBOX_4_VCLK_CLK", "Input clock"},
+        [2057] = {219, 0, "DEV_NAVSS0_MAILBOX_5_VCLK_CLK", "Input clock"},
+        [2058] = {220, 0, "DEV_NAVSS0_MAILBOX_6_VCLK_CLK", "Input clock"},
+        [2059] = {221, 0, "DEV_NAVSS0_MAILBOX_7_VCLK_CLK", "Input clock"},
+        [2060] = {222, 0, "DEV_NAVSS0_MAILBOX_8_VCLK_CLK", "Input clock"},
+        [2061] = {223, 0, "DEV_NAVSS0_MAILBOX_9_VCLK_CLK", "Input clock"},
+        [2062] = {227, 0, "DEV_NAVSS0_MCRC_0_CLK", "Input clock"},
+        [2063] = {299, 0, "DEV_NAVSS0_MODSS_VD2CLK", "Input clock"},
+        [2064] = {207, 0, "DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK", "Input clock"},
+        [2065] = {208, 0, "DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK", "Input clock"},
+        [2066] = {210, 0, "DEV_NAVSS0_PROXY_0_CLK_CLK", "Input clock"},
+        [2067] = {211, 0, "DEV_NAVSS0_RINGACC_0_SYS_CLK", "Input clock"},
+        [2068] = {226, 0, "DEV_NAVSS0_SPINLOCK_0_CLK", "Input clock"},
+        [2069] = {228, 0, "DEV_NAVSS0_TBU_0_CLK_CLK", "Input clock"},
+        [2070] = {229, 0, "DEV_NAVSS0_TCU_0_CLK_CLK", "Input clock"},
+        [2071] = {230, 0, "DEV_NAVSS0_TIMERMGR_0_VCLK_CLK", "Input clock"},
+        [2072] = {230, 1, "DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT", "Input clock"},
+        [2073] = {231, 0, "DEV_NAVSS0_TIMERMGR_1_VCLK_CLK", "Input clock"},
+        [2074] = {231, 1, "DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT", "Input clock"},
+        [2075] = {212, 0, "DEV_NAVSS0_UDMAP_0_SYS_CLK", "Input clock"},
+        [2076] = {300, 0, "DEV_NAVSS0_UDMASS_VD2CLK", "Input clock"},
+        [2077] = {209, 0, "DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK", "Input clock"},
+        [2078] = {301, 0, "DEV_NAVSS0_VIRTSS_VD2CLK", "Input clock"},
+        [2079] = {199, 0, "DEV_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Output clock"},
+        [2080] = {199, 1, "DEV_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Output clock"},
+        [2081] = {239, 0, "DEV_PCIE0_PCIE_LANE1_TXMCLK", "Input clock"},
+        [2082] = {239, 1, "DEV_PCIE0_PCIE_CBA_CLK", "Input clock"},
+        [2083] = {239, 2, "DEV_PCIE0_PCIE_LANE1_RXCLK", "Input clock"},
+        [2084] = {239, 3, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
+        [2085] = {239, 4, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2086] = {239, 5, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2087] = {239, 6, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2088] = {239, 7, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2089] = {239, 8, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2090] = {239, 9, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2091] = {239, 10, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2092] = {239, 11, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2093] = {239, 12, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2094] = {239, 13, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2095] = {239, 14, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2096] = {239, 15, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2097] = {239, 16, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2098] = {239, 17, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2099] = {239, 18, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2100] = {239, 19, "DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK"},
+        [2101] = {239, 20, "DEV_PCIE0_PCIE_LANE1_TXFCLK", "Input clock"},
+        [2102] = {239, 21, "DEV_PCIE0_PCIE_LANE1_REFCLK", "Input clock"},
+        [2103] = {239, 22, "DEV_PCIE0_PCIE_LANE0_REFCLK", "Input clock"},
+        [2104] = {239, 23, "DEV_PCIE0_PCIE_LANE0_TXMCLK", "Input clock"},
+        [2105] = {239, 24, "DEV_PCIE0_PCIE_LANE0_TXFCLK", "Input clock"},
+        [2106] = {239, 25, "DEV_PCIE0_PCIE_PM_CLK", "Input clock"},
+        [2107] = {239, 26, "DEV_PCIE0_PCIE_LANE0_RXFCLK", "Input clock"},
+        [2108] = {239, 27, "DEV_PCIE0_PCIE_LANE1_RXFCLK", "Input clock"},
+        [2109] = {239, 28, "DEV_PCIE0_PCIE_LANE0_RXCLK", "Input clock"},
+        [2110] = {239, 29, "DEV_PCIE0_PCIE_LANE1_TXCLK", "Output clock"},
+        [2111] = {239, 30, "DEV_PCIE0_PCIE_LANE0_TXCLK", "Output clock"},
+        [2112] = {240, 0, "DEV_PCIE1_PCIE_LANE1_TXMCLK", "Input clock"},
+        [2113] = {240, 1, "DEV_PCIE1_PCIE_CBA_CLK", "Input clock"},
+        [2114] = {240, 2, "DEV_PCIE1_PCIE_LANE1_RXCLK", "Input clock"},
+        [2115] = {240, 3, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
+        [2116] = {240, 4, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2117] = {240, 5, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2118] = {240, 6, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2119] = {240, 7, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2120] = {240, 8, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2121] = {240, 9, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2122] = {240, 10, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2123] = {240, 11, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2124] = {240, 12, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2125] = {240, 13, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2126] = {240, 14, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2127] = {240, 15, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2128] = {240, 16, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2129] = {240, 17, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2130] = {240, 18, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2131] = {240, 19, "DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK"},
+        [2132] = {240, 20, "DEV_PCIE1_PCIE_LANE1_TXFCLK", "Input clock"},
+        [2133] = {240, 21, "DEV_PCIE1_PCIE_LANE1_REFCLK", "Input clock"},
+        [2134] = {240, 22, "DEV_PCIE1_PCIE_LANE0_REFCLK", "Input clock"},
+        [2135] = {240, 23, "DEV_PCIE1_PCIE_LANE0_TXMCLK", "Input clock"},
+        [2136] = {240, 24, "DEV_PCIE1_PCIE_LANE0_TXFCLK", "Input clock"},
+        [2137] = {240, 25, "DEV_PCIE1_PCIE_PM_CLK", "Input clock"},
+        [2138] = {240, 26, "DEV_PCIE1_PCIE_LANE0_RXFCLK", "Input clock"},
+        [2139] = {240, 27, "DEV_PCIE1_PCIE_LANE1_RXFCLK", "Input clock"},
+        [2140] = {240, 28, "DEV_PCIE1_PCIE_LANE0_RXCLK", "Input clock"},
+        [2141] = {240, 29, "DEV_PCIE1_PCIE_LANE1_TXCLK", "Output clock"},
+        [2142] = {240, 30, "DEV_PCIE1_PCIE_LANE0_TXCLK", "Output clock"},
+        [2143] = {241, 0, "DEV_PCIE2_PCIE_LANE1_TXMCLK", "Input clock"},
+        [2144] = {241, 1, "DEV_PCIE2_PCIE_CBA_CLK", "Input clock"},
+        [2145] = {241, 2, "DEV_PCIE2_PCIE_LANE1_RXCLK", "Input clock"},
+        [2146] = {241, 3, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
+        [2147] = {241, 4, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2148] = {241, 5, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2149] = {241, 6, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2150] = {241, 7, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2151] = {241, 8, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2152] = {241, 9, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2153] = {241, 10, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2154] = {241, 11, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2155] = {241, 12, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2156] = {241, 13, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2157] = {241, 14, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2158] = {241, 15, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2159] = {241, 16, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2160] = {241, 17, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2161] = {241, 18, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2162] = {241, 19, "DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK"},
+        [2163] = {241, 20, "DEV_PCIE2_PCIE_LANE1_TXFCLK", "Input clock"},
+        [2164] = {241, 21, "DEV_PCIE2_PCIE_LANE1_REFCLK", "Input clock"},
+        [2165] = {241, 22, "DEV_PCIE2_PCIE_LANE0_REFCLK", "Input clock"},
+        [2166] = {241, 23, "DEV_PCIE2_PCIE_LANE0_TXMCLK", "Input clock"},
+        [2167] = {241, 24, "DEV_PCIE2_PCIE_LANE0_TXFCLK", "Input clock"},
+        [2168] = {241, 25, "DEV_PCIE2_PCIE_PM_CLK", "Input clock"},
+        [2169] = {241, 26, "DEV_PCIE2_PCIE_LANE0_RXFCLK", "Input clock"},
+        [2170] = {241, 27, "DEV_PCIE2_PCIE_LANE1_RXFCLK", "Input clock"},
+        [2171] = {241, 28, "DEV_PCIE2_PCIE_LANE0_RXCLK", "Input clock"},
+        [2172] = {241, 29, "DEV_PCIE2_PCIE_LANE1_TXCLK", "Output clock"},
+        [2173] = {241, 30, "DEV_PCIE2_PCIE_LANE0_TXCLK", "Output clock"},
+        [2174] = {242, 0, "DEV_PCIE3_PCIE_LANE1_TXMCLK", "Input clock"},
+        [2175] = {242, 1, "DEV_PCIE3_PCIE_CBA_CLK", "Input clock"},
+        [2176] = {242, 2, "DEV_PCIE3_PCIE_LANE1_RXCLK", "Input clock"},
+        [2177] = {242, 3, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK", "Input muxed clock"},
+        [2178] = {242, 4, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2179] = {242, 5, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2180] = {242, 6, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2181] = {242, 7, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2182] = {242, 8, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2183] = {242, 9, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2184] = {242, 10, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2185] = {242, 11, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2186] = {242, 12, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2187] = {242, 13, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2188] = {242, 14, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2189] = {242, 15, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2190] = {242, 16, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2191] = {242, 17, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2192] = {242, 18, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2193] = {242, 19, "DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK"},
+        [2194] = {242, 20, "DEV_PCIE3_PCIE_LANE1_TXFCLK", "Input clock"},
+        [2195] = {242, 21, "DEV_PCIE3_PCIE_LANE1_REFCLK", "Input clock"},
+        [2196] = {242, 22, "DEV_PCIE3_PCIE_LANE0_REFCLK", "Input clock"},
+        [2197] = {242, 23, "DEV_PCIE3_PCIE_LANE0_TXMCLK", "Input clock"},
+        [2198] = {242, 24, "DEV_PCIE3_PCIE_LANE0_TXFCLK", "Input clock"},
+        [2199] = {242, 25, "DEV_PCIE3_PCIE_PM_CLK", "Input clock"},
+        [2200] = {242, 26, "DEV_PCIE3_PCIE_LANE0_RXFCLK", "Input clock"},
+        [2201] = {242, 27, "DEV_PCIE3_PCIE_LANE1_RXFCLK", "Input clock"},
+        [2202] = {242, 28, "DEV_PCIE3_PCIE_LANE0_RXCLK", "Input clock"},
+        [2203] = {242, 29, "DEV_PCIE3_PCIE_LANE1_TXCLK", "Output clock"},
+        [2204] = {242, 30, "DEV_PCIE3_PCIE_LANE0_TXCLK", "Output clock"},
+        [2205] = {119, 0, "DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I_0", "Input clock"},
+        [2206] = {119, 1, "DEV_PRU_ICSSG0_VCLK_CLK", "Input clock"},
+        [2207] = {119, 2, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I_0", "Input clock"},
+        [2208] = {119, 3, "DEV_PRU_ICSSG0_IEP_CLK", "Input muxed clock"},
+        [2209] = {119, 4, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2210] = {119, 5, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2211] = {119, 6, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2212] = {119, 7, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2213] = {119, 8, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2214] = {119, 9, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2215] = {119, 10, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2216] = {119, 11, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2217] = {119, 12, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2218] = {119, 13, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2219] = {119, 14, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2220] = {119, 15, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2221] = {119, 16, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2222] = {119, 17, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2223] = {119, 18, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2224] = {119, 19, "DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK"},
+        [2225] = {119, 20, "DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK", "Input clock"},
+        [2226] = {119, 21, "DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I_0", "Input clock"},
+        [2227] = {119, 22, "DEV_PRU_ICSSG0_UCLK_CLK", "Input clock"},
+        [2228] = {119, 23, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I_0", "Input clock"},
+        [2229] = {119, 24, "DEV_PRU_ICSSG0_CORE_CLK", "Input muxed clock"},
+        [2230] = {119, 25, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
+        [2231] = {119, 26, "DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK"},
+        [2232] = {119, 27, "DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK", "Input clock"},
+        [2233] = {119, 28, "DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK", "Input clock"},
+        [2234] = {119, 29, "DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O_0", "Output clock"},
+        [2235] = {119, 30, "DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O_0", "Output clock"},
+        [2236] = {119, 31, "DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O_0", "Output clock"},
+        [2237] = {120, 0, "DEV_PRU_ICSSG1_SERDES0_RXCLK", "Input muxed clock"},
+        [2238] = {120, 1, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
+        [2239] = {120, 2, "DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK"},
+        [2240] = {120, 3, "DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I_0", "Input clock"},
+        [2241] = {120, 4, "DEV_PRU_ICSSG1_VCLK_CLK", "Input clock"},
+        [2242] = {120, 5, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I_0", "Input clock"},
+        [2243] = {120, 6, "DEV_PRU_ICSSG1_SERDES0_RXFCLK", "Input muxed clock"},
+        [2244] = {120, 7, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
+        [2245] = {120, 8, "DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK"},
+        [2246] = {120, 9, "DEV_PRU_ICSSG1_IEP_CLK", "Input muxed clock"},
+        [2247] = {120, 10, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2248] = {120, 11, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2249] = {120, 12, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2250] = {120, 13, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2251] = {120, 14, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2252] = {120, 15, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2253] = {120, 16, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2254] = {120, 17, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2255] = {120, 18, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2256] = {120, 19, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2257] = {120, 20, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2258] = {120, 21, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2259] = {120, 22, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2260] = {120, 23, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2261] = {120, 24, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2262] = {120, 25, "DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK", "Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK"},
+        [2263] = {120, 26, "DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK", "Input clock"},
+        [2264] = {120, 27, "DEV_PRU_ICSSG1_SERDES0_TXMCLK", "Input muxed clock"},
+        [2265] = {120, 28, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
+        [2266] = {120, 29, "DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK"},
+        [2267] = {120, 30, "DEV_PRU_ICSSG1_SERDES0_REFCLK", "Input muxed clock"},
+        [2268] = {120, 31, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
+        [2269] = {120, 32, "DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK"},
+        [2270] = {120, 33, "DEV_PRU_ICSSG1_SERDES1_RXFCLK", "Input muxed clock"},
+        [2271] = {120, 34, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
+        [2272] = {120, 35, "DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK"},
+        [2273] = {120, 36, "DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I_0", "Input clock"},
+        [2274] = {120, 37, "DEV_PRU_ICSSG1_SERDES1_RXCLK", "Input muxed clock"},
+        [2275] = {120, 38, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
+        [2276] = {120, 39, "DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK"},
+        [2277] = {120, 40, "DEV_PRU_ICSSG1_SERDES1_TXFCLK", "Input muxed clock"},
+        [2278] = {120, 41, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
+        [2279] = {120, 42, "DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK"},
+        [2280] = {120, 43, "DEV_PRU_ICSSG1_SERDES1_TXMCLK", "Input muxed clock"},
+        [2281] = {120, 44, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
+        [2282] = {120, 45, "DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK"},
+        [2283] = {120, 46, "DEV_PRU_ICSSG1_SERDES0_TXFCLK", "Input muxed clock"},
+        [2284] = {120, 47, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
+        [2285] = {120, 48, "DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK"},
+        [2286] = {120, 49, "DEV_PRU_ICSSG1_UCLK_CLK", "Input clock"},
+        [2287] = {120, 50, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I_0", "Input clock"},
+        [2288] = {120, 51, "DEV_PRU_ICSSG1_SERDES1_REFCLK", "Input muxed clock"},
+        [2289] = {120, 52, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
+        [2290] = {120, 53, "DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK", "Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK"},
+        [2291] = {120, 54, "DEV_PRU_ICSSG1_CORE_CLK", "Input muxed clock"},
+        [2292] = {120, 55, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
+        [2293] = {120, 56, "DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK", "Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK"},
+        [2294] = {120, 57, "DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK", "Input clock"},
+        [2295] = {120, 58, "DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK", "Input clock"},
+        [2296] = {120, 59, "DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O_0", "Output clock"},
+        [2297] = {120, 60, "DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O_0", "Output clock"},
+        [2298] = {120, 61, "DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O_0", "Output clock"},
+        [2299] = {120, 62, "DEV_PRU_ICSSG1_SERDES0_TXCLK", "Output clock"},
+        [2300] = {120, 63, "DEV_PRU_ICSSG1_SERDES1_TXCLK", "Output clock"},
+        [2301] = {133, 0, "DEV_PSC0_SLOW_CLK", "Input clock"},
+        [2302] = {133, 1, "DEV_PSC0_CLK", "Input clock"},
+        [2303] = {243, 0, "DEV_PULSAR_SL_MAIN_0_INTERFACE0_PHASE_0", "Input clock"},
+        [2304] = {243, 1, "DEV_PULSAR_SL_MAIN_0_INTERFACE1_PHASE_0", "Input clock"},
+        [2305] = {244, 0, "DEV_PULSAR_SL_MAIN_1_INTERFACE0_PHASE_0", "Input clock"},
+        [2306] = {244, 1, "DEV_PULSAR_SL_MAIN_1_INTERFACE1_PHASE_0", "Input clock"},
+        [2307] = {249, 0, "DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0", "Input muxed clock"},
+        [2308] = {249, 1, "DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE0_PHASE_0"},
+        [2309] = {249, 2, "DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0", "Input muxed clock"},
+        [2310] = {249, 3, "DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2", "Parent input clock option to DEV_PULSAR_SL_MCU_0_INTERFACE1_PHASE_0"},
+        [2311] = {245, 0, "DEV_R5FSS0_CORE0_CPU_CLK", "Input clock"},
+        [2312] = {245, 1, "DEV_R5FSS0_CORE0_INTERFACE_CLK", "Input clock"},
+        [2313] = {246, 0, "DEV_R5FSS0_CORE1_CPU_CLK", "Input clock"},
+        [2314] = {246, 1, "DEV_R5FSS0_CORE1_INTERFACE_CLK", "Input clock"},
+        [2315] = {134, 0, "DEV_R5FSS0_INTROUTER0_INTR_CLK", "Input clock"},
+        [2316] = {247, 0, "DEV_R5FSS1_CORE0_CPU_CLK", "Input clock"},
+        [2317] = {247, 1, "DEV_R5FSS1_CORE0_INTERFACE_CLK", "Input clock"},
+        [2318] = {248, 0, "DEV_R5FSS1_CORE1_CPU_CLK", "Input clock"},
+        [2319] = {248, 1, "DEV_R5FSS1_CORE1_INTERFACE_CLK", "Input clock"},
+        [2320] = {135, 0, "DEV_R5FSS1_INTROUTER0_INTR_CLK", "Input clock"},
+        [2321] = {252, 0, "DEV_RTI0_VBUSP_CLK", "Input clock"},
+        [2322] = {252, 1, "DEV_RTI0_RTI_CLK", "Input muxed clock"},
+        [2323] = {252, 2, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2324] = {252, 3, "DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2325] = {252, 4, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2326] = {252, 5, "DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2327] = {252, 6, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2328] = {252, 7, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2329] = {252, 8, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2330] = {252, 9, "DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI0_RTI_CLK"},
+        [2331] = {253, 0, "DEV_RTI1_VBUSP_CLK", "Input clock"},
+        [2332] = {253, 1, "DEV_RTI1_RTI_CLK", "Input muxed clock"},
+        [2333] = {253, 2, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2334] = {253, 3, "DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2335] = {253, 4, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2336] = {253, 5, "DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2337] = {253, 6, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2338] = {253, 7, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2339] = {253, 8, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2340] = {253, 9, "DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI1_RTI_CLK"},
+        [2341] = {257, 0, "DEV_RTI15_VBUSP_CLK", "Input clock"},
+        [2342] = {257, 1, "DEV_RTI15_RTI_CLK", "Input muxed clock"},
+        [2343] = {257, 2, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2344] = {257, 3, "DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2345] = {257, 4, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2346] = {257, 5, "DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2347] = {257, 6, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2348] = {257, 7, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2349] = {257, 8, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2350] = {257, 9, "DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI15_RTI_CLK"},
+        [2351] = {256, 0, "DEV_RTI16_VBUSP_CLK", "Input clock"},
+        [2352] = {256, 1, "DEV_RTI16_RTI_CLK", "Input muxed clock"},
+        [2353] = {256, 2, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2354] = {256, 3, "DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2355] = {256, 4, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2356] = {256, 5, "DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2357] = {256, 6, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2358] = {256, 7, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2359] = {256, 8, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2360] = {256, 9, "DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI16_RTI_CLK"},
+        [2361] = {254, 0, "DEV_RTI24_VBUSP_CLK", "Input clock"},
+        [2362] = {254, 1, "DEV_RTI24_RTI_CLK", "Input muxed clock"},
+        [2363] = {254, 2, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2364] = {254, 3, "DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2365] = {254, 4, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2366] = {254, 5, "DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2367] = {254, 6, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2368] = {254, 7, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2369] = {254, 8, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2370] = {254, 9, "DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI24_RTI_CLK"},
+        [2371] = {255, 0, "DEV_RTI25_VBUSP_CLK", "Input clock"},
+        [2372] = {255, 1, "DEV_RTI25_RTI_CLK", "Input muxed clock"},
+        [2373] = {255, 2, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2374] = {255, 3, "DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2375] = {255, 4, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2376] = {255, 5, "DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2377] = {255, 6, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2378] = {255, 7, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2379] = {255, 8, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2380] = {255, 9, "DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI25_RTI_CLK"},
+        [2381] = {258, 0, "DEV_RTI28_VBUSP_CLK", "Input clock"},
+        [2382] = {258, 1, "DEV_RTI28_RTI_CLK", "Input muxed clock"},
+        [2383] = {258, 2, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2384] = {258, 3, "DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2385] = {258, 4, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2386] = {258, 5, "DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2387] = {258, 6, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2388] = {258, 7, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2389] = {258, 8, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2390] = {258, 9, "DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI28_RTI_CLK"},
+        [2391] = {259, 0, "DEV_RTI29_VBUSP_CLK", "Input clock"},
+        [2392] = {259, 1, "DEV_RTI29_RTI_CLK", "Input muxed clock"},
+        [2393] = {259, 2, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2394] = {259, 3, "DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2395] = {259, 4, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2396] = {259, 5, "DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2397] = {259, 6, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2398] = {259, 7, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2399] = {259, 8, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2400] = {259, 9, "DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI29_RTI_CLK"},
+        [2401] = {260, 0, "DEV_RTI30_VBUSP_CLK", "Input clock"},
+        [2402] = {260, 1, "DEV_RTI30_RTI_CLK", "Input muxed clock"},
+        [2403] = {260, 2, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2404] = {260, 3, "DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2405] = {260, 4, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2406] = {260, 5, "DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2407] = {260, 6, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2408] = {260, 7, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2409] = {260, 8, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2410] = {260, 9, "DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI30_RTI_CLK"},
+        [2411] = {261, 0, "DEV_RTI31_VBUSP_CLK", "Input clock"},
+        [2412] = {261, 1, "DEV_RTI31_RTI_CLK", "Input muxed clock"},
+        [2413] = {261, 2, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2414] = {261, 3, "DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2415] = {261, 4, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2416] = {261, 5, "DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2417] = {261, 6, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2418] = {261, 7, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2419] = {261, 8, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2420] = {261, 9, "DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2", "Parent input clock option to DEV_RTI31_RTI_CLK"},
+        [2421] = {264, 0, "DEV_SA2_UL0_X2_CLK", "Input clock"},
+        [2422] = {264, 1, "DEV_SA2_UL0_PKA_IN_CLK", "Input clock"},
+        [2423] = {264, 2, "DEV_SA2_UL0_X1_CLK", "Input clock"},
+        [2424] = {297, 0, "DEV_SERDES_10G0_IP1_LN3_TXCLK", "Input clock"},
+        [2425] = {297, 1, "DEV_SERDES_10G0_CLK", "Input clock"},
+        [2426] = {297, 2, "DEV_SERDES_10G0_IP3_LN2_TXCLK", "Input clock"},
+        [2427] = {297, 3, "DEV_SERDES_10G0_IP1_LN2_TXCLK", "Input clock"},
+        [2428] = {297, 4, "DEV_SERDES_10G0_IP1_LN0_TXCLK", "Input clock"},
+        [2429] = {297, 5, "DEV_SERDES_10G0_IP3_LN1_TXCLK", "Input clock"},
+        [2430] = {297, 6, "DEV_SERDES_10G0_IP3_LN3_TXCLK", "Input clock"},
+        [2431] = {297, 7, "DEV_SERDES_10G0_IP3_LN0_TXCLK", "Input clock"},
+        [2432] = {297, 8, "DEV_SERDES_10G0_IP1_LN1_TXCLK", "Input clock"},
+        [2433] = {297, 9, "DEV_SERDES_10G0_CORE_REF_CLK", "Input muxed clock"},
+        [2434] = {297, 10, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+        [2435] = {297, 11, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+        [2436] = {297, 12, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+        [2437] = {297, 13, "DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK"},
+        [2438] = {297, 14, "DEV_SERDES_10G0_IP1_LN1_REFCLK", "Output clock"},
+        [2439] = {297, 15, "DEV_SERDES_10G0_IP1_LN2_RXCLK", "Output clock"},
+        [2440] = {297, 16, "DEV_SERDES_10G0_IP3_LN1_TXFCLK", "Output clock"},
+        [2441] = {297, 17, "DEV_SERDES_10G0_IP1_LN0_RXFCLK", "Output clock"},
+        [2442] = {297, 18, "DEV_SERDES_10G0_IP1_LN3_RXCLK", "Output clock"},
+        [2443] = {297, 19, "DEV_SERDES_10G0_IP3_LN3_RXCLK", "Output clock"},
+        [2444] = {297, 20, "DEV_SERDES_10G0_IP3_LN1_TXMCLK", "Output clock"},
+        [2445] = {297, 21, "DEV_SERDES_10G0_IP3_LN3_RXFCLK", "Output clock"},
+        [2446] = {297, 22, "DEV_SERDES_10G0_IP3_LN3_REFCLK", "Output clock"},
+        [2447] = {297, 23, "DEV_SERDES_10G0_IP3_LN2_RXCLK", "Output clock"},
+        [2448] = {297, 24, "DEV_SERDES_10G0_IP1_LN0_TXFCLK", "Output clock"},
+        [2449] = {297, 25, "DEV_SERDES_10G0_IP3_LN3_TXMCLK", "Output clock"},
+        [2450] = {297, 26, "DEV_SERDES_10G0_IP3_LN1_RXFCLK", "Output clock"},
+        [2451] = {297, 27, "DEV_SERDES_10G0_IP3_LN0_RXFCLK", "Output clock"},
+        [2452] = {297, 28, "DEV_SERDES_10G0_IP1_LN1_TXMCLK", "Output clock"},
+        [2453] = {297, 29, "DEV_SERDES_10G0_IP1_LN1_RXFCLK", "Output clock"},
+        [2454] = {297, 30, "DEV_SERDES_10G0_IP3_LN3_TXFCLK", "Output clock"},
+        [2455] = {297, 31, "DEV_SERDES_10G0_IP1_LN3_TXFCLK", "Output clock"},
+        [2456] = {297, 32, "DEV_SERDES_10G0_IP1_LN3_TXMCLK", "Output clock"},
+        [2457] = {297, 33, "DEV_SERDES_10G0_IP3_LN1_REFCLK", "Output clock"},
+        [2458] = {297, 34, "DEV_SERDES_10G0_IP3_LN0_REFCLK", "Output clock"},
+        [2459] = {297, 35, "DEV_SERDES_10G0_IP1_LN3_REFCLK", "Output clock"},
+        [2460] = {297, 36, "DEV_SERDES_10G0_IP3_LN0_RXCLK", "Output clock"},
+        [2461] = {297, 37, "DEV_SERDES_10G0_IP3_LN2_REFCLK", "Output clock"},
+        [2462] = {297, 38, "DEV_SERDES_10G0_IP1_LN0_RXCLK", "Output clock"},
+        [2463] = {297, 39, "DEV_SERDES_10G0_IP1_LN0_REFCLK", "Output clock"},
+        [2464] = {297, 40, "DEV_SERDES_10G0_IP1_LN2_RXFCLK", "Output clock"},
+        [2465] = {297, 41, "DEV_SERDES_10G0_IP1_LN1_TXFCLK", "Output clock"},
+        [2466] = {297, 42, "DEV_SERDES_10G0_IP3_LN0_TXFCLK", "Output clock"},
+        [2467] = {297, 43, "DEV_SERDES_10G0_REF_OUT_CLK", "Output clock"},
+        [2468] = {297, 44, "DEV_SERDES_10G0_IP3_LN1_RXCLK", "Output clock"},
+        [2469] = {297, 45, "DEV_SERDES_10G0_IP1_LN2_TXFCLK", "Output clock"},
+        [2470] = {297, 46, "DEV_SERDES_10G0_IP1_LN0_TXMCLK", "Output clock"},
+        [2471] = {297, 47, "DEV_SERDES_10G0_IP3_LN2_RXFCLK", "Output clock"},
+        [2472] = {297, 48, "DEV_SERDES_10G0_IP1_LN2_TXMCLK", "Output clock"},
+        [2473] = {297, 49, "DEV_SERDES_10G0_IP3_LN2_TXMCLK", "Output clock"},
+        [2474] = {297, 50, "DEV_SERDES_10G0_IP1_LN2_REFCLK", "Output clock"},
+        [2475] = {297, 51, "DEV_SERDES_10G0_IP3_LN2_TXFCLK", "Output clock"},
+        [2476] = {297, 52, "DEV_SERDES_10G0_IP3_LN0_TXMCLK", "Output clock"},
+        [2477] = {297, 53, "DEV_SERDES_10G0_IP1_LN3_RXFCLK", "Output clock"},
+        [2478] = {297, 54, "DEV_SERDES_10G0_IP1_LN1_RXCLK", "Output clock"},
+        [2479] = {292, 49, "DEV_SERDES_16G0_CMN_REFCLK1_M_0", "Input clock"},
+        [2480] = {292, 0, "DEV_SERDES_16G0_CORE_REF1_CLK", "Input muxed clock"},
+        [2481] = {292, 1, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
+        [2482] = {292, 2, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
+        [2483] = {292, 3, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
+        [2484] = {292, 4, "DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK"},
+        [2485] = {292, 5, "DEV_SERDES_16G0_CLK", "Input clock"},
+        [2486] = {292, 57, "DEV_SERDES_16G0_CMN_REFCLK1_P_0", "Input clock"},
+        [2487] = {292, 6, "DEV_SERDES_16G0_IP1_LN0_TXCLK", "Input clock"},
+        [2488] = {292, 7, "DEV_SERDES_16G0_IP2_LN1_TXCLK", "Input clock"},
+        [2489] = {292, 8, "DEV_SERDES_16G0_IP3_LN1_TXCLK", "Input clock"},
+        [2490] = {292, 9, "DEV_SERDES_16G0_IP2_LN0_TXCLK", "Input clock"},
+        [2491] = {292, 10, "DEV_SERDES_16G0_IP1_LN1_TXCLK", "Input clock"},
+        [2492] = {292, 11, "DEV_SERDES_16G0_CORE_REF_CLK", "Input muxed clock"},
+        [2493] = {292, 12, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
+        [2494] = {292, 13, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
+        [2495] = {292, 14, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
+        [2496] = {292, 15, "DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK"},
+        [2497] = {292, 17, "DEV_SERDES_16G0_IP1_LN1_REFCLK", "Output clock"},
+        [2498] = {292, 27, "DEV_SERDES_16G0_IP1_LN1_RXFCLK", "Output clock"},
+        [2499] = {292, 19, "DEV_SERDES_16G0_IP3_LN1_TXFCLK", "Output clock"},
+        [2500] = {292, 20, "DEV_SERDES_16G0_IP1_LN0_RXFCLK", "Output clock"},
+        [2501] = {292, 21, "DEV_SERDES_16G0_IP2_LN1_REFCLK", "Output clock"},
+        [2502] = {292, 22, "DEV_SERDES_16G0_IP2_LN1_TXFCLK", "Output clock"},
+        [2503] = {292, 24, "DEV_SERDES_16G0_IP1_LN0_TXFCLK", "Output clock"},
+        [2504] = {292, 25, "DEV_SERDES_16G0_IP3_LN1_RXFCLK", "Output clock"},
+        [2505] = {292, 26, "DEV_SERDES_16G0_IP1_LN1_TXMCLK", "Output clock"},
+        [2506] = {292, 16, "DEV_SERDES_16G0_IP2_LN0_TXFCLK", "Output clock"},
+        [2507] = {292, 28, "DEV_SERDES_16G0_IP3_LN1_RXCLK", "Output clock"},
+        [2508] = {292, 29, "DEV_SERDES_16G0_IP3_LN1_REFCLK", "Output clock"},
+        [2509] = {292, 32, "DEV_SERDES_16G0_IP1_LN0_RXCLK", "Output clock"},
+        [2510] = {292, 30, "DEV_SERDES_16G0_IP2_LN1_RXCLK", "Output clock"},
+        [2511] = {292, 31, "DEV_SERDES_16G0_IP2_LN0_RXFCLK", "Output clock"},
+        [2512] = {292, 35, "DEV_SERDES_16G0_IP1_LN0_REFCLK", "Output clock"},
+        [2513] = {292, 33, "DEV_SERDES_16G0_REF_OUT_CLK", "Output clock"},
+        [2514] = {292, 34, "DEV_SERDES_16G0_REF1_OUT_CLK", "Output clock"},
+        [2515] = {292, 36, "DEV_SERDES_16G0_IP1_LN0_TXMCLK", "Output clock"},
+        [2516] = {292, 37, "DEV_SERDES_16G0_IP2_LN1_RXFCLK", "Output clock"},
+        [2517] = {292, 18, "DEV_SERDES_16G0_IP3_LN1_TXMCLK", "Output clock"},
+        [2518] = {292, 38, "DEV_SERDES_16G0_IP2_LN1_TXMCLK", "Output clock"},
+        [2519] = {292, 39, "DEV_SERDES_16G0_IP2_LN0_REFCLK", "Output clock"},
+        [2520] = {292, 40, "DEV_SERDES_16G0_IP2_LN0_TXMCLK", "Output clock"},
+        [2521] = {292, 41, "DEV_SERDES_16G0_IP1_LN1_TXFCLK", "Output clock"},
+        [2522] = {292, 42, "DEV_SERDES_16G0_IP2_LN0_RXCLK", "Output clock"},
+        [2523] = {292, 43, "DEV_SERDES_16G0_IP1_LN1_RXCLK", "Output clock"},
+        [2524] = {293, 60, "DEV_SERDES_16G1_CMN_REFCLK1_M_0", "Input clock"},
+        [2525] = {293, 0, "DEV_SERDES_16G1_CORE_REF1_CLK", "Input muxed clock"},
+        [2526] = {293, 1, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
+        [2527] = {293, 2, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
+        [2528] = {293, 3, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
+        [2529] = {293, 4, "DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK"},
+        [2530] = {293, 5, "DEV_SERDES_16G1_CLK", "Input clock"},
+        [2531] = {293, 67, "DEV_SERDES_16G1_CMN_REFCLK1_P_0", "Input clock"},
+        [2532] = {293, 6, "DEV_SERDES_16G1_IP1_LN0_TXCLK", "Input clock"},
+        [2533] = {293, 7, "DEV_SERDES_16G1_IP2_LN1_TXCLK", "Input clock"},
+        [2534] = {293, 8, "DEV_SERDES_16G1_IP4_LN1_TXCLK", "Input clock"},
+        [2535] = {293, 9, "DEV_SERDES_16G1_IP4_LN0_TXCLK", "Input clock"},
+        [2536] = {293, 10, "DEV_SERDES_16G1_IP3_LN1_TXCLK", "Input clock"},
+        [2537] = {293, 11, "DEV_SERDES_16G1_IP2_LN0_TXCLK", "Input clock"},
+        [2538] = {293, 12, "DEV_SERDES_16G1_IP1_LN1_TXCLK", "Input clock"},
+        [2539] = {293, 13, "DEV_SERDES_16G1_CORE_REF_CLK", "Input muxed clock"},
+        [2540] = {293, 14, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
+        [2541] = {293, 15, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
+        [2542] = {293, 16, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
+        [2543] = {293, 17, "DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK"},
+        [2544] = {293, 19, "DEV_SERDES_16G1_IP1_LN1_REFCLK", "Output clock"},
+        [2545] = {293, 20, "DEV_SERDES_16G1_IP4_LN1_RXFCLK", "Output clock"},
+        [2546] = {293, 30, "DEV_SERDES_16G1_IP1_LN1_RXFCLK", "Output clock"},
+        [2547] = {293, 22, "DEV_SERDES_16G1_IP3_LN1_TXFCLK", "Output clock"},
+        [2548] = {293, 23, "DEV_SERDES_16G1_IP1_LN0_RXFCLK", "Output clock"},
+        [2549] = {293, 24, "DEV_SERDES_16G1_IP2_LN1_REFCLK", "Output clock"},
+        [2550] = {293, 25, "DEV_SERDES_16G1_IP2_LN1_TXFCLK", "Output clock"},
+        [2551] = {293, 27, "DEV_SERDES_16G1_IP1_LN0_TXFCLK", "Output clock"},
+        [2552] = {293, 28, "DEV_SERDES_16G1_IP3_LN1_RXFCLK", "Output clock"},
+        [2553] = {293, 29, "DEV_SERDES_16G1_IP1_LN1_TXMCLK", "Output clock"},
+        [2554] = {293, 18, "DEV_SERDES_16G1_IP2_LN0_TXFCLK", "Output clock"},
+        [2555] = {293, 31, "DEV_SERDES_16G1_IP4_LN1_REFCLK", "Output clock"},
+        [2556] = {293, 35, "DEV_SERDES_16G1_IP4_LN0_REFCLK", "Output clock"},
+        [2557] = {293, 32, "DEV_SERDES_16G1_IP3_LN1_RXCLK", "Output clock"},
+        [2558] = {293, 33, "DEV_SERDES_16G1_IP4_LN1_TXMCLK", "Output clock"},
+        [2559] = {293, 34, "DEV_SERDES_16G1_IP3_LN1_REFCLK", "Output clock"},
+        [2560] = {293, 38, "DEV_SERDES_16G1_IP1_LN0_RXCLK", "Output clock"},
+        [2561] = {293, 36, "DEV_SERDES_16G1_IP2_LN1_RXCLK", "Output clock"},
+        [2562] = {293, 37, "DEV_SERDES_16G1_IP2_LN0_RXFCLK", "Output clock"},
+        [2563] = {293, 42, "DEV_SERDES_16G1_IP1_LN0_REFCLK", "Output clock"},
+        [2564] = {293, 39, "DEV_SERDES_16G1_REF_OUT_CLK", "Output clock"},
+        [2565] = {293, 40, "DEV_SERDES_16G1_REF1_OUT_CLK", "Output clock"},
+        [2566] = {293, 41, "DEV_SERDES_16G1_IP4_LN1_RXCLK", "Output clock"},
+        [2567] = {293, 43, "DEV_SERDES_16G1_IP1_LN0_TXMCLK", "Output clock"},
+        [2568] = {293, 44, "DEV_SERDES_16G1_IP4_LN0_TXFCLK", "Output clock"},
+        [2569] = {293, 45, "DEV_SERDES_16G1_IP4_LN0_RXCLK", "Output clock"},
+        [2570] = {293, 46, "DEV_SERDES_16G1_IP2_LN1_RXFCLK", "Output clock"},
+        [2571] = {293, 21, "DEV_SERDES_16G1_IP3_LN1_TXMCLK", "Output clock"},
+        [2572] = {293, 47, "DEV_SERDES_16G1_IP2_LN1_TXMCLK", "Output clock"},
+        [2573] = {293, 48, "DEV_SERDES_16G1_IP4_LN0_RXFCLK", "Output clock"},
+        [2574] = {293, 49, "DEV_SERDES_16G1_IP2_LN0_REFCLK", "Output clock"},
+        [2575] = {293, 50, "DEV_SERDES_16G1_IP2_LN0_TXMCLK", "Output clock"},
+        [2576] = {293, 51, "DEV_SERDES_16G1_IP1_LN1_TXFCLK", "Output clock"},
+        [2577] = {293, 52, "DEV_SERDES_16G1_IP2_LN0_RXCLK", "Output clock"},
+        [2578] = {293, 53, "DEV_SERDES_16G1_IP4_LN0_TXMCLK", "Output clock"},
+        [2579] = {293, 54, "DEV_SERDES_16G1_IP1_LN1_RXCLK", "Output clock"},
+        [2580] = {293, 55, "DEV_SERDES_16G1_IP4_LN1_TXFCLK", "Output clock"},
+        [2581] = {294, 51, "DEV_SERDES_16G2_CMN_REFCLK1_M_0", "Input clock"},
+        [2582] = {294, 0, "DEV_SERDES_16G2_CORE_REF1_CLK", "Input muxed clock"},
+        [2583] = {294, 1, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
+        [2584] = {294, 2, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
+        [2585] = {294, 3, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
+        [2586] = {294, 4, "DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK"},
+        [2587] = {294, 5, "DEV_SERDES_16G2_CLK", "Input clock"},
+        [2588] = {294, 61, "DEV_SERDES_16G2_CMN_REFCLK1_P_0", "Input clock"},
+        [2589] = {294, 6, "DEV_SERDES_16G2_IP2_LN1_TXCLK", "Input clock"},
+        [2590] = {294, 7, "DEV_SERDES_16G2_IP4_LN1_TXCLK", "Input clock"},
+        [2591] = {294, 8, "DEV_SERDES_16G2_IP4_LN0_TXCLK", "Input clock"},
+        [2592] = {294, 9, "DEV_SERDES_16G2_IP3_LN1_TXCLK", "Input clock"},
+        [2593] = {294, 10, "DEV_SERDES_16G2_IP2_LN0_TXCLK", "Input clock"},
+        [2594] = {294, 11, "DEV_SERDES_16G2_CORE_REF_CLK", "Input muxed clock"},
+        [2595] = {294, 12, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
+        [2596] = {294, 13, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
+        [2597] = {294, 14, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
+        [2598] = {294, 15, "DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK"},
+        [2599] = {294, 17, "DEV_SERDES_16G2_IP4_LN1_RXFCLK", "Output clock"},
+        [2600] = {294, 19, "DEV_SERDES_16G2_IP3_LN1_TXFCLK", "Output clock"},
+        [2601] = {294, 20, "DEV_SERDES_16G2_IP2_LN1_REFCLK", "Output clock"},
+        [2602] = {294, 21, "DEV_SERDES_16G2_IP2_LN1_TXFCLK", "Output clock"},
+        [2603] = {294, 23, "DEV_SERDES_16G2_IP3_LN1_RXFCLK", "Output clock"},
+        [2604] = {294, 16, "DEV_SERDES_16G2_IP2_LN0_TXFCLK", "Output clock"},
+        [2605] = {294, 24, "DEV_SERDES_16G2_IP4_LN1_REFCLK", "Output clock"},
+        [2606] = {294, 28, "DEV_SERDES_16G2_IP4_LN0_REFCLK", "Output clock"},
+        [2607] = {294, 25, "DEV_SERDES_16G2_IP3_LN1_RXCLK", "Output clock"},
+        [2608] = {294, 26, "DEV_SERDES_16G2_IP4_LN1_TXMCLK", "Output clock"},
+        [2609] = {294, 27, "DEV_SERDES_16G2_IP3_LN1_REFCLK", "Output clock"},
+        [2610] = {294, 29, "DEV_SERDES_16G2_IP2_LN1_RXCLK", "Output clock"},
+        [2611] = {294, 30, "DEV_SERDES_16G2_IP2_LN0_RXFCLK", "Output clock"},
+        [2612] = {294, 31, "DEV_SERDES_16G2_REF_OUT_CLK", "Output clock"},
+        [2613] = {294, 32, "DEV_SERDES_16G2_REF1_OUT_CLK", "Output clock"},
+        [2614] = {294, 33, "DEV_SERDES_16G2_IP4_LN1_RXCLK", "Output clock"},
+        [2615] = {294, 34, "DEV_SERDES_16G2_IP4_LN0_TXFCLK", "Output clock"},
+        [2616] = {294, 35, "DEV_SERDES_16G2_IP4_LN0_RXCLK", "Output clock"},
+        [2617] = {294, 36, "DEV_SERDES_16G2_IP2_LN1_RXFCLK", "Output clock"},
+        [2618] = {294, 18, "DEV_SERDES_16G2_IP3_LN1_TXMCLK", "Output clock"},
+        [2619] = {294, 37, "DEV_SERDES_16G2_IP2_LN1_TXMCLK", "Output clock"},
+        [2620] = {294, 38, "DEV_SERDES_16G2_IP4_LN0_RXFCLK", "Output clock"},
+        [2621] = {294, 39, "DEV_SERDES_16G2_IP2_LN0_REFCLK", "Output clock"},
+        [2622] = {294, 40, "DEV_SERDES_16G2_IP2_LN0_TXMCLK", "Output clock"},
+        [2623] = {294, 41, "DEV_SERDES_16G2_IP2_LN0_RXCLK", "Output clock"},
+        [2624] = {294, 42, "DEV_SERDES_16G2_IP4_LN0_TXMCLK", "Output clock"},
+        [2625] = {294, 43, "DEV_SERDES_16G2_IP4_LN1_TXFCLK", "Output clock"},
+        [2626] = {295, 40, "DEV_SERDES_16G3_CMN_REFCLK1_M_0", "Input clock"},
+        [2627] = {295, 0, "DEV_SERDES_16G3_CORE_REF1_CLK", "Input muxed clock"},
+        [2628] = {295, 1, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
+        [2629] = {295, 2, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
+        [2630] = {295, 3, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
+        [2631] = {295, 4, "DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK"},
+        [2632] = {295, 5, "DEV_SERDES_16G3_CLK", "Input clock"},
+        [2633] = {295, 51, "DEV_SERDES_16G3_CMN_REFCLK1_P_0", "Input clock"},
+        [2634] = {295, 6, "DEV_SERDES_16G3_IP2_LN1_TXCLK", "Input clock"},
+        [2635] = {295, 7, "DEV_SERDES_16G3_IP3_LN1_TXCLK", "Input clock"},
+        [2636] = {295, 8, "DEV_SERDES_16G3_IP2_LN0_TXCLK", "Input clock"},
+        [2637] = {295, 9, "DEV_SERDES_16G3_CORE_REF_CLK", "Input muxed clock"},
+        [2638] = {295, 10, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
+        [2639] = {295, 11, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
+        [2640] = {295, 12, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
+        [2641] = {295, 13, "DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK", "Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK"},
+        [2642] = {295, 16, "DEV_SERDES_16G3_IP3_LN1_TXFCLK", "Output clock"},
+        [2643] = {295, 17, "DEV_SERDES_16G3_IP2_LN1_REFCLK", "Output clock"},
+        [2644] = {295, 18, "DEV_SERDES_16G3_IP2_LN1_TXFCLK", "Output clock"},
+        [2645] = {295, 20, "DEV_SERDES_16G3_IP3_LN1_RXFCLK", "Output clock"},
+        [2646] = {295, 14, "DEV_SERDES_16G3_IP2_LN0_TXFCLK", "Output clock"},
+        [2647] = {295, 21, "DEV_SERDES_16G3_IP3_LN1_RXCLK", "Output clock"},
+        [2648] = {295, 22, "DEV_SERDES_16G3_IP3_LN1_REFCLK", "Output clock"},
+        [2649] = {295, 23, "DEV_SERDES_16G3_IP2_LN1_RXCLK", "Output clock"},
+        [2650] = {295, 24, "DEV_SERDES_16G3_IP2_LN0_RXFCLK", "Output clock"},
+        [2651] = {295, 25, "DEV_SERDES_16G3_REF_OUT_CLK", "Output clock"},
+        [2652] = {295, 26, "DEV_SERDES_16G3_REF1_OUT_CLK", "Output clock"},
+        [2653] = {295, 27, "DEV_SERDES_16G3_IP2_LN1_RXFCLK", "Output clock"},
+        [2654] = {295, 15, "DEV_SERDES_16G3_IP3_LN1_TXMCLK", "Output clock"},
+        [2655] = {295, 28, "DEV_SERDES_16G3_IP2_LN1_TXMCLK", "Output clock"},
+        [2656] = {295, 29, "DEV_SERDES_16G3_IP2_LN0_REFCLK", "Output clock"},
+        [2657] = {295, 30, "DEV_SERDES_16G3_IP2_LN0_TXMCLK", "Output clock"},
+        [2658] = {295, 31, "DEV_SERDES_16G3_IP2_LN0_RXCLK", "Output clock"},
+        [2659] = {29, 0, "DEV_STM0_VBUSP_CLK", "Input clock"},
+        [2660] = {29, 1, "DEV_STM0_CORE_CLK", "Input clock"},
+        [2661] = {29, 2, "DEV_STM0_ATB_CLK", "Input clock"},
+        [2662] = {49, 0, "DEV_TIMER0_TIMER_HCLK_CLK", "Input clock"},
+        [2663] = {49, 1, "DEV_TIMER0_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2664] = {49, 2, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2665] = {49, 3, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2666] = {49, 4, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2667] = {49, 5, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2668] = {49, 6, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2669] = {49, 7, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2670] = {49, 8, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2671] = {49, 9, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2672] = {49, 10, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2673] = {49, 11, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2674] = {49, 12, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2675] = {49, 13, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2676] = {49, 14, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2677] = {49, 15, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2678] = {49, 16, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2679] = {49, 17, "DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK"},
+        [2680] = {49, 18, "DEV_TIMER0_TIMER_PWM_0", "Output clock"},
+        [2681] = {50, 0, "DEV_TIMER1_TIMER_HCLK_CLK", "Input clock"},
+        [2682] = {50, 1, "DEV_TIMER1_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2683] = {50, 2, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+        [2684] = {50, 3, "DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM_0", "Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK"},
+        [2685] = {60, 0, "DEV_TIMER10_TIMER_HCLK_CLK", "Input clock"},
+        [2686] = {60, 1, "DEV_TIMER10_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2687] = {60, 2, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2688] = {60, 3, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2689] = {60, 4, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2690] = {60, 5, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2691] = {60, 6, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2692] = {60, 7, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2693] = {60, 8, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2694] = {60, 9, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2695] = {60, 10, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2696] = {60, 11, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2697] = {60, 12, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2698] = {60, 13, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2699] = {60, 14, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2700] = {60, 15, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2701] = {60, 16, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2702] = {60, 17, "DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK"},
+        [2703] = {60, 18, "DEV_TIMER10_TIMER_PWM_0", "Output clock"},
+        [2704] = {62, 0, "DEV_TIMER11_TIMER_HCLK_CLK", "Input clock"},
+        [2705] = {62, 1, "DEV_TIMER11_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2706] = {62, 2, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
+        [2707] = {62, 3, "DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM_0", "Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK"},
+        [2708] = {63, 0, "DEV_TIMER12_TIMER_HCLK_CLK", "Input clock"},
+        [2709] = {63, 1, "DEV_TIMER12_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2710] = {63, 2, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2711] = {63, 3, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2712] = {63, 4, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2713] = {63, 5, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2714] = {63, 6, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2715] = {63, 7, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2716] = {63, 8, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2717] = {63, 9, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2718] = {63, 10, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2719] = {63, 11, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2720] = {63, 12, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2721] = {63, 13, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2722] = {63, 14, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2723] = {63, 15, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2724] = {63, 16, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2725] = {63, 17, "DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK"},
+        [2726] = {63, 18, "DEV_TIMER12_TIMER_PWM_0", "Output clock"},
+        [2727] = {64, 0, "DEV_TIMER13_TIMER_HCLK_CLK", "Input clock"},
+        [2728] = {64, 1, "DEV_TIMER13_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2729] = {64, 2, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
+        [2730] = {64, 3, "DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM_0", "Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK"},
+        [2731] = {65, 0, "DEV_TIMER14_TIMER_HCLK_CLK", "Input clock"},
+        [2732] = {65, 1, "DEV_TIMER14_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2733] = {65, 2, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2734] = {65, 3, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2735] = {65, 4, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2736] = {65, 5, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2737] = {65, 6, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2738] = {65, 7, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2739] = {65, 8, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2740] = {65, 9, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2741] = {65, 10, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2742] = {65, 11, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2743] = {65, 12, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2744] = {65, 13, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2745] = {65, 14, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2746] = {65, 15, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2747] = {65, 16, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2748] = {65, 17, "DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK"},
+        [2749] = {65, 18, "DEV_TIMER14_TIMER_PWM_0", "Output clock"},
+        [2750] = {66, 0, "DEV_TIMER15_TIMER_HCLK_CLK", "Input clock"},
+        [2751] = {66, 1, "DEV_TIMER15_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2752] = {66, 2, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
+        [2753] = {66, 3, "DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM_0", "Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK"},
+        [2754] = {67, 0, "DEV_TIMER16_TIMER_HCLK_CLK", "Input clock"},
+        [2755] = {67, 1, "DEV_TIMER16_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2756] = {67, 2, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2757] = {67, 3, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2758] = {67, 4, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2759] = {67, 5, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2760] = {67, 6, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2761] = {67, 7, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2762] = {67, 8, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2763] = {67, 9, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2764] = {67, 10, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2765] = {67, 11, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2766] = {67, 12, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2767] = {67, 13, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2768] = {67, 14, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2769] = {67, 15, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2770] = {67, 16, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2771] = {67, 17, "DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK"},
+        [2772] = {67, 18, "DEV_TIMER16_TIMER_PWM_0", "Output clock"},
+        [2773] = {68, 0, "DEV_TIMER17_TIMER_HCLK_CLK", "Input clock"},
+        [2774] = {68, 1, "DEV_TIMER17_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2775] = {68, 2, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
+        [2776] = {68, 3, "DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM_0", "Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK"},
+        [2777] = {69, 0, "DEV_TIMER18_TIMER_HCLK_CLK", "Input clock"},
+        [2778] = {69, 1, "DEV_TIMER18_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2779] = {69, 2, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2780] = {69, 3, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2781] = {69, 4, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2782] = {69, 5, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2783] = {69, 6, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2784] = {69, 7, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2785] = {69, 8, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2786] = {69, 9, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2787] = {69, 10, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2788] = {69, 11, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2789] = {69, 12, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2790] = {69, 13, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2791] = {69, 14, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2792] = {69, 15, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2793] = {69, 16, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2794] = {69, 17, "DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK"},
+        [2795] = {69, 18, "DEV_TIMER18_TIMER_PWM_0", "Output clock"},
+        [2796] = {70, 0, "DEV_TIMER19_TIMER_HCLK_CLK", "Input clock"},
+        [2797] = {70, 1, "DEV_TIMER19_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2798] = {70, 2, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
+        [2799] = {70, 3, "DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM_0", "Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK"},
+        [2800] = {51, 0, "DEV_TIMER2_TIMER_HCLK_CLK", "Input clock"},
+        [2801] = {51, 1, "DEV_TIMER2_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2802] = {51, 2, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2803] = {51, 3, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2804] = {51, 4, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2805] = {51, 5, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2806] = {51, 6, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2807] = {51, 7, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2808] = {51, 8, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2809] = {51, 9, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2810] = {51, 10, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2811] = {51, 11, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2812] = {51, 12, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2813] = {51, 13, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2814] = {51, 14, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2815] = {51, 15, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2816] = {51, 16, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2817] = {51, 17, "DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK"},
+        [2818] = {51, 18, "DEV_TIMER2_TIMER_PWM_0", "Output clock"},
+        [2819] = {52, 0, "DEV_TIMER3_TIMER_HCLK_CLK", "Input clock"},
+        [2820] = {52, 1, "DEV_TIMER3_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2821] = {52, 2, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+        [2822] = {52, 3, "DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM_0", "Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK"},
+        [2823] = {53, 0, "DEV_TIMER4_TIMER_HCLK_CLK", "Input clock"},
+        [2824] = {53, 1, "DEV_TIMER4_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2825] = {53, 2, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2826] = {53, 3, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2827] = {53, 4, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2828] = {53, 5, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2829] = {53, 6, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2830] = {53, 7, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2831] = {53, 8, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2832] = {53, 9, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2833] = {53, 10, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2834] = {53, 11, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2835] = {53, 12, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2836] = {53, 13, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2837] = {53, 14, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2838] = {53, 15, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2839] = {53, 16, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2840] = {53, 17, "DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK"},
+        [2841] = {53, 18, "DEV_TIMER4_TIMER_PWM_0", "Output clock"},
+        [2842] = {54, 0, "DEV_TIMER5_TIMER_HCLK_CLK", "Input clock"},
+        [2843] = {54, 1, "DEV_TIMER5_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2844] = {54, 2, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+        [2845] = {54, 3, "DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM_0", "Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK"},
+        [2846] = {55, 0, "DEV_TIMER6_TIMER_HCLK_CLK", "Input clock"},
+        [2847] = {55, 1, "DEV_TIMER6_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2848] = {55, 2, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2849] = {55, 3, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2850] = {55, 4, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2851] = {55, 5, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2852] = {55, 6, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2853] = {55, 7, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2854] = {55, 8, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2855] = {55, 9, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2856] = {55, 10, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2857] = {55, 11, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2858] = {55, 12, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2859] = {55, 13, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2860] = {55, 14, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2861] = {55, 15, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2862] = {55, 16, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2863] = {55, 17, "DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK"},
+        [2864] = {55, 18, "DEV_TIMER6_TIMER_PWM_0", "Output clock"},
+        [2865] = {57, 0, "DEV_TIMER7_TIMER_HCLK_CLK", "Input clock"},
+        [2866] = {57, 1, "DEV_TIMER7_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2867] = {57, 2, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+        [2868] = {57, 3, "DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM_0", "Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK"},
+        [2869] = {58, 0, "DEV_TIMER8_TIMER_HCLK_CLK", "Input clock"},
+        [2870] = {58, 1, "DEV_TIMER8_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2871] = {58, 2, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2872] = {58, 3, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2873] = {58, 4, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2874] = {58, 5, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2875] = {58, 6, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2876] = {58, 7, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2877] = {58, 8, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2878] = {58, 9, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2879] = {58, 10, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2880] = {58, 11, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2881] = {58, 12, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2882] = {58, 13, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2883] = {58, 14, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2884] = {58, 15, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2885] = {58, 16, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0_0", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2886] = {58, 17, "DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK", "Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK"},
+        [2887] = {58, 18, "DEV_TIMER8_TIMER_PWM_0", "Output clock"},
+        [2888] = {59, 0, "DEV_TIMER9_TIMER_HCLK_CLK", "Input clock"},
+        [2889] = {59, 1, "DEV_TIMER9_TIMER_TCLK_CLK", "Input muxed clock"},
+        [2890] = {59, 2, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
+        [2891] = {59, 3, "DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM_0", "Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK"},
+        [2892] = {136, 0, "DEV_TIMESYNC_INTRTR0_INTR_CLK", "Input clock"},
+        [2893] = {146, 0, "DEV_UART0_FCLK_CLK", "Input clock"},
+        [2894] = {146, 1, "DEV_UART0_VBUSP_CLK", "Input clock"},
+        [2895] = {278, 0, "DEV_UART1_FCLK_CLK", "Input clock"},
+        [2896] = {278, 1, "DEV_UART1_VBUSP_CLK", "Input clock"},
+        [2897] = {279, 0, "DEV_UART2_FCLK_CLK", "Input clock"},
+        [2898] = {279, 1, "DEV_UART2_VBUSP_CLK", "Input clock"},
+        [2899] = {280, 0, "DEV_UART3_FCLK_CLK", "Input clock"},
+        [2900] = {280, 1, "DEV_UART3_VBUSP_CLK", "Input clock"},
+        [2901] = {281, 0, "DEV_UART4_FCLK_CLK", "Input clock"},
+        [2902] = {281, 1, "DEV_UART4_VBUSP_CLK", "Input clock"},
+        [2903] = {282, 0, "DEV_UART5_FCLK_CLK", "Input clock"},
+        [2904] = {282, 1, "DEV_UART5_VBUSP_CLK", "Input clock"},
+        [2905] = {283, 0, "DEV_UART6_FCLK_CLK", "Input clock"},
+        [2906] = {283, 1, "DEV_UART6_VBUSP_CLK", "Input clock"},
+        [2907] = {284, 0, "DEV_UART7_FCLK_CLK", "Input clock"},
+        [2908] = {284, 1, "DEV_UART7_VBUSP_CLK", "Input clock"},
+        [2909] = {285, 0, "DEV_UART8_FCLK_CLK", "Input clock"},
+        [2910] = {285, 1, "DEV_UART8_VBUSP_CLK", "Input clock"},
+        [2911] = {286, 0, "DEV_UART9_FCLK_CLK", "Input clock"},
+        [2912] = {286, 1, "DEV_UART9_VBUSP_CLK", "Input clock"},
+        [2913] = {277, 0, "DEV_UFS0_UFSHCI_HCLK_CLK", "Input clock"},
+        [2914] = {277, 1, "DEV_UFS0_UFSHCI_MCLK_CLK", "Input muxed clock"},
+        [2915] = {277, 2, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
+        [2916] = {277, 3, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
+        [2917] = {277, 4, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
+        [2918] = {277, 5, "DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT", "Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK"},
+        [2919] = {277, 6, "DEV_UFS0_UFSHCI_MPHY_REFCLK_0", "Output clock"},
+        [2920] = {288, 0, "DEV_USB0_PIPE_REFCLK", "Input muxed clock"},
+        [2921] = {288, 1, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
+        [2922] = {288, 2, "DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB0_PIPE_REFCLK"},
+        [2923] = {288, 3, "DEV_USB0_CLK_LPM_CLK", "Input clock"},
+        [2924] = {288, 4, "DEV_USB0_BUF_CLK", "Input clock"},
+        [2925] = {288, 5, "DEV_USB0_USB2_APB_PCLK_CLK", "Input clock"},
+        [2926] = {288, 6, "DEV_USB0_PIPE_RXCLK", "Input muxed clock"},
+        [2927] = {288, 7, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
+        [2928] = {288, 8, "DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB0_PIPE_RXCLK"},
+        [2929] = {288, 9, "DEV_USB0_PIPE_TXMCLK", "Input muxed clock"},
+        [2930] = {288, 10, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
+        [2931] = {288, 11, "DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB0_PIPE_TXMCLK"},
+        [2932] = {288, 12, "DEV_USB0_PIPE_RXFCLK", "Input muxed clock"},
+        [2933] = {288, 13, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
+        [2934] = {288, 14, "DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB0_PIPE_RXFCLK"},
+        [2935] = {288, 15, "DEV_USB0_USB2_REFCLOCK_CLK", "Input muxed clock"},
+        [2936] = {288, 16, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+        [2937] = {288, 17, "DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK"},
+        [2938] = {288, 18, "DEV_USB0_PCLK_CLK", "Input clock"},
+        [2939] = {288, 19, "DEV_USB0_ACLK_CLK", "Input clock"},
+        [2940] = {288, 20, "DEV_USB0_PIPE_TXFCLK", "Input muxed clock"},
+        [2941] = {288, 21, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
+        [2942] = {288, 22, "DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB0_PIPE_TXFCLK"},
+        [2943] = {288, 23, "DEV_USB0_PIPE_TXCLK", "Output clock"},
+        [2944] = {289, 0, "DEV_USB1_PIPE_REFCLK", "Input muxed clock"},
+        [2945] = {289, 1, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"},
+        [2946] = {289, 2, "DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK", "Parent input clock option to DEV_USB1_PIPE_REFCLK"},
+        [2947] = {289, 3, "DEV_USB1_CLK_LPM_CLK", "Input clock"},
+        [2948] = {289, 4, "DEV_USB1_BUF_CLK", "Input clock"},
+        [2949] = {289, 5, "DEV_USB1_USB2_APB_PCLK_CLK", "Input clock"},
+        [2950] = {289, 6, "DEV_USB1_PIPE_RXCLK", "Input muxed clock"},
+        [2951] = {289, 7, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"},
+        [2952] = {289, 8, "DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK", "Parent input clock option to DEV_USB1_PIPE_RXCLK"},
+        [2953] = {289, 9, "DEV_USB1_PIPE_TXMCLK", "Input muxed clock"},
+        [2954] = {289, 10, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"},
+        [2955] = {289, 11, "DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK", "Parent input clock option to DEV_USB1_PIPE_TXMCLK"},
+        [2956] = {289, 12, "DEV_USB1_PIPE_RXFCLK", "Input muxed clock"},
+        [2957] = {289, 13, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"},
+        [2958] = {289, 14, "DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK", "Parent input clock option to DEV_USB1_PIPE_RXFCLK"},
+        [2959] = {289, 15, "DEV_USB1_USB2_REFCLOCK_CLK", "Input muxed clock"},
+        [2960] = {289, 16, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
+        [2961] = {289, 17, "DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT", "Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK"},
+        [2962] = {289, 18, "DEV_USB1_PCLK_CLK", "Input clock"},
+        [2963] = {289, 19, "DEV_USB1_ACLK_CLK", "Input clock"},
+        [2964] = {289, 20, "DEV_USB1_PIPE_TXFCLK", "Input muxed clock"},
+        [2965] = {289, 21, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"},
+        [2966] = {289, 22, "DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK", "Parent input clock option to DEV_USB1_PIPE_TXFCLK"},
+        [2967] = {289, 23, "DEV_USB1_PIPE_TXCLK", "Output clock"},
+        [2968] = {291, 0, "DEV_VPFE0_CCD_PCLK_CLK", "Input clock"},
+        [2969] = {291, 1, "DEV_VPFE0_VPFE_CLK", "Input clock"},
+        [2970] = {145, 0, "DEV_WKUP_DDPA0_DDPA_CLK", "Input clock"},
+        [2971] = {99, 0, "DEV_WKUP_ESM0_CLK", "Input clock"},
+        [2972] = {113, 0, "DEV_WKUP_GPIO0_MMR_CLK", "Input clock"},
+        [2973] = {114, 0, "DEV_WKUP_GPIO1_MMR_CLK", "Input clock"},
+        [2974] = {137, 0, "DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK", "Input clock"},
+        [2975] = {197, 0, "DEV_WKUP_I2C0_PISYS_CLK", "Input muxed clock"},
+        [2976] = {197, 1, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
+        [2977] = {197, 2, "DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK"},
+        [2978] = {197, 3, "DEV_WKUP_I2C0_PISCL_0", "Input clock"},
+        [2979] = {197, 4, "DEV_WKUP_I2C0_CLK", "Input clock"},
+        [2980] = {197, 5, "DEV_WKUP_I2C0_PORSCL_0", "Output clock"},
+        [2981] = {132, 0, "DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK", "Input clock"},
+        [2982] = {138, 0, "DEV_WKUP_PSC0_SLOW_CLK", "Input clock"},
+        [2983] = {138, 1, "DEV_WKUP_PSC0_CLK", "Input clock"},
+        [2984] = {287, 0, "DEV_WKUP_UART0_FCLK_CLK", "Input muxed clock"},
+        [2985] = {287, 1, "DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
+        [2986] = {287, 2, "DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT", "Parent input clock option to DEV_WKUP_UART0_FCLK_CLK"},
+        [2987] = {287, 3, "DEV_WKUP_UART0_VBUSP_CLK", "Input clock"},
+        [2988] = {154, 0, "DEV_WKUP_VTM0_FIX_REF2_CLK", "Input clock"},
+        [2989] = {154, 1, "DEV_WKUP_VTM0_VBUSP_CLK", "Input clock"},
+        [2990] = {154, 2, "DEV_WKUP_VTM0_FIX_REF_CLK", "Input clock"},
+};